1.1 --- a/packages/devs/adc/cortexm/stm32/current/ChangeLog	Wed May 04 21:01:02 2011 +0000
     1.2 +++ b/packages/devs/adc/cortexm/stm32/current/ChangeLog	Thu May 05 06:51:37 2011 +0000
     1.3 @@ -1,3 +1,10 @@
     1.4 +2011-05-02  Christophe Coutand  <ecos@hotmail.co.uk>
     1.5 +
     1.6 +	* cdl/adc_stm32.cdl:
     1.7 +	* src/adc_stm32.c:
     1.8 +	Make sure DMA clock is enabled. Fix ADC clock divider not set in
     1.9 +	stm32_adc_init_clock.
    1.10 +
    1.11  2009-03-05  Simon Kallweit  <simon.kallweit@intefo.ch>
    1.12  
    1.13  	* src/adc_stm32.c:
    1.14 @@ -15,7 +22,7 @@
    1.15  // ####GPLCOPYRIGHTBEGIN####                                                
    1.16  // -------------------------------------------                              
    1.17  // This file is part of eCos, the Embedded Configurable Operating System.   
    1.18 -// Copyright (C) 2009 Free Software Foundation, Inc.                        
    1.19 +// Copyright (C) 2009, 2011 Free Software Foundation, Inc.                  
    1.20  //
    1.21  // This program is free software; you can redistribute it and/or modify     
    1.22  // it under the terms of the GNU General Public License as published by     

     2.1 --- a/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl	Wed May 04 21:01:02 2011 +0000
     2.2 +++ b/packages/devs/adc/cortexm/stm32/current/cdl/adc_stm32.cdl	Thu May 05 06:51:37 2011 +0000
     2.3 @@ -8,7 +8,7 @@
     2.4  ## ####ECOSGPLCOPYRIGHTBEGIN####                                            
     2.5  ## -------------------------------------------                              
     2.6  ## This file is part of eCos, the Embedded Configurable Operating System.   
     2.7 -## Copyright (C) 2009 Free Software Foundation, Inc.                        
     2.8 +## Copyright (C) 2009, 2011 Free Software Foundation, Inc                   
     2.9  ##
    2.10  ## eCos is free software; you can redistribute it and/or modify it under    
    2.11  ## the terms of the GNU General Public License as published by the Free     
    2.12 @@ -63,18 +63,23 @@
    2.13             
    2.14      include_dir cyg/io
    2.15      compile     -library=libextras.a adc_stm32.c
    2.16 -    
    2.17 +
    2.18 +    cdl_option CYGPKG_DEVS_ADC_CORTEXM_STM32_TRACE {
    2.19 +        display       "ADC driver tracing"
    2.20 +        flavor        bool
    2.21 +        default_value 0
    2.22 +        description   "
    2.23 +            Enable tracing of the ADC driver. Select to debug the driver."
    2.24 +    }
    2.25 +
    2.26      cdl_option CYGNUM_DEVS_ADC_CORTEXM_STM32_CLOCK_DIV {
    2.27           display        "ADC clock divider"
    2.28           flavor         data
    2.29           legal_values   { 2 4 6 8 }
    2.30           default_value  8
    2.31           description    "
    2.32 -             This option specifies the level of debug data output by
    2.33 -             the STM32 ADC device driver. A value of 0 signifies
    2.34 -             no debug data output; 1 signifies normal debug data
    2.35 -             output. If an overrun occurred then this can only be
    2.36 -             detected by debug output messages."         
    2.37 +             This option specifies the ADC clock divider value. The 
    2.38 +             ADC clock frequency is defined as PCLK2 / ADC divider. "
    2.39      }
    2.40      
    2.41      cdl_component CYGHWR_DEVS_ADC_CORTEXM_STM32_ADC1 {

     3.1 --- a/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c	Wed May 04 21:01:02 2011 +0000
     3.2 +++ b/packages/devs/adc/cortexm/stm32/current/src/adc_stm32.c	Thu May 05 06:51:37 2011 +0000
     3.3 @@ -8,7 +8,7 @@
     3.4  // ####ECOSGPLCOPYRIGHTBEGIN####                                            
     3.5  // -------------------------------------------                              
     3.6  // This file is part of eCos, the Embedded Configurable Operating System.   
     3.7 -// Copyright (C) 2009 Free Software Foundation, Inc.                        
     3.8 +// Copyright (C) 2009, 2011 Free Software Foundation, Inc.
     3.9  //
    3.10  // eCos is free software; you can redistribute it and/or modify it under    
    3.11  // the terms of the GNU General Public License as published by the Free     
    3.12 @@ -64,11 +64,11 @@
    3.13  // Diagnostic support
    3.14  // Switch the #if to 1 to generate some diagnostic messages.
    3.15  
    3.16 -#if 0
    3.17 -#include <cyg/infra/diag.h>
    3.18 -#define adc_diag( __fmt, ... ) diag_printf("ADC: %30s[%4d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
    3.19 +#ifdef CYGPKG_DEVS_ADC_CORTEXM_STM32_TRACE
    3.20 +# include <cyg/infra/diag.h>
    3.21 +# define adc_diag( __fmt, ... ) diag_printf("ADC: %30s[%4d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ );
    3.22  #else
    3.23 -#define adc_diag( __fmt, ... ) 
    3.24 +# define adc_diag( __fmt, ... ) 
    3.25  #endif
    3.26  
    3.27  
    3.28 @@ -432,7 +432,7 @@
    3.29      adc_clock = hal_stm32_pclk2 / 8;
    3.30  #endif
    3.31  
    3.32 -    HAL_READ_UINT32(rcc + CYGHWR_HAL_STM32_RCC_CFGR, cfgr);
    3.33 +    HAL_WRITE_UINT32(rcc + CYGHWR_HAL_STM32_RCC_CFGR, cfgr);
    3.34  }
    3.35  
    3.36  //-----------------------------------------------------------------------------
    3.37 @@ -446,6 +446,8 @@
    3.38      cyg_uint64 tmp;
    3.39      cyg_uint32 cycles;
    3.40      cyg_uint32 smpr;
    3.41 +    cyg_uint32 rcc_base = CYGHWR_HAL_STM32_RCC;
    3.42 +    cyg_uint32 reg_data;
    3.43      int i;
    3.44      
    3.45      static const cyg_uint32 cycles_table[] = 
    3.46 @@ -470,7 +472,7 @@
    3.47      } while (cr & CYGHWR_HAL_STM32_ADC_CR2_CAL);
    3.48      
    3.49      // Power off ADC 
    3.50 -    cr &= CYGHWR_HAL_STM32_ADC_CR2_ADON;
    3.51 +    cr &= ~CYGHWR_HAL_STM32_ADC_CR2_ADON;
    3.52      HAL_WRITE_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR2, cr);
    3.53      
    3.54      // Enable external triggering and DMA
    3.55 @@ -494,6 +496,14 @@
    3.56      
    3.57  
    3.58      // Setup DMA channel
    3.59 +    // Ensure that the DMA clocks are enabled.
    3.60 +    HAL_READ_UINT32 (rcc_base + CYGHWR_HAL_STM32_RCC_AHBENR, reg_data);
    3.61 +    if (info->setup->dma_base == CYGHWR_HAL_STM32_DMA1)
    3.62 +      reg_data |= CYGHWR_HAL_STM32_RCC_AHBENR_DMA1;
    3.63 +    else
    3.64 +      reg_data |= CYGHWR_HAL_STM32_RCC_AHBENR_DMA2;
    3.65 +    HAL_WRITE_UINT32 (rcc_base + CYGHWR_HAL_STM32_RCC_AHBENR, reg_data);
    3.66 +
    3.67      HAL_WRITE_UINT32(info->setup->dma_base + 
    3.68                       CYGHWR_HAL_STM32_DMA_CPAR(info->setup->dma_channel),
    3.69                       info->setup->adc_base + CYGHWR_HAL_STM32_ADC_DR);
    3.70 @@ -557,7 +567,7 @@
    3.71      cyg_uint32 sqr2 = 0;
    3.72      cyg_uint32 sqr3 = 0;
    3.73      
    3.74 -    adc_diag("Updateing regular group\n");
    3.75 +    adc_diag("Updating regular group\n");
    3.76      
    3.77      // Disable ADC
    3.78      HAL_READ_UINT32(info->setup->adc_base + CYGHWR_HAL_STM32_ADC_CR2, cr);