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comparison packages/hal/mips/arch/current/include/hal_cache.h @ 18:7253dcc42a09 ecos-sw-1999-06-25

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Merge from eCos master repository on 1999-06-25-15:31:50-BST
author jlarmour
date Fri, 25 Jun 1999 08:28:05 +0000
parents d3fbcdfa1b2f
children 306eee292492
comparison
equal deleted inserted replaced
17:a658ec000d9f 18:7253dcc42a09
106 #endif 106 #endif
107 107
108 // Synchronize the contents of the cache with memory. 108 // Synchronize the contents of the cache with memory.
109 // This uses the index-writeback-invalidate operation. 109 // This uses the index-writeback-invalidate operation.
110 #ifndef HAL_DCACHE_SYNC_DEFINED 110 #ifndef HAL_DCACHE_SYNC_DEFINED
111 #define HAL_DCACHE_SYNC() \ 111 #define HAL_DCACHE_SYNC() \
112 { \ 112 { \
113 register CYG_ADDRESS _baddr_ = 0x80000000; \ 113 register CYG_ADDRESS _baddr_ = 0x80000000; \
114 register CYG_ADDRESS _addr_ = 0x80000000; \ 114 register CYG_ADDRESS _addr_ = 0x80000000; \
115 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ 115 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
116 register CYG_WORD _state_; \ 116 register CYG_WORD _state_; \
117 HAL_DCACHE_IS_ENABLED(_state_); \ 117 HAL_DCACHE_IS_ENABLED( _state_ ); \
118 HAL_DCACHE_DISABLE(); \ 118 if( _state_ ) \
119 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 119 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
120 { \ 120 { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \
121 asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \
122 } \
123 if( _state_ ) HAL_DCACHE_ENABLE(); \
124 } 121 }
125 #endif 122 #endif
126 123
127 // Set the data cache refill burst size 124 // Set the data cache refill burst size
128 //#define HAL_DCACHE_BURST_SIZE(_size_) 125 //#define HAL_DCACHE_BURST_SIZE(_size_)
135 132
136 // Load the contents of the given address range into the data cache 133 // Load the contents of the given address range into the data cache
137 // and then lock the cache so that it stays there. 134 // and then lock the cache so that it stays there.
138 // This uses the fetch-and-lock cache operation. 135 // This uses the fetch-and-lock cache operation.
139 #ifndef HAL_DCACHE_LOCK_DEFINED 136 #ifndef HAL_DCACHE_LOCK_DEFINED
140 #define HAL_DCACHE_LOCK(_base_, _asize_) \ 137 #define HAL_DCACHE_LOCK(_base_, _asize_) \
141 CYG_MACRO_START \ 138 CYG_MACRO_START \
142 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 139 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
143 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 140 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
144 register CYG_WORD _size_ = (_asize_); \ 141 register CYG_WORD _size_ = (_asize_); \
145 register CYG_WORD _state_; \ 142 register CYG_WORD _state_; \
146 HAL_DCACHE_IS_ENABLED(_state_); \ 143 HAL_DCACHE_IS_ENABLED( _state_ ); \
147 HAL_DCACHE_DISABLE(); \ 144 if( _state_ ) \
148 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 145 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
149 { \ 146 { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \
150 asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \
151 } \
152 if( _state_ ) HAL_DCACHE_ENABLE(); \
153 CYG_MACRO_END 147 CYG_MACRO_END
154 #endif 148 #endif
155 149
156 // Undo a previous lock operation. 150 // Undo a previous lock operation.
157 // Do this by flushing the cache, which is defined to clear the lock bit. 151 // Do this by flushing the cache, which is defined to clear the lock bit.
175 169
176 // Write dirty cache lines to memory and invalidate the cache entries 170 // Write dirty cache lines to memory and invalidate the cache entries
177 // for the given address range. 171 // for the given address range.
178 // This uses the hit-writeback-invalidate cache operation. 172 // This uses the hit-writeback-invalidate cache operation.
179 #ifndef HAL_DCACHE_FLUSH_DEFINED 173 #ifndef HAL_DCACHE_FLUSH_DEFINED
180 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ 174 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
181 { \ 175 { \
182 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 176 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
183 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 177 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
184 register CYG_WORD _size_ = (_asize_); \ 178 register CYG_WORD _size_ = (_asize_); \
185 register CYG_WORD _state_; \ 179 register CYG_WORD _state_; \
186 HAL_DCACHE_IS_ENABLED(_state_); \ 180 HAL_DCACHE_IS_ENABLED( _state_ ); \
187 HAL_DCACHE_DISABLE(); \ 181 if( _state_ ) \
188 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 182 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
189 { \ 183 { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \
190 asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \
191 } \
192 if( _state_ ) HAL_DCACHE_ENABLE(); \
193 } 184 }
194 #endif 185 #endif
195 186
196 // Invalidate cache lines in the given range without writing to memory. 187 // Invalidate cache lines in the given range without writing to memory.
197 // This uses the hit-invalidate cache operation. 188 // This uses the hit-invalidate cache operation.
198 #ifndef HAL_DCACHE_INVALIDATE_DEFINED 189 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
199 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ 190 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
200 { \ 191 { \
201 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 192 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
202 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 193 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
203 register CYG_WORD _size_ = (_asize_); \ 194 register CYG_WORD _size_ = (_asize_); \
204 register CYG_WORD _state_; \ 195 register CYG_WORD _state_; \
205 HAL_DCACHE_IS_ENABLED(_state_); \ 196 HAL_DCACHE_IS_ENABLED( _state_ ); \
206 HAL_DCACHE_DISABLE(); \ 197 if( _state_ ) \
207 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 198 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
208 { \ 199 { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \
209 asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \
210 } \
211 if( _state_ ) HAL_DCACHE_ENABLE(); \
212 } 200 }
213 #endif 201 #endif
214 202
215 // Write dirty cache lines to memory for the given address range. 203 // Write dirty cache lines to memory for the given address range.
216 // This uses the hit-writeback cache operation. 204 // This uses the hit-writeback cache operation.
217 #ifndef HAL_DCACHE_STORE_DEFINED 205 #ifndef HAL_DCACHE_STORE_DEFINED
218 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \ 206 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
219 { \ 207 { \
220 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 208 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
221 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 209 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
222 register CYG_WORD _size_ = (_asize_); \ 210 register CYG_WORD _size_ = (_asize_); \
223 register CYG_WORD _state_; \ 211 register CYG_WORD _state_; \
224 HAL_DCACHE_IS_ENABLED(_state_); \ 212 HAL_DCACHE_IS_ENABLED( _state_ ); \
225 HAL_DCACHE_DISABLE(); \ 213 if( _state_ ) \
226 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 214 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
227 { \ 215 { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \
228 asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \
229 } \
230 if( _state_ ) HAL_DCACHE_ENABLE(); \
231 } 216 }
232 #endif 217 #endif
233 218
234 // Preread the given range into the cache with the intention of reading 219 // Preread the given range into the cache with the intention of reading
235 // from it later. 220 // from it later.
261 #endif 246 #endif
262 247
263 // Invalidate the entire cache 248 // Invalidate the entire cache
264 // This uses the index-invalidate cache operation. 249 // This uses the index-invalidate cache operation.
265 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED 250 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
266 #define HAL_ICACHE_INVALIDATE_ALL() \ 251 #define HAL_ICACHE_INVALIDATE_ALL() \
267 { \ 252 { \
268 register CYG_ADDRESS _baddr_ = 0x80000000; \ 253 register CYG_ADDRESS _baddr_ = 0x80000000; \
269 register CYG_ADDRESS _addr_ = 0x80000000; \ 254 register CYG_ADDRESS _addr_ = 0x80000000; \
270 register CYG_WORD _state_; \ 255 register CYG_WORD _state_; \
271 HAL_ICACHE_IS_ENABLED(_state_); \ 256 HAL_ICACHE_IS_ENABLED( _state_ ); \
272 HAL_ICACHE_DISABLE(); \ 257 if( _state_ ) \
273 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 258 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
274 { \ 259 { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \
275 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
276 } \
277 if( _state_ ) HAL_ICACHE_ENABLE(); \
278 } 260 }
279 #endif 261 #endif
280 262
281 // Synchronize the contents of the cache with memory. 263 // Synchronize the contents of the cache with memory.
282 // Simply force the cache to reload. 264 // Simply force the cache to reload.
289 271
290 // Load the contents of the given address range into the instruction cache 272 // Load the contents of the given address range into the instruction cache
291 // and then lock the cache so that it stays there. 273 // and then lock the cache so that it stays there.
292 // This uses the fetch-and-lock cache operation. 274 // This uses the fetch-and-lock cache operation.
293 #ifndef HAL_ICACHE_LOCK_DEFINED 275 #ifndef HAL_ICACHE_LOCK_DEFINED
294 #define HAL_ICACHE_LOCK(_base_, _asize_) \ 276 #define HAL_ICACHE_LOCK(_base_, _asize_) \
295 CYG_MACRO_START \ 277 CYG_MACRO_START \
296 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 278 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
297 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 279 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
298 register CYG_WORD _size_ = (_asize_); \ 280 register CYG_WORD _size_ = (_asize_); \
299 register CYG_WORD _state_; \ 281 register CYG_WORD _state_; \
300 HAL_ICACHE_IS_ENABLED(_state_); \ 282 HAL_ICACHE_IS_ENABLED( _state_ ); \
301 HAL_ICACHE_DISABLE(); \ 283 if( _state_ ) \
302 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 284 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
303 { \ 285 { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \
304 asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \
305 } \
306 if( _state_ ) HAL_ICACHE_ENABLE(); \
307 CYG_MACRO_END 286 CYG_MACRO_END
308 #endif 287 #endif
309 288
310 // Undo a previous lock operation. 289 // Undo a previous lock operation.
311 // Do this by invalidating the cache, which is defined to clear the lock bit. 290 // Do this by invalidating the cache, which is defined to clear the lock bit.
321 // Instruction cache line control 300 // Instruction cache line control
322 301
323 // Invalidate cache lines in the given range without writing to memory. 302 // Invalidate cache lines in the given range without writing to memory.
324 // This uses the hit-invalidate cache operation. 303 // This uses the hit-invalidate cache operation.
325 #ifndef HAL_ICACHE_INVALIDATE_DEFINED 304 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
326 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ 305 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
327 { \ 306 { \
328 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 307 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
329 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 308 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
330 register CYG_WORD _size_ = (_asize_); \ 309 register CYG_WORD _size_ = (_asize_); \
331 register CYG_WORD _state_; \ 310 register CYG_WORD _state_; \
332 HAL_ICACHE_IS_ENABLED(_state_); \ 311 HAL_ICACHE_IS_ENABLED( _state_ ); \
333 HAL_ICACHE_DISABLE(); \ 312 if( _state_ ) \
334 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 313 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
335 { \ 314 { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \
336 asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \
337 } \
338 HAL_ICACHE_ENABLE(); \
339 } 315 }
340 #endif 316 #endif
341 317
342 //----------------------------------------------------------------------------- 318 //-----------------------------------------------------------------------------
343 // Check that a supported configuration has actually defined some macros. 319 // Check that a supported configuration has actually defined some macros.