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comparison packages/hal/mips/arch/current/include/hal_cache.h @ 1656:ea74d0ea9eb1

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* include/hal_cache.h: Changed the calculation of _IWAY and _DWAY for the case where HAL_MIPS_CACHE_INSN_USES_LSB is set to only affect the LSBs in the CACHE instruction offset field. #define MIPS cache ops and use them instead of constants in the HAL_?CACHE_* macros below.
author jlarmour
date Thu, 27 May 2004 06:26:53 +0000
parents bac0bf105669
children
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equal deleted inserted replaced
1655:ca8bb447fe5f 1656:ea74d0ea9eb1
97 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) 97 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
98 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) 98 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
99 99
100 #endif 100 #endif
101 101
102 // Defines for various R4000+ MIPS cache operations
103 // this is a 5 bit field with bits 4-2 defining the operation
104 // and bits 1-0 defining which cache is being operated on
105 #define HAL_MIPS_CACHE_INDEX_INVALIDATE_I 0x00 /* 0 0 */
106 #define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D 0x01 /* 0 1 */
107 #define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_S 0x03 /* 0 3 */
108 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_I 0x04 /* 1 0 */
109 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_D 0x05 /* 1 1 */
110 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_S 0x07 /* 1 3 */
111 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_I 0x08 /* 2 0 */
112 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_D 0x09 /* 2 1 */
113 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_S 0x0b /* 2 3 */
114 #define HAL_MIPS_CACHE_HIT_INVALIDATE_I 0x10 /* 4 0 */
115 #define HAL_MIPS_CACHE_HIT_INVALIDATE_D 0x11 /* 4 1 */
116 #define HAL_MIPS_CACHE_HIT_INVALIDATE_S 0x13 /* 4 3 */
117 #define HAL_MIPS_CACHE_FILL_I 0x14 /* 5 0 */
118 #define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D 0x15 /* 5 1 */
119 #define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_S 0x17 /* 5 3 */
120
121 // there seems to be different uses for operation
122 // code 6 depending on CPU
123 #define HAL_MIPS_CACHE_HIT_WRITEBACK_D 0x19 /* 6 1 */
124
125 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_I 0x18 /* 6 0 */
126 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_D 0x19 /* 6 1 */
127 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_S 0x1b /* 6 3 */
128
129 // there seems to be different uses for operation
130 // code 7 depending on CPU
131 #define HAL_MIPS_CACHE_FETCH_AND_LOCK_I 0x1c /* 7 0 */
132 #define HAL_MIPS_CACHE_FETCH_AND_LOCK_D 0x1d /* 7 1 */
133
134 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_I 0x1c /* 7 0 */
135 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_D 0x1d /* 7 1 */
136 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_S 0x1f /* 7 3 */
137
138
102 //----------------------------------------------------------------------------- 139 //-----------------------------------------------------------------------------
103 // Cache instruction uses LSBs or MSBs (depending on the 140 // Cache instruction uses LSBs or MSBs (depending on the
104 // implementation) of the virtual address to specify which WAY to 141 // implementation) of the virtual address to specify which WAY to
105 // affect. The _ALL_WAYS macro defines the necessary cache instructions 142 // affect. The _ALL_WAYS macro defines the necessary cache instructions
106 // to affect all ways. 143 // to affect all ways.
107 144
108 #ifdef HAL_MIPS_CACHE_INSN_USES_LSB 145 #ifdef HAL_MIPS_CACHE_INSN_USES_LSB
109 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS+(_n_)) 146 # define _IWAY(_n_) (_n_)
110 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS+(_n_)) 147 # define _DWAY(_n_) (_n_)
111 #else 148 #else
112 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS) 149 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS)
113 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS) 150 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS)
114 #endif 151 #endif
115 152
212 register CYG_ADDRESS _baddr_ = 0x80000000; \ 249 register CYG_ADDRESS _baddr_ = 0x80000000; \
213 register CYG_ADDRESS _addr_ = 0x80000000; \ 250 register CYG_ADDRESS _addr_ = 0x80000000; \
214 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ 251 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
215 _HAL_ASM_SET_MIPS_ISA(3); \ 252 _HAL_ASM_SET_MIPS_ISA(3); \
216 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 253 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
217 { _HAL_ASM_DCACHE_ALL_WAYS(0x01, _addr_); } \ 254 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D, _addr_); } \
218 _HAL_ASM_SET_MIPS_ISA(0); \ 255 _HAL_ASM_SET_MIPS_ISA(0); \
219 CYG_MACRO_END 256 CYG_MACRO_END
220 #endif 257 #endif
221 258
222 // Set the data cache refill burst size 259 // Set the data cache refill burst size
239 register CYG_WORD _state_; \ 276 register CYG_WORD _state_; \
240 HAL_DCACHE_IS_ENABLED( _state_ ); \ 277 HAL_DCACHE_IS_ENABLED( _state_ ); \
241 if( _state_ ) { \ 278 if( _state_ ) { \
242 _HAL_ASM_SET_MIPS_ISA(3); \ 279 _HAL_ASM_SET_MIPS_ISA(3); \
243 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 280 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
244 { _HAL_ASM_DCACHE_ALL_WAYS(0x1d, _addr_); } \ 281 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_D, _addr_); } \
245 _HAL_ASM_SET_MIPS_ISA(0); \ 282 _HAL_ASM_SET_MIPS_ISA(0); \
246 } \ 283 } \
247 CYG_MACRO_END 284 CYG_MACRO_END
248 #endif 285 #endif
249 286
278 register CYG_WORD _state_; \ 315 register CYG_WORD _state_; \
279 HAL_DCACHE_IS_ENABLED( _state_ ); \ 316 HAL_DCACHE_IS_ENABLED( _state_ ); \
280 if( _state_ ) { \ 317 if( _state_ ) { \
281 _HAL_ASM_SET_MIPS_ISA(3); \ 318 _HAL_ASM_SET_MIPS_ISA(3); \
282 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 319 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
283 { _HAL_ASM_DCACHE_ALL_WAYS(0x15, _addr_); } \ 320 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D, _addr_); } \
284 _HAL_ASM_SET_MIPS_ISA(0); \ 321 _HAL_ASM_SET_MIPS_ISA(0); \
285 } \ 322 } \
286 CYG_MACRO_END 323 CYG_MACRO_END
287 #endif 324 #endif
288 325
293 CYG_MACRO_START \ 330 CYG_MACRO_START \
294 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \ 331 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
295 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \ 332 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
296 _HAL_ASM_SET_MIPS_ISA(3); \ 333 _HAL_ASM_SET_MIPS_ISA(3); \
297 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 334 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
298 { _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); } \ 335 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_D, _addr_); } \
299 _HAL_ASM_SET_MIPS_ISA(0); \ 336 _HAL_ASM_SET_MIPS_ISA(0); \
300 CYG_MACRO_END 337 CYG_MACRO_END
301 #endif 338 #endif
302 339
303 // Write dirty cache lines to memory for the given address range. 340 // Write dirty cache lines to memory for the given address range.
310 register CYG_WORD _state_; \ 347 register CYG_WORD _state_; \
311 HAL_DCACHE_IS_ENABLED( _state_ ); \ 348 HAL_DCACHE_IS_ENABLED( _state_ ); \
312 if( _state_ ) { \ 349 if( _state_ ) { \
313 _HAL_ASM_SET_MIPS_ISA(3); \ 350 _HAL_ASM_SET_MIPS_ISA(3); \
314 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 351 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
315 { _HAL_ASM_DCACHE_ALL_WAYS(0x19, _addr_); } \ 352 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_D, _addr_); } \
316 _HAL_ASM_SET_MIPS_ISA(0); \ 353 _HAL_ASM_SET_MIPS_ISA(0); \
317 } \ 354 } \
318 CYG_MACRO_END 355 CYG_MACRO_END
319 #endif 356 #endif
320 357
354 CYG_MACRO_START \ 391 CYG_MACRO_START \
355 register CYG_ADDRESS _baddr_ = 0x80000000; \ 392 register CYG_ADDRESS _baddr_ = 0x80000000; \
356 register CYG_ADDRESS _addr_ = 0x80000000; \ 393 register CYG_ADDRESS _addr_ = 0x80000000; \
357 _HAL_ASM_SET_MIPS_ISA(3); \ 394 _HAL_ASM_SET_MIPS_ISA(3); \
358 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 395 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
359 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \ 396 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_INVALIDATE_I, _addr_); } \
360 _HAL_ASM_SET_MIPS_ISA(0); \ 397 _HAL_ASM_SET_MIPS_ISA(0); \
361 CYG_MACRO_END 398 CYG_MACRO_END
362 #endif 399 #endif
363 400
364 // Synchronize the contents of the cache with memory. 401 // Synchronize the contents of the cache with memory.
381 register CYG_WORD _state_; \ 418 register CYG_WORD _state_; \
382 HAL_ICACHE_IS_ENABLED( _state_ ); \ 419 HAL_ICACHE_IS_ENABLED( _state_ ); \
383 if( _state_ ) { \ 420 if( _state_ ) { \
384 _HAL_ASM_SET_MIPS_ISA(3); \ 421 _HAL_ASM_SET_MIPS_ISA(3); \
385 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 422 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
386 { _HAL_ASM_ICACHE_ALL_WAYS(0x1c, _addr_); } \ 423 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_I, _addr_); } \
387 _HAL_ASM_SET_MIPS_ISA(0); \ 424 _HAL_ASM_SET_MIPS_ISA(0); \
388 } \ 425 } \
389 CYG_MACRO_END 426 CYG_MACRO_END
390 #endif 427 #endif
391 428
409 CYG_MACRO_START \ 446 CYG_MACRO_START \
410 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \ 447 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
411 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \ 448 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
412 _HAL_ASM_SET_MIPS_ISA(3); \ 449 _HAL_ASM_SET_MIPS_ISA(3); \
413 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 450 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
414 { _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); } \ 451 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_I, _addr_); } \
415 _HAL_ASM_SET_MIPS_ISA(0); \ 452 _HAL_ASM_SET_MIPS_ISA(0); \
416 CYG_MACRO_END 453 CYG_MACRO_END
417 #endif 454 #endif
418 455
419 //----------------------------------------------------------------------------- 456 //-----------------------------------------------------------------------------