# HG changeset patch # User gthomas # Date 1067330870 0 # Node ID 0e2485da1dbcc1caaafae3224c5afe054dc6653c # Parent 2c334e9015ab55ec49eee9ec9231081cd5e3438f Fix problem with [re]enable of FPU during interrupts diff --git a/packages/hal/powerpc/arch/current/ChangeLog b/packages/hal/powerpc/arch/current/ChangeLog --- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -1,3 +1,8 @@ +2003-10-28 Gary Thomas + + * src/vectors.S: Revert change to interrupt handling (see below) which + was over-exuberant on platforms without MMU (but with FP). + 2003-09-19 Gary Thomas * src/vectors.S: Respect initial MMU settings when handling interrupts diff --git a/packages/hal/powerpc/arch/current/src/vectors.S b/packages/hal/powerpc/arch/current/src/vectors.S --- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -379,13 +379,13 @@ 2: bl hal_platform_init # MMU and cache are controlled by the same option since caching - # on the PPC does not make sense without the MMU to mark regions - # which should not be cached. + # on the PPC [typically] does not make sense without the MMU to mark + # regions which should not be cached. #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU # Initialize MMU. bl hal_MMU_init - # Enable MMU so we can safely enable caches. + # Enable MMU (if desired) so we can safely enable caches. lwi r3,CYG_MSR # interrupts enabled later sync mtmsr r3 @@ -474,13 +474,11 @@ cyg_hal_default_exception_vsr: stw r3,CYGARC_PPCREG_WALL_TAIL(sp) #endif -#ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU - # Enable MMU. + # Enable MMU & interrupt/FPU environment (as configured) lwi r3,CYG_MSR sync mtmsr r3 sync -#endif mfspr r3,SPRG1 # save original R3 stw r3,CYGARC_PPCREG_REGS+3*4(sp) @@ -623,13 +621,11 @@ cyg_hal_default_interrupt_vsr: stw r3,CYGARC_PPCREG_WALL_TAIL(sp) #endif -#ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU - # Enable MMU. + # Enable MMU & interrupt/FPU environment as configured lwi r3,CYG_MSR sync mtmsr r3 sync -#endif mfspr r3,SPRG1 # save original R3 stw r3,CYGARC_PPCREG_REGS+3*4(sp)