Mercurial > flash_v2
annotate packages/hal/arm/aeb/current/include/hal_cache.h @ 44:41bd4f3a90de ecos-sw-1999-10-08
Merge from eCos master repository on 1999-10-08-07:47:04-BST
| author | jlarmour |
|---|---|
| date | Fri, 08 Oct 1999 13:16:25 +0000 |
| parents | 443894e2e912 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 2 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 29 // ------------------------------------------- | |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 32 //============================================================================= | |
| 33 //#####DESCRIPTIONBEGIN#### | |
| 34 // | |
| 35 // Author(s): nickg, gthomas | |
| 36 // Contributors: nickg, gthomas | |
| 37 // Date: 1998-09-28 | |
| 38 // Purpose: Cache control API | |
| 39 // Description: The macros defined here provide the HAL APIs for handling | |
| 40 // cache control operations. | |
| 41 // Usage: | |
| 42 // #include <cyg/hal/hal_cache.h> | |
| 43 // ... | |
| 44 // | |
| 45 // | |
| 46 //####DESCRIPTIONEND#### | |
| 47 // | |
| 48 //============================================================================= | |
| 49 | |
| 50 #include <cyg/infra/cyg_type.h> | |
| 51 #include <cyg/hal/hal_io.h> | |
| 52 | |
| 53 //----------------------------------------------------------------------------- | |
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54 // Cache dimensions - one unified cache |
| 2 | 55 |
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56 #define HAL_CACHE_UNIFIED |
| 2 | 57 |
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58 #define HAL_UCACHE_SIZE 0x800 // Size of cache in bytes |
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59 #define HAL_UCACHE_LINE_SIZE 4 // Size of a cache line |
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60 #define HAL_UCACHE_WAYS 4 // Associativity of the cache |
| 2 | 61 |
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62 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) |
| 2 | 63 |
| 64 // Cache & SRAM control | |
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65 #define CYG_DEVICE_CCR 0xFFFFA400 |
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66 #define CYG_DEVICE_LSCR 0xFFFFA404 |
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67 #define CYG_DEVICE_CACHE_MEM 0x60000800 |
| 2 | 68 |
| 69 #define CCR_E 0x01 // Cache enabled | |
| 70 #define CCR_S 0x02 // SRAM mode enabled | |
| 71 #define CCR_F 0x04 // Flush mode enabled | |
| 72 #define CCR_I 0x08 // Invalidate mode | |
| 73 | |
| 74 #define LCSR_E 0x01 // Local SRAM enabled | |
| 75 #define LCSR_L 0x02 // Local SRAM mapped to high memory | |
| 76 | |
| 77 //----------------------------------------------------------------------------- | |
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78 // Global control of cache |
| 2 | 79 |
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80 // Enable the cache |
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81 #define HAL_UCACHE_ENABLE() \ |
| 2 | 82 { \ |
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83 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_E); \ |
| 2 | 84 } |
| 85 | |
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86 // Disable the cache |
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87 #define HAL_UCACHE_DISABLE() \ |
| 2 | 88 { \ |
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89 HAL_WRITE_UINT8(CYG_DEVICE_CCR, 0); \ |
| 2 | 90 } |
| 91 | |
| 92 // Invalidate the entire cache | |
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93 #define HAL_UCACHE_INVALIDATE_ALL() \ |
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94 { \ |
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95 register cyg_uint8 old_ccr; \ |
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96 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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97 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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98 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
| 2 | 99 } |
| 100 | |
| 101 // Synchronize the contents of the cache with memory. | |
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102 #define HAL_UCACHE_SYNC() \ |
| 2 | 103 { \ |
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104 register volatile cyg_uint8 *cache_SRAM = \ |
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105 (volatile cyg_uint8*) CYG_DEVICE_CACHE_MEM; \ |
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106 register int i; \ |
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107 register cyg_uint8 old_ccr; \ |
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108 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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109 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_F); \ |
| 2 | 110 for (i = 0; i < HAL_DCACHE_SETS; i++) { \ |
| 111 *cache_SRAM = 0; \ | |
| 112 cache_SRAM += HAL_DCACHE_LINE_SIZE; \ | |
| 113 } \ | |
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114 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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115 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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116 } |
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117 |
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118 // Query the state of the cache |
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119 #define HAL_UCACHE_IS_ENABLED(_state_) \ |
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120 { \ |
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121 cyg_uint8 __ccr; \ |
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122 HAL_READ_UINT8(CYG_DEVICE_CCR, __ccr); \ |
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123 (_state_) = (CCR_E == __ccr) ? 1 : 0; \ |
| 2 | 124 } |
| 125 | |
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126 // Purge contents of cache |
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127 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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128 |
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129 // Set the cache refill burst size |
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130 //#define HAL_UCACHE_BURST_SIZE(_size_) |
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131 |
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132 // Set the cache write mode |
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133 //#define HAL_UCACHE_WRITE_MODE( _mode_ ) |
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134 |
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135 //#define HAL_UCACHE_WRITETHRU_MODE 0 |
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136 //#define HAL_UCACHE_WRITEBACK_MODE 1 |
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137 |
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138 // Load the contents of the given address range into the cache |
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139 // and then lock the cache so that it stays there. |
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140 //#define HAL_UCACHE_LOCK(_base_, _size_) |
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141 |
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142 // Undo a previous lock operation |
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143 //#define HAL_UCACHE_UNLOCK(_base_, _size_) |
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144 |
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145 // Unlock entire cache |
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146 //#define HAL_UCACHE_UNLOCK_ALL() |
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147 |
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148 //----------------------------------------------------------------------------- |
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149 // Cache line control |
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150 |
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151 // Allocate cache lines for the given address range without reading its |
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152 // contents from memory. |
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153 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) |
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154 |
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155 // Write dirty cache lines to memory and invalidate the cache entries |
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156 // for the given address range. |
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157 //#define HAL_UCACHE_FLUSH( _base_ , _size_ ) |
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158 |
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159 // Invalidate cache lines in the given range without writing to memory. |
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160 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) |
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161 |
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162 // Write dirty cache lines to memory for the given address range. |
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163 //#define HAL_UCACHE_STORE( _base_ , _size_ ) |
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164 |
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165 // Preread the given range into the cache with the intention of reading |
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166 // from it later. |
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167 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) |
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168 |
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169 // Preread the given range into the cache with the intention of writing |
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170 // to it later. |
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171 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) |
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172 |
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173 // Allocate and zero the cache lines associated with the given range. |
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174 //#define HAL_UCACHE_ZERO( _base_ , _size_ ) |
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175 |
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176 //----------------------------------------------------------------------------- |
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177 |
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178 //----------------------------------------------------------------------------- |
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179 // Data and instruction cache macros map onto the both-cache macros |
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180 |
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181 //----------------------------------------------------------------------------- |
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182 // Global control of data cache |
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183 |
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184 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE |
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185 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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186 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS |
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187 #define HAL_DCACHE_SETS HAL_UCACHE_SETS |
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188 |
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189 // Enable the data cache |
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190 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() |
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191 |
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192 // Disable the data cache |
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193 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() |
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194 |
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195 // Invalidate the entire cache |
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196 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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197 |
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198 // Synchronize the contents of the cache with memory. |
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199 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() |
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200 |
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201 // Query the state of the data cache |
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202 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 203 |
| 204 // Set the data cache refill burst size | |
| 205 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 206 | |
| 207 // Set the data cache write mode | |
| 208 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 209 | |
| 210 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 211 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 212 | |
| 213 // Load the contents of the given address range into the data cache | |
| 214 // and then lock the cache so that it stays there. | |
| 215 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 216 | |
| 217 // Undo a previous lock operation | |
| 218 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 219 | |
| 220 // Unlock entire cache | |
| 221 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 222 | |
| 223 //----------------------------------------------------------------------------- | |
| 224 // Data cache line control | |
| 225 | |
| 226 // Allocate cache lines for the given address range without reading its | |
| 227 // contents from memory. | |
| 228 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 229 | |
| 230 // Write dirty cache lines to memory and invalidate the cache entries | |
| 231 // for the given address range. | |
| 232 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 233 | |
| 234 // Invalidate cache lines in the given range without writing to memory. | |
| 235 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 236 | |
| 237 // Write dirty cache lines to memory for the given address range. | |
| 238 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 239 | |
| 240 // Preread the given range into the cache with the intention of reading | |
| 241 // from it later. | |
| 242 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 243 | |
| 244 // Preread the given range into the cache with the intention of writing | |
| 245 // to it later. | |
| 246 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 247 | |
| 248 // Allocate and zero the cache lines associated with the given range. | |
| 249 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 250 | |
| 251 //----------------------------------------------------------------------------- | |
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252 // Global control of Instruction cache |
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253 |
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254 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE |
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255 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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256 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS |
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257 #define HAL_ICACHE_SETS HAL_UCACHE_SETS |
| 2 | 258 |
| 259 // Enable the instruction cache | |
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260 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() |
| 2 | 261 |
| 262 // Disable the instruction cache | |
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263 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() |
| 2 | 264 |
| 265 // Invalidate the entire cache | |
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266 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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267 |
| 2 | 268 |
| 269 // Synchronize the contents of the cache with memory. | |
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270 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() |
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271 |
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272 // Query the state of the instruction cache |
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273 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 274 |
| 275 // Set the instruction cache refill burst size | |
| 276 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 277 | |
| 278 // Load the contents of the given address range into the instruction cache | |
| 279 // and then lock the cache so that it stays there. | |
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280 |
| 2 | 281 //#define HAL_ICACHE_LOCK(_base_, _size_) |
| 282 | |
| 283 // Undo a previous lock operation | |
| 284 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 285 | |
| 286 // Unlock entire cache | |
| 287 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 288 | |
| 289 //----------------------------------------------------------------------------- | |
| 290 // Instruction cache line control | |
| 291 | |
| 292 // Invalidate cache lines in the given range without writing to memory. | |
| 293 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 294 | |
| 295 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 296 // End of hal_cache.h |
