flash_v2: packages/hal/mips/arch/current/include/hal

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 6:d376b777e2ce ecos-sw-1999-05-14

Merge from eCos master repository on 1999-05-14-19:27:43-BST

author	jlarmour
date	Fri, 14 May 1999 12:20:00 +0000
parents	443894e2e912
children	d3fbcdfa1b2f

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	11 //####COPYRIGHTBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	12 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	13 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	14 // The contents of this file are subject to the Cygnus eCos Public License
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	15 // Version 1.0 (the "License"); you may not use this file except in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	16 // compliance with the License. You may obtain a copy of the License at
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	17 // http://sourceware.cygnus.com/ecos
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	18 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	19 // Software distributed under the License is distributed on an "AS IS"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	21 // License for the specific language governing rights and limitations under
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	22 // the License.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	23 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	24 // The Original Code is eCos - Embedded Cygnus Operating System, released
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	25 // September 30, 1998.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	26 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	27 // The Initial Developer of the Original Code is Cygnus. Portions created
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	29 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	30 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	31 //####COPYRIGHTEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	32 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	33 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	34 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	35 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	36 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	37 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	38 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	40 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	41 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	42 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	43 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	44 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	45 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	46 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	47 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	48 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	49
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	50 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	52
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	53 #include <cyg/hal/var_cache.h>
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	54
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	55 //=============================================================================
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	56 // Default Implementation. This uses the standard MIPS CP0 registers and
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	57 // cache instructions. Note that not all variants will have all of the
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	58 // functionality defined here.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	60 //-----------------------------------------------------------------------------
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	61 // Cache dimensions.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	62 // These really should be defined in var_cache.h. If they are not, then provide
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	63 // a set of numbers that are typical of many variants.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	64
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	65 #ifndef HAL_DCACHE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	66
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	67 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	68 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	69 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	70 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	71
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	72 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	73 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	74 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	76
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	77 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	78 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	80 #endif
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	81
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	82 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	83 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85 // Enable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	86 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	87 #ifndef HAL_DCACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88 #define HAL_DCACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	89 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	91 // Disable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	92 #ifndef HAL_DCACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 #define HAL_DCACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	94 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	97 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	98 // is not quite what we want, but there is no index-invalidate operation
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	99 // available.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	100 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	101 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	102 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	103
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	104 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	105 // This uses the index-writeback-invalidate operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	106 #ifndef HAL_DCACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	107 #define HAL_DCACHE_SYNC() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	108 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	109 register CYG_ADDRESS _baddr_ = 0x80000000; \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	110 register CYG_ADDRESS _addr_ = 0x80000000; \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	111 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	112 HAL_DCACHE_DISABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	113 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	114 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	115 asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	116 } \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	117 HAL_DCACHE_ENABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	118 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	119 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	120
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	121 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	122 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	123
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	124 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	125 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	126
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	127 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	128 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	129
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	130 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	131 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	132 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	133 #ifndef HAL_DCACHE_LOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	134 #define HAL_DCACHE_LOCK(_base_, _asize_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	135 CYG_MACRO_START \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	136 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	137 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	138 register CYG_WORD _size_ = (_asize_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	139 HAL_DCACHE_DISABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	140 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	141 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	142 asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	143 } \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	144 HAL_DCACHE_ENABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	145 CYG_MACRO_END
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	146 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	147
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	148 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	149 // Do this by flushing the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	150 #ifndef HAL_DCACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	151 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	152 HAL_DCACHE_FLUSH( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	153 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	154
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	155 // Unlock entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	156 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	157 #define HAL_DCACHE_UNLOCK_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	158 HAL_DCACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	159 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	160
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	161 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	163
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	164 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	165 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	166 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	167
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	168 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	169 // for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	170 // This uses the hit-writeback-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	171 #ifndef HAL_DCACHE_FLUSH_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	172 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	173 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	174 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	175 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	176 register CYG_WORD _size_ = (_asize_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	177 HAL_DCACHE_DISABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	178 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	179 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	180 asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	181 } \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	182 HAL_DCACHE_ENABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	183 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	184 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	185
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	186 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	187 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	188 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	189 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	190 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	191 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	192 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	193 register CYG_WORD _size_ = (_asize_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	194 HAL_DCACHE_DISABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	195 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	196 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	197 asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	198 } \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	199 HAL_DCACHE_ENABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	200 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	201 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	202
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	203 // Write dirty cache lines to memory for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	204 // This uses the hit-writeback cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	205 #ifndef HAL_DCACHE_STORE_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	206 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	207 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	208 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	209 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	210 register CYG_WORD _size_ = (_asize_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	211 HAL_DCACHE_DISABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	212 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	213 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	214 asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	215 } \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	216 HAL_DCACHE_ENABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	217 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	218 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	222 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	224 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	225 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	227
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	228 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	229 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	230
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	231 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	232 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	233
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	234 // Enable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	235 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	236 #ifndef HAL_ICACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	237 #define HAL_ICACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	238 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	239
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	240 // Disable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	241 #ifndef HAL_ICACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	242 #define HAL_ICACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	243 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	244
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	245 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	246 // This uses the index-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	247 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	248 #define HAL_ICACHE_INVALIDATE_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	249 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	250 register CYG_ADDRESS _baddr_ = 0x80000000; \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	251 register CYG_ADDRESS _addr_ = 0x80000000; \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	252 HAL_ICACHE_DISABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	253 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	254 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	255 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	256 } \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	257 HAL_ICACHE_ENABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	258 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	259 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	260
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	261 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	262 // Simply force the cache to reload.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	263 #ifndef HAL_ICACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	264 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	265 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	266
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	269
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	270 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	271 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	272 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	273 #ifndef HAL_ICACHE_LOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	274 #define HAL_ICACHE_LOCK(_base_, _asize_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	275 CYG_MACRO_START \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	276 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	277 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	278 register CYG_WORD _size_ = (_asize_); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	279 HAL_DCACHE_DISABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	280 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	281 { \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	282 asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	283 } \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	284 HAL_DCACHE_ENABLE(); \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	285 CYG_MACRO_END
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	286 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	287
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	288 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	289 // Do this by invalidating the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	290 #ifndef HAL_ICACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	291 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	292 HAL_ICACHE_INVALIDATE( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	293 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	294
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	295 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	296 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	297
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	298 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	299 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	301 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	302 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	303 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	304 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	305 { \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	306 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	307 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	308 register CYG_WORD _size_ = (_asize_); \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	309 HAL_DCACHE_DISABLE(); \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	310 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	311 { \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	312 asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	313 } \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	314 HAL_DCACHE_ENABLE(); \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	315 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	316 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	317
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	318 //-----------------------------------------------------------------------------
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	319 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	320
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	321 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	322
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	323 #error Unsupported MIPS configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	324
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	325 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	326
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	327 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	328 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	329 // End of hal_cache.h

Mercurial > flash_v2

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 6:d376b777e2ce ecos-sw-1999-05-14