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changeset 419:047f0d36832a

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Add cache control for writethru/copyback modes
author gthomas
date Wed, 13 Nov 2002 21:05:25 +0000
parents 5441298dacbc
children d35f86833a7c
files packages/hal/powerpc/arch/current/ChangeLog packages/hal/powerpc/arch/current/src/hal_misc.c packages/hal/powerpc/mpc8xx/current/ChangeLog packages/hal/powerpc/mpc8xx/current/include/var_cache.h
diffstat 4 files changed, 40 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/powerpc/arch/current/ChangeLog
+++ b/packages/hal/powerpc/arch/current/ChangeLog
@@ -1,3 +1,8 @@
+2002-11-13  Gary Thomas  <gthomas@ecoscentric.com>
+
+	* src/hal_misc.c (hal_enable_caches): Support new CDL options for
+	how [mode] to enable DATA cache.
+
 2002-08-05  Gary Thomas  <gary@chez-thomas.org>
 2002-08-05  Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>	
 
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c
+++ b/packages/hal/powerpc/arch/current/src/hal_misc.c
@@ -304,11 +304,24 @@ hal_enable_caches(void)
 #endif
 
 #ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+#ifdef HAL_ICACHE_UNLOCK_ALL
+    HAL_ICACHE_UNLOCK_ALL();
+#endif
     HAL_ICACHE_ENABLE();
 #endif
 
 #ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+#ifdef HAL_DCACHE_UNLOCK_ALL
+    HAL_DCACHE_UNLOCK_ALL();
+#endif
     HAL_DCACHE_ENABLE();
+#ifdef HAL_DCACHE_WRITE_MODE
+#ifdef CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK
+    HAL_DCACHE_WRITE_MODE(HAL_DCACHE_WRITEBACK_MODE);
+#else
+    HAL_DCACHE_WRITE_MODE(HAL_DCACHE_WRITETHRU_MODE);
+#endif
+#endif
 #endif
 }
 
--- a/packages/hal/powerpc/mpc8xx/current/ChangeLog
+++ b/packages/hal/powerpc/mpc8xx/current/ChangeLog
@@ -1,3 +1,8 @@
+2002-11-13  Gary Thomas  <gthomas@ecoscentric.com>
+
+	* include/var_cache.h (HAL_DCACHE_WRITE_MODE): Define for support
+	of various modes (copyback/writethru)
+
 2002-06-27  Gary Thomas  <gary@chez-thomas.org>
 
 	* include/var_regs.h: Allow platform to override certain assumptions,
--- a/packages/hal/powerpc/mpc8xx/current/include/var_cache.h
+++ b/packages/hal/powerpc/mpc8xx/current/include/var_cache.h
@@ -148,10 +148,24 @@
 //#define HAL_DCACHE_BURST_SIZE(_size_)
 
 // Set the data cache write mode
-//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+#define HAL_DCACHE_WRITE_MODE( _mode_ )                 \
+    CYG_MACRO_START                                     \
+    if (_mode_ == HAL_DCACHE_WRITETHRU_MODE) {          \
+        asm volatile ("sync;"                           \
+                  "mtspr %0, %1;"                       \
+                  : : "I" (CYGARC_REG_DC_CST),          \
+                      "r" (CYGARC_REG_DC_CMD_SW));      \
+    }                                                   \
+    if (_mode_ == HAL_DCACHE_WRITEBACK_MODE) {          \
+        asm volatile ("sync;"                           \
+                  "mtspr %0, %1;"                       \
+                  : : "I" (CYGARC_REG_DC_CST),          \
+                      "r" (CYGARC_REG_DC_CMD_CW));      \
+    }                                                   \
+    CYG_MACRO_END
 
-//#define HAL_DCACHE_WRITETHRU_MODE       0
-//#define HAL_DCACHE_WRITEBACK_MODE       1
+#define HAL_DCACHE_WRITETHRU_MODE       0
+#define HAL_DCACHE_WRITEBACK_MODE       1
 
 
 // Load the contents of the given address range into the data cache