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changeset 1057:296fd6e05b39

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XScale verde tweaks
author msalter
date Sat, 21 Jun 2003 18:55:12 +0000
parents 72c6adb4efe1
children 4de388a3615b
files packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h packages/hal/arm/xscale/verde/current/ChangeLog packages/hal/arm/xscale/verde/current/include/hal_verde.h packages/hal/arm/xscale/verde/current/src/verde_pci.c
diffstat 4 files changed, 61 insertions(+), 47 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h
+++ b/packages/hal/arm/xscale/iq80321/current/include/hal_platform_setup.h
@@ -11,7 +11,7 @@
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -225,10 +225,8 @@ icache_boundary:
 	//
 
 	// Pointers to I2C Registers
-	ldr	r11, =I2C_ICR0		// address of the I2C Control Register in r11.
-	ldr	r12, =I2C_ISR0		// address of the I2C Status Register in r12.
-	ldr	r13, =I2C_IDBR0		// address of the I2C Data Buffer Register in r13.
-
+	ldr	r11, =I2C_BASE0		// base address of the I2C unit
+        
 	//  Write 0 to avoid interfering with I2C bus.
 	//  (See GPIO section in 80321 manual)
 	ldr	r2, =GPIO_GPOD
@@ -237,20 +235,19 @@ icache_boundary:
 
 	// Reset I2C Unit
 	mov	r1, #ICR_RESET
-	str	r1, [r11]
+	str	r1, [r11, #I2C_ICR0]
 	ldr	r1, =0x7ff
-	str	r1, [r12]
+	str	r1, [r11, #I2C_ISR0]
 	mov	r1, #0
-	str	r1, [r11]
+	str	r1, [r11, #I2C_ICR0]
 
 	//  Setup I2C Slave Address Register
-	ldr	r2, =I2C_ISAR0		// Load address of the I2C Slave Address Register in r2.
 	mov	r1, #I2C_DEVID		// Load slave address r1.
-	str	r1, [r2]		// Save the value 0x02 (I2C_DEVID) in the register.
+	str	r1, [r11, #I2C_ISAR0]	// Save the value 0x02 (I2C_DEVID) in the register.
 
 	//  Enable I2C Interface Unit - status will be polled
 	ldr	r1, =ICR_GCALL | ICR_ENB | ICR_SCLENB
-	str	r1, [r11]
+	str	r1, [r11, #I2C_ICR0]
 
 	//
 	//  *** Now read the SPD Data ***
@@ -266,8 +263,8 @@ icache_boundary:
 	mov	r10, #0		// Bank size
 	mov	r14, #0         // ECC flag
 
-	ldr	r0, [r12]		// Load I2C Status Reg into R0
-	str	r0, [r12]		// Clear status
+	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
+	str	r0, [r11, #I2C_ISR0]	// Clear status
 
 	/*  FREE REGISTERS ARE R0 - R3 */
 
@@ -276,13 +273,13 @@ icache_boundary:
 	// Set SDRAM module address and write mode
 	mov	r1, #SDRAM_DEVID	// Load slave address for SDRAM module. 0xA2 (Presence Detect Data)
 	bic	r1, r1, #IDBR_MODE	// Clear read bit (bit #0)
-	str	r1, [r13]		// Store to data register
+	str	r1, [r11, #I2C_IDBR0]	// Store to data register
 
 	// Initiate dummy write to set EEPROM pointer to 0
-	ldr	r1, [r11]		// read the current Control Register value
+	ldr	r1, [r11, #I2C_ICR0]	// read the current Control Register value
 	bic	r1, r1,	#ICR_STOP	// No stop bit
 	orr	r1, r1,	#ICR_START | ICR_TRANSFER
-	str	r1, [r11]		// Store to control register
+	str	r1, [r11, #I2C_ICR0]	// Store to control register
 
 	// ====================================================================
 	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_0
@@ -292,10 +289,10 @@ icache_boundary:
 	mov	r1, #I2C_TIMOUT		// Initialize I2C timeout counter
     0:	subs	r1, r1, #1		// Increment I2C timeout counter (r1 = r1 + 1)
 	beq	i2c_error		// Kick out of SDRAM initialization if timeout occurs
-	ldr	r0, [r12]		// Load I2C Status Reg into R0
+	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
 	ands	r3, r0, #ISR_EMPTY	// Bit #6 is checked, IDBR Transmit Empty
 	beq	0b			// If bit = 0 then branch to 0 and check again
-	str	r0, [r12]		// Write back status to clear
+	str	r0, [r11, #I2C_ISR0]	// Write back status to clear
 
 	// ====================================================================
 	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_1
@@ -303,13 +300,13 @@ icache_boundary:
 		
 	// Write pointer register on EEPROM to 0x00000000
 	mov	r1, #0			// Load base address of SDRAM module EEPROM
-	str	r1, [r13]	        // Store to data register
+	str	r1, [r11, #I2C_IDBR0]   // Store to data register
 
 	//  Send address to EEPROM
-	ldr	r1, [r11]		// read the current Control Register value
+	ldr	r1, [r11, #I2C_ICR0]	// read the current Control Register value
 	bic	r1, r1,	#ICR_START | ICR_STOP
 	orr	r1, r1, #ICR_TRANSFER	// Set transfer bit - bit is self_clearing
-	str	r1, [r11]		// Store to control register
+	str	r1, [r11, #I2C_ICR0]	// Store to control register
 
 	// ====================================================================
 	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_2
@@ -319,10 +316,10 @@ icache_boundary:
 	mov	r1, #I2C_TIMOUT		// Initialize I2C timeout counter
     0:	subs	r1, r1, #1		// Increment I2C timeout counter (r1 = r1 + 1)
 	beq	i2c_error		// Kick out of SDRAM initialization if timeout occurs
-	ldr	r0, [r12]		// Load I2C Status Reg into R0 -  ld	(r12), r10
+	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
 	ands	r3, r0, #ISR_EMPTY	// Bit #6 is checked, IDBR Transmit Empty
 	beq	0b			// If bit = 0 then branch to 0 and check again
-	str	r0, [r12]		// Write back status to clear
+	str	r0, [r11, #I2C_ISR0]	// Write back status to clear
 1:
 	// ====================================================================
 	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_3
@@ -335,22 +332,22 @@ 1:
 	//  Set SDRAM module address and read mode
 	mov	r0, #SDRAM_DEVID	// Load slave address for SDRAM module (0xA2)
 	orr	r1, r0, #IDBR_MODE	// Set read bit (bit #0)
-	str	r1, [r13]		// Store to data register
+	str	r1, [r11, #I2C_IDBR0]	// Store to data register
 
 	//  Send next read request
-	ldr	r1, [r11]		// read the current Control Register value
+	ldr	r1, [r11, #I2C_ICR0]	// read the current Control Register value
 	bic	r1, r1,	#ICR_STOP	// No stop bit
 	orr	r1, r1,	#ICR_START | ICR_TRANSFER
-	str	r1, [r11]		// Store to control register
+	str	r1, [r11, #I2C_ICR0]	// Store to control register
 
 	// Wait for transmit empty status
 	mov	r1, #I2C_TIMOUT		// Initialize I2C timeout counter
     0:	subs	r1, r1, #1		// Increment I2C timeout counter (r1 = r1 + 1)
 	beq	i2c_error		// Kick out of SDRAM initialization if timeout occurs
-	ldr	r0, [r12]		// Load I2C Status Reg into R0 -  ld	(r12), r10
+	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
 	ands	r3, r0, #ISR_EMPTY	// Bit #6 is checked, IDBR Transmit Empty
 	beq	0b			// If bit = 0 then branch to 0 and check again
-	str	r0, [r12]		// Write back status to clear
+	str	r0, [r11, #I2C_ISR0]	// Write back status to clear
 
 	// ====================================================================
 	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_4
@@ -359,7 +356,7 @@ 1:
   spd_loop:
 	// read the next Byte of Serial Presence Detect data
 
-	ldr	r1, [r11]		// read the current Control Register value
+	ldr	r1, [r11, #I2C_ICR0]	// read the current Control Register value
 	bic	r1, r1,	#ICR_START	// No start bit (already started)
 	orr	r1, r1, #ICR_TRANSFER	// Set transfer bit - bit is self_clearing
 
@@ -367,18 +364,18 @@ 1:
 	add     r2, r6, #1
 	cmp	r2, r7			// r7 = 64 (decimal) so if r6 = 64, this is the last byte to be read
 	orreq	r1, r1, #ICR_ACK | ICR_STOP
-	str	r1, [r11]		// Store to control register
+	str	r1, [r11, #I2C_ICR0]	// Store to control register
 
 	// Wait for read full status
 	mov	r1, #I2C_TIMOUT		// Initialize I2C timeout counter
     0:	subs	r1, r1, #1		// decrement timeout
 	beq	i2c_error		// Kick out of SDRAM initialization if timeout occurs
-	ldr	r0, [r12]		// Load I2C Status Reg into R0
+	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
 	ands	r3, r0, #ISR_FULL	// Bit #7 is checked
 	beq	0b			// If bit = 0 then branch to 0 and check again
-	str	r0, [r12]		// Write back status to clear
+	str	r0, [r11, #I2C_ISR0]	// Write back status to clear
 
-	ldr	r1, [r13] 		// Read the byte
+	ldr	r1, [r11, #I2C_IDBR0]	// Read the byte
 
 	// check for checksum byte
 	subs	r2, r6, #SPD_CHECKSUM
@@ -545,9 +542,9 @@ 1:
 	b i2c_error
     i2c_disable:
 	//  Disable I2C Interface Unit
-	ldr	r1, [r11] 
+	ldr	r1, [r11, #I2C_ICR0] 
 	bic	r1, r1, #ICR_ENB | ICR_SCLENB	// Disable I2C unit
-	str	r1, [r11]
+	str	r1, [r11, #I2C_ICR0]
 	
 	// At this point, r4 = SDRAM size in bytes, r8 = Bank count, r10 = bank size in MB
 
@@ -773,6 +770,8 @@ 1:
 	mov	r0, #0xc
         ldr     r1, =ATU_IABAR1
 	str     r0, [r1]
+0        ldr     r1, =ATU_IABAR2
+        str     r0, [r1]
 	mov	r0, #0
         ldr     r1, =ATU_IAUBAR1
 	str     r0, [r1]
--- a/packages/hal/arm/xscale/verde/current/ChangeLog
+++ b/packages/hal/arm/xscale/verde/current/ChangeLog
@@ -1,3 +1,9 @@
+2003-06-21  Mark Salter  <msalter@redhat.com>
+
+	* src/verde_pci.c (pci_config_setup): Add dev field to PCI-X Type 0
+	config cycles. 
+	* include/hal_verde.h: Define I2C registers as base+offset.
+
 2003-01-24  Mark Salter  <msalter@redhat.com>
 
 	* include/hal_verde.h: Add some arbitatration unit defines.
--- a/packages/hal/arm/xscale/verde/current/include/hal_verde.h
+++ b/packages/hal/arm/xscale/verde/current/include/hal_verde.h
@@ -300,16 +300,25 @@
 
 // --------------------------------------------------------------------------
 // I2C (Chapter 9)
-#define I2C_ICR0	REG32(0,0xfffff680)
-#define I2C_ICR1	REG32(0,0xfffff6A0)
-#define I2C_ISR0	REG32(0,0xfffff684)
-#define I2C_ISR1	REG32(0,0xfffff6A4)
-#define I2C_ISAR0	REG32(0,0xfffff688)
-#define I2C_ISAR1	REG32(0,0xfffff6A8)
-#define I2C_IDBR0	REG32(0,0xfffff68c)
-#define I2C_IDBR1	REG32(0,0xfffff6Ac)
-#define I2C_IBMR0	REG32(0,0xfffff694)
-#define I2C_IBMR1	REG32(0,0xfffff6b4)
+#define I2C_BASE0       0xfffff680
+#define I2C_BASE1       0xfffff6A0
+
+#define I2C_ICR	        0x00
+#define I2C_ISR	        0x04
+#define I2C_ISAR	0x08
+#define I2C_IDBR	0x0c
+#define I2C_IBMR	0x14
+
+#define I2C_ICR0	REG32(I2C_BASE0,I2C_ICR)
+#define I2C_ICR1	REG32(I2C_BASE1,I2C_ICR)
+#define I2C_ISR0	REG32(I2C_BASE0,I2C_ISR)
+#define I2C_ISR1	REG32(I2C_BASE1,I2C_ISR)
+#define I2C_ISAR0	REG32(I2C_BASE0,I2C_ISAR)
+#define I2C_ISAR1	REG32(I2C_BASE1,I2C_ISAR)
+#define I2C_IDBR0	REG32(I2C_BASE0,I2C_IDBR)
+#define I2C_IDBR1	REG32(I2C_BASE1,I2C_IDBR)
+#define I2C_IBMR0	REG32(I2C_BASE0,I2C_IBMR)
+#define I2C_IBMR1	REG32(I2C_BASE1,I2C_IBMR)
 
 // Control Register bits
 #define	ICR_START	0x0001  /* 1:send a Start condition to the I2C when in master mode */
--- a/packages/hal/arm/xscale/verde/current/src/verde_pci.c
+++ b/packages/hal/arm/xscale/verde/current/src/verde_pci.c
@@ -8,7 +8,7 @@
 //####ECOSGPLCOPYRIGHTBEGIN####
 // -------------------------------------------
 // This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
 //
 // eCos is free software; you can redistribute it and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -103,7 +103,7 @@ pci_config_setup(cyg_uint32 bus, cyg_uin
 #endif
 
     if (bus == localbus)
-	*ATU_OCCAR = ( (1 << (dev + 16)) | (fn << 8) | offset | 0 );
+        *ATU_OCCAR = ( (1 << (dev + 16)) | (dev << 11) | (fn << 8) | offset | 0 );
     else
         *ATU_OCCAR = ( (bus << 16) | (dev << 11) | (fn << 8) | offset | 1 );