Mercurial > flash_v2
changeset 211:6eb55882e01c
Merge from eCos master repository on 2002-05-29-16:32:18-BST
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--- a/packages/NEWS +++ b/packages/NEWS @@ -47,6 +47,8 @@ boards that have old-style GDB stubs without VV support. * Added ELF and wider decompression support to RedBoot. * Added support for SuperH SH2 CPUs +* Added port for Motorola MCF5272c3 ColdFire evaulation board from + Wade Jensen <Wade_Jensen@inter-tel.com>. * Added ports to Wuerz Elektronik and Axiom Manufacturing MPC555 based eval boards. Contributed by Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be> from Katholieke Universiteit Leuven. Includes FLASH, serial and wallclock
--- a/packages/compat/uitron/current/ChangeLog +++ b/packages/compat/uitron/current/ChangeLog @@ -1,3 +1,7 @@ +2002-05-27 Jesper Skov <jskov@redhat.com> + + * cdl/uitron.cdl: Don't build C tests when C++ options selected. + 2002-05-22 Nick Garnett <nickg@redhat.com> * doc/uitron.sgml: Fixed dangling xref.
--- a/packages/compat/uitron/current/cdl/uitron.cdl +++ b/packages/compat/uitron/current/cdl/uitron.cdl @@ -425,7 +425,11 @@ cdl_package CYGPKG_UITRON { display "uITRON tests" flavor data no_define - calculated { "tests/test1 tests/test2 tests/test3 tests/test4 tests/test5 tests/test6 tests/test7 tests/test8 tests/test9 tests/testcxx tests/testcx2 tests/testcx3 tests/testcx4 tests/testcx5 tests/testcx6 tests/testcx7 tests/testcx8 tests/testcx9 tests/testintr" } + calculated { + "tests/testcxx tests/testcx2 tests/testcx3 tests/testcx4 tests/testcx5 tests/testcx6 tests/testcx7 tests/testcx8 tests/testcx9" + . ((!CYGIMP_UITRON_INLINE_FUNCS && !CYGIMP_UITRON_CPP_OUTLINE_FUNCS) ? + " tests/test1 tests/test2 tests/test3 tests/test4 tests/test5 tests/test6 tests/test7 tests/test8 tests/test9 tests/testintr" : "") + } description " This option specifies the set of tests for the uITRON compatibility layer." }
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/mcf52xx/mcf5272/current/cdl/mcf5272_eth_driver.cdl @@ -0,0 +1,89 @@ +# ==================================================================== +# +# mfc_eth_drivers.cdl +# +# Ethernet drivers - platform dependent support for MCF5272 +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_NET_MCF5272_ETH_DRIVERS { + display "MCF5272 ethernet driver" + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + implements CYGHWR_NET_DRIVERS + include_dir cyg/devs/eth + description "MCF5272 Ethernet driver" + compile -library=libextras.a if_mcf5272.c nbuf.c + + cdl_component CYGPKG_NET_MCF5272_ETH_DRIVERS_OPTIONS { + display "MCF5272 ethernet driver build options" + flavor none + no_define + + cdl_option CYGPKG_NET_MCF5272_ETH_DRIVERS_RX_NUM_BDS { + display "The number of receive buffer descriptors" + flavor data + legal_values 2 to 2048 + default_value 256 + description " + This option specifies the number of buffer descriptors that + the driver should allocated for the receive side." + } + + cdl_option CYGPKG_NET_MCF5272_ETH_DRIVERS_TX_NUM_BDS { + display "The number of transmit buffer descriptors" + flavor data + legal_values 2 to 2048 + default_value 128 + description " + This option specifies the number of buffer descriptors that + the driver should allocated for the transmit side." + } + + + cdl_option CYGPKG_NET_MCF5272_ETH_DRIVERS_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-D_KERNEL -D__ECOS" } + description " + This option modifies the set of compiler flags for + building the MCF5272 ethernet driver package. These flags are used in addition + to the set of global flags." + } + } +}
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/mcf52xx/mcf5272/current/include/if_mcf5272.h @@ -0,0 +1,330 @@ +#ifndef _IF_MCF5272_FEC +#define _IF_MCF5272_FEC +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/hal/drv_api.h> +#include <cyg/io/eth/eth_drv_stats.h> +#include <cyg/devs/eth/nbuf.h> + + /* Ethernet controller inetrrupt priority level. */ +#define MCF5272_INT_LEVEL 4 + +/* Bit level definitions and macros */ +#define MCF5272_FEC_ECR_RESET (0x00000001) +#define MCF5272_FEC_ECR_ETHER_EN (0x00000002) +#define MCF5272_FEC_EIR_GRA (0x10000000) + +#define MCF5272_FEC_EIR_HBE (0x80000000) +#define MCF5272_FEC_EIR_BR (0x40000000) +#define MCF5272_FEC_EIR_BT (0x20000000) +#define MCF5272_FEC_EIR_GRA (0x10000000) +#define MCF5272_FEC_EIR_TXF (0x08000000) +#define MCF5272_FEC_EIR_TXB (0x04000000) +#define MCF5272_FEC_EIR_RXF (0x02000000) +#define MCF5272_FEC_EIR_RXB (0x01000000) +#define MCF5272_FEC_EIR_MII (0x00800000) +#define MCF5272_FEC_EIR_EBERR (0x00400000) +#define MCF5272_FEC_EIR_UMINT (1<<21) + +#define MCF5272_FEC_IMR_HBEEN (0x80000000) +#define MCF5272_FEC_IMR_BREN (0x40000000) +#define MCF5272_FEC_IMR_BTEN (0x20000000) +#define MCF5272_FEC_IMR_GRAEN (0x10000000) +#define MCF5272_FEC_IMR_TXFEN (0x08000000) +#define MCF5272_FEC_IMR_TXBEN (0x04000000) +#define MCF5272_FEC_IMR_RXFEN (0x02000000) +#define MCF5272_FEC_IMR_RXBEN (0x01000000) +#define MCF5272_FEC_IMR_MIIEN (0x00800000) +#define MCF5272_FEC_IMR_EBERREN (0x00400000) +#define MCF5272_FEC_RCR_PROM (0x00000008) +#define MCF5272_FEC_RCR_MII_MODE (0x00000004) +#define MCF5272_FEC_RCR_DRT (0x00000002) +#define MCF5272_FEC_RCR_LOOP (0x00000001) +#define MCF5272_FEC_TCR_GTS (0x00000001) +#define MCF5272_FEC_TCR_HBC (0x00000002) +#define MCF5272_FEC_TCR_FDEN (0x00000004) +#define MCF5272_FEC_RDAR_DESTACT (0x01000000) +#define MCF5272_FEC_MFLR_BRDCAST (0x80000000) +#define MCF5272_FEC_MFLR_MLTCAST (0x40000000) +#define MCF5272_FEC_XWMRK_64 (0x00000000) +#define MCF5272_FEC_XWMRK_128 (0x00000002) +#define MCF5272_FEC_XWMRK_192 (0x00000003) + +/* Define the PHY addresss. This address specifies which 32 attached */ +/* PHY devices. */ + +//#define MCF5272_PHY_ADD (0) +#define MCF5272_PHY_ADD (0 << 23) + + +/* Start of frame delimter for valid MII management frame. */ + +#define MCF5272_FEC_MII_ST (0x40000000) + +/* Operation code. This field bust be programmed to generate a valid */ +/* MII management frame. */ + +#define MCF5272_FEC_MII_OP_READ (0x20000000) +#define MCF5272_FEC_MII_OP_WRITE (0x10000000) + +/* Register address. Specifies one of the 32 attached PHY devices. */ + +#define MCF5272_FEC_MII_RA_POS (18) +#define MCF5272_FEC_MII_RA_MASK (0x1F) + +/* Turn around. Must be programmed to 10 to generate a valid MII */ +/* management frame. */ + +#define MCF5272_FEC_MII_TA (0x00020000) + + +/* The management frame data maske. Field for data to be written to */ +/* or read from PHY register. */ + +#define MCF5272_FEC_MII_DATA_MASK (0x0000FFFF) + + +/* This define the MII unchanged MII frame management bits. */ + +#define MCF5272_FEC_MII_FIX_HDR (0 | \ + MCF5272_FEC_MII_ST | \ + MCF5272_PHY_ADD | \ + MCF5272_FEC_MII_TA) + + +/* The PHY address mask. */ + +#define MCF5272_FEC_MII_PA (0x1F << 23) + +/* Define the interrupt mask. */ + +#define MCF5272_FEC_INTERRUPT_MASK (MCF5272_FEC_IMR_TXFEN | \ + MCF5272_FEC_IMR_RXFEN ) + + +/************************************************** + * FEC diagnostic counters + **************************************************/ +typedef struct MCF5272_FEC_DIAG +{ + + /* We put all the receive statistics first. */ + + unsigned long rx_pk_cnt; /* The total number of */ + /* received packets */ + + unsigned long rx_pk_cnt_sec; + + unsigned long rx_bytes_cnt; /* The total number of */ + /* received bytes */ + + unsigned long rx_bytes_cnt_sec; + + unsigned long rx_err_cnt; /* The total number of bad */ + /* packets received */ + + unsigned long rx_long_frm_err_cnt; /* The total number of long */ + /* frame errors. */ + + unsigned long rx_short_frm_err_cnt; /* The total number of short */ + /* frame errors. */ + + unsigned long rx_crc_err_cnt; /* The total number of CRC */ + /* errors. */ + + unsigned long rx_overrun_err_cnt; /* The total number of */ + /* overrun errors. */ + + unsigned long rx_trunc_error_cnt; /* The total numbers of */ + /* receieve truncated packet */ + /* errors. */ + + /* We put all the transmit statistics next. start_of_transmit */ + /* doesn't take any space but only separates the receive statistics */ + /* from the transmit statistics. */ + + char start_of_transmit[0]; + + unsigned long tx_pk_cnt; /* The total number of */ + /* transmitted packet */ + + unsigned long tx_pk_cnt_sec; + + unsigned long tx_bytes_cnt; /* The total number of */ + /* transmitted bytes */ + + unsigned long tx_bytes_cnt_sec; + + unsigned long tx_err_cnt; /* The total number of failed */ + /* packet transmission */ + + unsigned long tx_def_cnt; /* The total number of tansmit */ + /* defers. */ + + unsigned long tx_hb_err_cnt; /* The total number of heart */ + /* beat errors. */ + + unsigned long tx_late_col_cnt; /* The total number of late */ + /* collisions. */ + + unsigned long tx_exes_retry_cnt; /* Excessive rettry count. */ + + unsigned long tx_retry_cnt; /* The total number of transmit */ + /* retries. */ + + unsigned long tx_underrun_cnt; /* The total number of transmit */ + /* underruns. */ + + unsigned long tx_carrrier_loss_cnt; /* The total number of */ + /* trasnmit carrier losses. */ + + unsigned long tx_free_bd_cnt; /* The total number of freed */ + /* buffer descriptor. */ + + unsigned long tx_free_min_bd_cnt; /* The minimum number of free */ + /* buffer descriptor count. */ + + unsigned long tx_full_cnt; /* The number of times when */ + /* there is no transmit buffer. */ + + unsigned long tx_not_complete_cnt; /* The number of times the */ + /* device driver discovered */ + /* that the BD is still in use */ + /* by the FEC. */ + + unsigned long internal_bus_error_cnt; /* FEC bus error count. A */ + /* bus error occurred when */ + /* the FEC was accessing an */ + /* internal bus. */ + +}MCF5272_FEC_DIAG __attribute__ ((aligned, packed)); + +/* Ethernet driver status. */ +enum eth_drv_status_t +{ + ETH_DEV_UNKNOWN = 1, + ETH_DEV_DOWN = 2, + ETH_DEV_UP = 3 +}; + +/* Ethernet duplex mode. */ +enum eth_drv_mode_t +{ + ETH_MODE_UNKNOWN = 1, + ETH_MODE_SIMPLEX = 2, + ETH_MODE_DUPLEX = 3 +}; + + +/* Ethernet speed values. */ +enum eth_speed_t +{ + ETH_SPEED_10MB = 10*1000*1000, + ETH_SPEED_100MB = 100*1000*1000 +}; + +/* Ethernet driver statistics information structure. */ + +struct mcf5272_ether_drv_stats +{ + struct ifreq ifreq; // tell ioctl() which interface. + + char description[ DESC_LEN ]; // Textual description of hardware + unsigned char snmp_chipset[ SNMP_CHIPSET_LEN ]; + // SNMP ID of chipset + enum eth_drv_mode_t duplex; // 1 = UNKNOWN, 2 = SIMPLEX, 3 = DUPLEX + enum eth_drv_status_t operational; // 1 = UNKNOWN, 2 = DOWN, 3 = UP + // These are general status information: + unsigned int speed; // 10,000,000 or 100,000,000 + // to infinity and beyond? + + MCF5272_FEC_DIAG stats; + +}__attribute__ ((aligned, packed)); + +#ifndef FIELD_OFFSET +#define FIELD_OFFSET(type,field) (cyg_uint32)(&(((type*)0)->field) +#endif /* FIELD_OFFSET */ + +/* The value of 1 second in nanosecond. */ +#define SEC_IN_NS 1000000000 + +/* 48-bit Ethernet Addresses */ +typedef u8_t ETH_ADDR[6]; + +/* 16-bit Ethernet Frame Type, ie. Protocol */ +typedef u16_t ETH_FTYPE; + +/* Maximum and Minimum Ethernet Frame Size (Data Field) */ +#define ETH_DATA_MAX_SIZE (1500) +#define ETH_DATA_MIN_SIZE (46) + +/* Maximum and Minimum Ethernet Frame Size (Entire frame) */ +#define ETH_MAX_SIZE (ETH_DATA_MAX_SIZE+14) +#define ETH_MIN_SIZE (ETH_DATA_MIN_SIZE+14) + +/* Common Ethernet Frame definition */ +typedef struct +{ + ETH_ADDR dest; + ETH_ADDR src; + ETH_FTYPE type; + u8_t data[ETH_DATA_MAX_SIZE]; + u32_t fcs; +} eth_frame_hdr __attribute__ ((aligned, packed)); + +/* 802.1Q Ethernet Frame definition */ +typedef struct +{ + ETH_ADDR dest; + ETH_ADDR src; + u32_t header_802_1q; + ETH_FTYPE type; + u8_t data[ETH_DATA_MAX_SIZE]; + u32_t fcs; +} eth_802_1Q_frame_hdr __attribute__ ((aligned, packed)); + +/* Definition of macros that access the FEC registers */ +#define put_reg(_addr_,_value_) \ + *((volatile u32_t*)&(_addr_)) = (cyg_uint32)(_value_) + +#define get_reg(_addr_) \ + *(((volatile u32_t*)&(_addr_))) + + +#endif /* _IF_MCF5272_FEC */ + +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/mcf52xx/mcf5272/current/include/if_mcf5272_private_data.h @@ -0,0 +1,96 @@ +#ifndef _IF_MCF5272_PRIVATE_DATA_H_ +#define _IF_MCF5272_PRIVATE_DATA_H_ +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/hal/drv_api.h> +#include <cyg/io/eth/netdev.h> +#include <cyg/io/eth/eth_drv.h> +#include <cyg/devs/eth/if_mcf5272.h> +#include <cyg/devs/eth/nbuf.h> + +/* Device driver private data. */ + +struct MCF5272_fec_priv_data_t +{ + + buf_info_t nbuffer; + + /* Diagnositc supplement variables. */ + + struct + { + unsigned int old_tx_pk_cnt; + unsigned int old_rx_pk_cnt; + unsigned int old_tx_bytes_cnt; + unsigned int old_rx_bytes_cnt; + }diag_info_sup; + + /* 1 second alarm variables */ + + cyg_handle_t alarm_h; + cyg_alarm alarm; + cyg_handle_t counter_h; + + /* Diagnostic counters */ + + MCF5272_FEC_DIAG diag_counters; + + /* This flag is set if the device is operational */ + + enum eth_drv_status_t operational; + + /* Unknown, Half Duplex or Full duplex. */ + + enum eth_drv_mode_t duplex; + + /* Ethernet bandwidth. */ + + u32_t speed; + + /* Temporary packet buffer. */ + + eth_frame_hdr pkt_buf; + +}; +typedef struct MCF5272_fec_priv_data_t MCF5272_fec_priv_data_t; + +#define PMCF5272_FEC_DATA(_SC_) \ + ((MCF5272_fec_priv_data_t*)(((struct eth_drv_sc*)(_SC_))->driver_private)) +#define PBUF_INFO(_SC_) \ + (&(((MCF5272_fec_priv_data_t*)((_SC_)->driver_private))->nbuffer)) + +#endif /* _IF_MCF5272_PRIVATE_DATA_H_ */ +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/mcf52xx/mcf5272/current/include/nbuf.h @@ -0,0 +1,648 @@ +#ifndef _NBUF_H +#define _NBUF_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +/* + * File: nbuf.h + * Purpose: Definitions for Network Buffer Allocation. + * + * Notes: These routines implement a static buffer scheme. + * The buffer descriptors are as specified by the + * MPC860T/MCF5272 FEC. + * + * Modifications: + * + */ + +#include <cyg/hal/drv_api.h> +#include <pkgconf/net_mcf5272_eth_drivers.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/io/eth/eth_drv.h> + + + +/********************************************************************/ + + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + + +#define Rx 1 +#define Tx 0 + +/* + * Buffer sizes in bytes -- The following values were chosen based + * on TFTP maximum packet sizes. These sizes may need to be + * increased to implement other protocols. + */ +#define RX_BUFFER_SIZE (576) /* must be divisible by 16 */ +/* #define TX_BUFFER_SIZE 576 */ + + +/* The this label is not defined, we define it and default it to 256. */ +#ifndef CYGPKG_NET_MCF5272_ETH_DRIVERS_RX_NUM_BDS +#define CYGPKG_NET_MCF5272_ETH_DRIVERS_RX_NUM_BDS 256 +#endif + +/* The this label is not defined, we define it and default it to 256. */ +#ifndef CYGPKG_NET_MCF5272_ETH_DRIVERS_TX_NUM_BDS +#define CYGPKG_NET_MCF5272_ETH_DRIVERS_TX_NUM_BDS 256 +#endif + + +/* Number of Receive and Transmit Buffers and Buffer Descriptors */ +#define NUM_RXBDS (CYGPKG_NET_MCF5272_ETH_DRIVERS_RX_NUM_BDS) +#define NUM_TXBDS (CYGPKG_NET_MCF5272_ETH_DRIVERS_TX_NUM_BDS) + + + +/* + * Buffer Descriptor Format -- must be aligned on 4-byte boundary + * but a 16-byte boundary is recommended. However, we cannot pack + * them on 16-byte boundaries as this will add 8-bytes of padding + * between structures and the FEC of the MPC860T/MCF5272 will choke. + */ +typedef struct NBUF +{ + uint16 status; /* control and status */ + uint16 length; /* transfer length */ + uint8 *data; /* buffer address */ +} __attribute__ ((packed, aligned))NBUF; + + +/* Defines the tx key type. */ +typedef enum tx_key_type_t +{ + TX_KEY_ECOS, /* eCos key */ + TX_KEY_USER /* user key */ +}tx_key_type_t; + +typedef struct tx_keys_t +{ + unsigned long tx_key; /* The transmit key that eCos gives us. */ + uint_t tx_buf_index; /* Index to the TxNBUF where the last Buffer Descriptor of the frame. */ + int num_dbufs; /* The number transmit buffer allocated for the frame. */ + uint_t start_index; /* Index of the bd */ + int_t pk_len; + tx_key_type_t key_type; /* The type of the key. */ + +}tx_keys_t; + +typedef struct buf_info_t +{ + + /* Buffer descriptor indexes */ + + uint_t iTxbd; + uint_t iRxbd; + + /* Queue for the transmit keys */ + + #define TX_KEY_QUEUE_SIZE (NUM_TXBDS+1) + tx_keys_t tx_keys_queue[TX_KEY_QUEUE_SIZE]; + + /* Rear and front pointer for the keys queue. */ + + uint_t tq_rear; + uint_t tq_front; + + /* Number transmit descriptor buffers busy. */ + + volatile int num_busy_bd; + + /* The maximum number of buffer decriptor used. */ + + volatile int max_num_busy_bd; + + /* Buffer Descriptors */ + NBUF ntxbuf[NUM_TXBDS+2]; + NBUF nrxbuf[NUM_RXBDS+2]; + + NBUF* RxNBUF; + NBUF* TxNBUF; + + /* Buffers */ + //TXB TxBuffer[NUM_TXBDS]; + u8_t RxBuffer[(NUM_RXBDS+2)*RX_BUFFER_SIZE]; + + +}buf_info_t; + + +/********************************************************************/ + +/* + * Bit level Buffer Descriptor definitions + */ + +#define TX_BD_R 0x8000 +#define TX_BD_TO1 0x4000 +#define TX_BD_INUSE TX_BD_TO1 +#define TX_BD_W 0x2000 +#define TX_BD_TO2 0x1000 +#define TX_BD_L 0x0800 +#define TX_BD_TC 0x0400 +#define TX_BD_DEF 0x0200 +#define TX_BD_HB 0x0100 +#define TX_BD_LC 0x0080 +#define TX_BD_RL 0x0040 +#define TX_BD_UN 0x0002 +#define TX_BD_CSL 0x0001 + +#define RX_BD_E 0x8000 +#define RX_BD_R01 0x4000 +#define RX_BD_W 0x2000 +#define RX_BD_R02 0x1000 +#define RX_BD_L 0x0800 +#define RX_BD_M 0x0100 +#define RX_BD_BC 0x0080 +#define RX_BD_MC 0x0040 +#define RX_BD_LG 0x0020 +#define RX_BD_NO 0x0010 +#define RX_BD_SH 0x0008 +#define RX_BD_CR 0x0004 +#define RX_BD_OV 0x0002 +#define RX_BD_TR 0x0001 + +/*******************************************************************/ + +/* + * Functions to manipulate the network buffers. + */ + +void nbuf_init (buf_info_t* pBuf); + + +/********************************************************************/ +inline static +uint32 +nbuf_get_start(buf_info_t* pBuf, uint8 direction) +{ + /* + * Return the address of the first buffer descriptor in the ring. + * This routine is needed by the FEC of the MPC860T and MCF5272 + * in order to write the Rx/Tx descriptor ring start registers + */ + switch (direction){ + case Rx: + return (uint32)pBuf->RxNBUF; + default: + case Tx: + return (uint32)pBuf->TxNBUF; + } +} + + + + + + +/****************************************************************************** + nbuf_rx_get_next() - Retrieve the next receive buffer descriptor. + + INPUT: + pBuf - Pointer to the buffer info. + +RETURN: + Returns the pointer to the next receive buffer descriptor. +*/ + +inline static +NBUF * +nbuf_rx_get_next(buf_info_t* pBuf) +{ + NBUF* pBd = &pBuf->RxNBUF[pBuf->iRxbd]; + + /* Check to see if the ring of BDs is full */ + if (pBd->status & RX_BD_E) + { + return NULL; + } + + /* increment the circular index */ + pBuf->iRxbd = (pBuf->iRxbd + 1) % NUM_RXBDS; + + return pBd; +} + + +/* Return the pointer to the buffer descriptor based on the index */ +inline static +NBUF* +nbuf_rx_get(buf_info_t* pBuf, uint_t index) +{ + return(&pBuf->RxNBUF[index]); +} + +/******************************************************************** + Release the buffer descrip so that it can be use + to receive the enxt packet. + + INPUT: + pNbuf - pointer to the buffer descriptor. +*/ + +inline static +void +nbuf_rx_release (NBUF* pNbuf) +{ + + /* Mark the buffer as empty and not in use */ + pNbuf->status |= RX_BD_E; + +} + + +/* Return the current rx buffer descriptor index */ +inline static uint_t +nbuf_rx_get_index(buf_info_t* pBuf) +{ + return pBuf->iRxbd; +} + +/**************************************************************** + This function checks the EMPTY bit of the next Rx buffer to be + allocated. If the EMPTY bit is cleared, then the next buffer in + the ring has been filled by the FEC and has not already been + allocated and passed up the stack. In this case, the next buffer + in the ring is ready to be allocated. Otherwise, the buffer is + either empty or not empty but still in use by a higher level + protocol. The FEC receive routine uses this function to determine + if multiple buffers where filled by the FEC during a single + interrupt event. + ****************************************************************/ +inline static +uint_t +nbuf_rx_next_ready(buf_info_t* pBuf) +{ + + return ( !(pBuf->RxNBUF[pBuf->iRxbd].status & RX_BD_E)); +} + + + + +/****************************************************************************** + nbuf_rx_release_pkt() - Release the buffer descriptors of the next packet. + + INPUT: + pointer to the buffer info. +*/ +inline static +void nbuf_rx_release_pkt(buf_info_t* pBuf) +{ + + NBUF* pNbuf; + + /* Indicates whether the last buffer descriptor is encountered. */ + cyg_bool_t last = false; + + do + { + /* Get the buffer descriptor. */ + pNbuf = nbuf_rx_get_next(pBuf); + + /* Stop when there is a packet truncated bit is set or it is the */ + /* last buffer descriptor of the packet. */ + + if ((!(pNbuf->status & RX_BD_E) && pNbuf->status & RX_BD_TR) || + pNbuf->status & RX_BD_L) + { + last = true; + } + + /* Release the buffer descriptor. */ + nbuf_rx_release(pNbuf); + + }while(last == false); + +} + + + +/****************************************************************************** + nbuf_rx_release_good_pkt() - Release the buffer descriptors for + good received packets. + Note call this function + only when there is valid received + buffer descriptors. + + INPUT: + pBuf - pointer to the buffer info. +*/ +inline static +void nbuf_rx_release_good_pkt(buf_info_t* pBuf) +{ + + u16_t status; + + do + { + + /* Read the status bits. If the RX_BD_L is set we terminate the */ + /* loop. */ + + status = pBuf->RxNBUF[pBuf->iRxbd].status; + + /* Release the buffer descriptor so that it could reused. */ + + nbuf_rx_release(&pBuf->RxNBUF[pBuf->iRxbd]); + + /* Advance the index to the next buffer descriptor. */ + + pBuf->iRxbd = (pBuf->iRxbd + 1) % NUM_RXBDS; + + + }while(!(status & RX_BD_L)); + +} + + +/****************************************************************************** + nbuf_tx_release() - Set the buffer descriptor ready for use to transmit + the next packet. + + INPUT: + pNbuf - Pointer to the transmit buffer descriptor. +*/ +inline static +void +nbuf_tx_release (NBUF* pNbuf) +{ + + /* Clear the TX_BD_INUSE to indicate that we have read the */ + /* transmitted buffer. */ + + pNbuf->status &= ~(TX_BD_INUSE | TX_BD_R | TX_BD_L | TX_BD_TC); + +} + +/* Return a nozero value if the buffer is full. Otherwise, it returns a + zero value. +*/ +inline static +int_t nbuf_tx_full(buf_info_t* pBuf) +{ + return (pBuf->TxNBUF[pBuf->iTxbd].status & TX_BD_R); +} + + +/* Return the pointer to the transmit buffer descriptor. */ +inline static +NBUF* +nbuf_tx_get(buf_info_t* pBuf, int_t index) +{ + return(&pBuf->TxNBUF[index]); +} + +/****************************************************************************** + nbuf_peek_tx_key() - Peek whether there is any + pending packets that are still in transmisison. + + INPUT: + pBuf - Pointer to the buffer structure. + + OUTPUT: + index - The index to the oldest pending packet in the queue. + + RETURN: + Returns the index to the oldest pending packet in the queue. Otherwise, + it returns -1. + +*/ +inline static +int_t nbuf_peek_tx_key(buf_info_t* pBuf) +{ + if (pBuf->tq_rear == pBuf->tq_front) + { + return -1; /* No pending transmit buffers. */ + } + return pBuf->tx_keys_queue[pBuf->tq_front].tx_buf_index; +} + +/****************************************************************************** + nbuf_peek_bd_ahead() - Returns the pointer of the to the last buffer + descriptor of the 2nd. pending transmit frame. + + INPUT: + pBuf - Pointer to the buffer structure. + + + RETURN: + Returns the pointer of the to the last buffer + descriptor of the 2nd. pending transmit frame. If there is not 2nd. + pending frame, it returns NULL. + + +*/ +inline static +NBUF* nbuf_peek_bd_ahead(buf_info_t* pBuf) +{ + uint_t ahead_front = (pBuf->tq_front + 1) % TX_KEY_QUEUE_SIZE; + + if (pBuf->tq_rear == pBuf->tq_front || + ahead_front == pBuf->tq_rear) + { + return NULL; /* No pending transmit buffers. */ + } + + return &pBuf->TxNBUF[pBuf->tx_keys_queue[ahead_front].tx_buf_index]; +} + + + +/****************************************************************************** + nbuf_enq_tx_key() - Enqueue and deuque transmit key queue. + Enqueue the transmit key. The buf_index is the index to the transmit buffer deiscriptor + table of the last buffer descriptor for the frame and the transmit packet + type. +*/ +inline static +void nbuf_enq_tx_key(buf_info_t* pBuf, + uint_t buf_index, + unsigned long txkey, + uint_t start_index, + int num_bd, + int_t total_len, + tx_key_type_t key_type) +{ + tx_keys_t* p_keys = &pBuf->tx_keys_queue[pBuf->tq_rear]; + /* Assign the transmit packet information to the transmit key queue. */ + + /* NOTE: We don't check for the full condition because the transmit */ + /* key queue size is as big as the number of buffer descriptors. */ + + p_keys->tx_key = txkey; + p_keys->tx_buf_index = buf_index; + p_keys->num_dbufs = num_bd; + p_keys->pk_len = total_len; + p_keys->start_index = start_index; + p_keys->key_type = key_type; + + /* Advance the transmit queue pointer to the next entry. */ + + pBuf->tq_rear = (pBuf->tq_rear + 1) % TX_KEY_QUEUE_SIZE; + + } + + +/****************************************************************************** + nbuf_deq_tx_key() - Dequeue the transmit packet from the transmit key queue. + Assume that the queue is not empty. + + + INPUT: + pBuf - Pointer to the buffer structure. + + OUTPUT: + key - The key the transmit information. +*/ +inline static +void nbuf_deq_tx_key(buf_info_t* pBuf, tx_keys_t* key) +{ + + CYG_ASSERT(pBuf->tq_rear != pBuf->tq_front, "nbuf_deq_tx_key: empty"); + *key = pBuf->tx_keys_queue[pBuf->tq_front]; + pBuf->tq_front = (pBuf->tq_front + 1) % TX_KEY_QUEUE_SIZE; + +} + +/******************************************************************************* + nbuf_tx_dump() - Dump the transmit buffer information. + + INPUT: + pBuf - pointer to the buffer info. +*/ +inline static +void nbuf_tx_dump(buf_info_t* pBuf) +{ + + tx_keys_t key; + + diag_printf("Current index to ring buffer: %d\n", pBuf->iTxbd); + diag_printf("Address to the BD: %08X\n", + &pBuf->TxNBUF[pBuf->iTxbd]); + + diag_printf("BD status: %04X\n", pBuf->TxNBUF[pBuf->iTxbd].status); + diag_printf("TX Queue rear index: %d\n", pBuf->tq_rear); + diag_printf("TX Queue front index: %d\n", pBuf->tq_front); + diag_printf("Number of busy BDs: %d\n", pBuf->num_busy_bd); + + diag_printf("Dump Transmit Queue\n"); + diag_printf("===================\n"); + + while(nbuf_peek_tx_key(pBuf) != -1) + { + nbuf_deq_tx_key(pBuf, &key); + diag_printf("Number of BDs: %d\n", key.num_dbufs); + diag_printf("Frame length: %d\n", key.pk_len); + diag_printf("Begin index to ring bufer: %d\n", key.start_index); + diag_printf("BD address: %08X\n", &pBuf->TxNBUF[key.tx_buf_index]); + diag_printf("status: %04X\n", pBuf->TxNBUF[key.tx_buf_index].status); + + diag_printf("End index to ring buffer: %d\n", key.tx_buf_index); + diag_printf("Key Info: %08X\n", key.tx_key); + diag_printf("Key type: %d\n", key.key_type); + diag_printf("\n"); + + } + diag_printf("===================\n"); + + +} + + +/******************************************************************** + nbuf_tx_allocate() - Alocate transmit buffer descriptor. + + INPUT: + pBuf - pointer to the buffer info. + + OUTPUT: + index - index to the buffer descriptor ring buffer that it returns. This + value is invalid if this funtion returns a NULL. + + RETURN: + Returns the pointer to the buffer descriptor. If the ring buffer + descriptor is full, it returns NULL. + + */ +inline static +NBUF * +nbuf_tx_allocate (buf_info_t* pBuf) +{ + NBUF* pBd = &pBuf->TxNBUF[pBuf->iTxbd]; + + /* If the ring buffer is full, then return a NULL. */ + + if (pBd->status & TX_BD_INUSE) + { + nbuf_tx_dump(pBuf); + return NULL; + } + + /* Make sure that the buffer descriptor is still not in use by the */ + /* FEC . */ + + CYG_ASSERT(!(pBd->status & TX_BD_R), + "Buffer descriptor allocated still in use"); + + /* Set the buffer to be in used so that we can check the status */ + /* before we resuse it to send another packet. */ + + pBd->status |= TX_BD_INUSE; + + + /* increment the circular index */ + pBuf->iTxbd = ((pBuf->iTxbd + 1) % NUM_TXBDS); + + return pBd; +} + + + + +/*****************************************************************************/ + +#endif /* _NBUF_H */
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/mcf52xx/mcf5272/current/src/if_mcf5272.c @@ -0,0 +1,1883 @@ +//========================================================================== +// +// dev/if_MCF5272_fec.c +// +// Ethernet device driver for MCF5272's Fast Ethernet Controller (FEC) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + + +// Ethernet device driver for Fast Ethernet MCF5272_fec +#include <cyg/hal/drv_api.h> +#include <cyg/io/eth/netdev.h> +#include <cyg/io/eth/eth_drv.h> +#include <cyg/devs/eth/nbuf.h> +#include <cyg/devs/eth/if_mcf5272.h> +#include <cyg/devs/eth/if_mcf5272_private_data.h> + +#include <cyg/infra/cyg_ass.h> +#include <sys/param.h> +#include <net/if.h> + + +/* Function to retrieve the Ethernet address of the device from the device's + database. We declare it weak so that other routines can overide it. + */ + +externC const void* +db_get_eth_address(void) __attribute__ ((weak)); + + +/***************************************************************************** + + The following functions provide an interface directly to the +ethernet driver for applications that wish to circumvent the IP stack. + + Applications that wish to take advantage of this should override +these routine with their own. Leaving these routines as default routes +all data through the IP stack. + +*****************************************************************************/ +externC int_t +eth_rx_pkt_filter(u8_t* pkt, uint_t pkt_len) __attribute__ ((weak)); +externC void +eth_tx_check(struct eth_drv_sg * sg_list, unsigned int sg_len) + __attribute__ ((weak)); +externC void +eth_send_done(unsigned long tag) __attribute__ ((weak)); +externC int_t +eth_send(struct eth_drv_sg * sg_list, unsigned int sg_len, int total_len, + unsigned long tag); + +static MCF5272_fec_priv_data_t MCF5272_fec_priv_data; + +/* Interrupt strcture and handles. */ +static cyg_interrupt MCF5272_fec_rx_interrupt; +static cyg_interrupt MCF5272_fec_tx_interrupt; + +static cyg_handle_t MCF5272_fec_rx_interrupt_handle; +static cyg_handle_t MCF5272_fec_tx_interrupt_handle; + + +// Interrupt handler +static void MCF5272_fec_int(struct eth_drv_sc *sc); +static int MCF5272_fec_int_vector(struct eth_drv_sc *sc); + +// This DSR handles the ethernet [logical] processing +static void MCF5272_fec_deliver(struct eth_drv_sc * sc); +static void MCF5272_fec_stop(struct eth_drv_sc *sc); + +static void +MCF5272_fec_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, + int total_len, unsigned long key); + +static void +MCF5272_fec_common_send(struct eth_drv_sc *sc, + struct eth_drv_sg *sg_list, int sg_len, + int total_len, + unsigned long key, + tx_key_type_t key_type); + +static int +MCF5272_fec_isr(cyg_vector_t vector, cyg_addrword_t data, + HAL_SavedRegisters *regs); + + +// One-second call back alarm +static void one_second_alarm_func(cyg_handle_t alarm, cyg_addrword_t data); + +// Retrieve statistics +static void MCF5272_get_stats(struct eth_drv_sc *sc, MCF5272_FEC_DIAG* stats); + + +ETH_DRV_SC(MCF5272_fec_sc, + &MCF5272_fec_priv_data, // Driver specific data + "eth0", // Name for this interface + MCF5272_fec_start, + MCF5272_fec_stop, + MCF5272_fec_control, + MCF5272_fec_can_send, + MCF5272_fec_send, + MCF5272_fec_recv, + MCF5272_fec_deliver, + MCF5272_fec_int, + MCF5272_fec_int_vector); + +/* Device name */ +static const char ether_device_name[] = "MCF5272-eth"; + +NETDEVTAB_ENTRY(MCF5272_fec_netdev, + ether_device_name, + MCF5272_fec_init, + &MCF5272_fec_sc); + + +/******************************************************************************* + db_get_eth_address() - Returns the default Ethernet address. +*/ +const void* db_get_eth_address(void) +{ + + /* Just use an obviously invalid address until someone overrides this */ + /* routine to provide their own address. */ + + static const unsigned char enaddr[] = + { + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 + }; + return (const void*)enaddr; +} +/******************************************************************************* + MCF5272_fec_init() - Routine that initializes the FEC. + + INPUT: + tab - Pointer to the network device table. + + */ +static bool MCF5272_fec_init(struct cyg_netdevtab_entry *tab) +{ + struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; + const u8_t *enaddr; + + /* Indicate that the ethernet driver is down. */ + + PMCF5272_FEC_DATA(sc)->operational = ETH_DEV_DOWN; + + /* Initialize the entire driver private area to zero. */ + + memset((char*)sc->driver_private, sizeof(MCF5272_fec_priv_data_t), 0); + + /* Initialize the buffers structure. This strucre contains transmit */ + /* and receive buffer descriptor managment information. */ + + nbuf_init(PBUF_INFO(sc)); + + /* Start a alarm that will trigger every second. This alarm will */ + /* periodically update the recevie and transmit statistics. */ + + cyg_clock_to_counter(cyg_real_time_clock(), + &(((MCF5272_fec_priv_data_t*)sc->driver_private)->counter_h)); + cyg_alarm_create(((MCF5272_fec_priv_data_t*)sc->driver_private)->counter_h, + one_second_alarm_func, + (cyg_addrword_t)(MCF5272_fec_priv_data_t*)sc->driver_private, + &(((MCF5272_fec_priv_data_t*)sc->driver_private)->alarm_h), + &(((MCF5272_fec_priv_data_t*)sc->driver_private)->alarm)); + cyg_alarm_initialize(((MCF5272_fec_priv_data_t*)sc->driver_private)->alarm_h, + cyg_current_time()+ + (1*SEC_IN_NS)/CYGNUM_KERNEL_COUNTERS_RTC_PERIOD, + (1*SEC_IN_NS)/CYGNUM_KERNEL_COUNTERS_RTC_PERIOD); + + /* Initialize environment, setup receive, transmit and non-critical */ + /* interrupt handlers. */ + + cyg_drv_interrupt_create(CYGNUM_HAL_VECTOR_ERX, + MCF5272_INT_LEVEL, // Priority + (cyg_addrword_t)sc, // Data item passed to interrupt handler + (cyg_ISR_t *)MCF5272_fec_isr, + (cyg_DSR_t *)eth_drv_dsr, + &MCF5272_fec_rx_interrupt_handle, + &MCF5272_fec_rx_interrupt); + cyg_drv_interrupt_create(CYGNUM_HAL_VECTOR_ETX, + MCF5272_INT_LEVEL, // Priority + (cyg_addrword_t)sc, // Data item passed to interrupt handler + (cyg_ISR_t *)MCF5272_fec_isr, + (cyg_DSR_t *)eth_drv_dsr, + &MCF5272_fec_tx_interrupt_handle, + &MCF5272_fec_tx_interrupt); + + /* Attach interrupt here in order to start receiving interrupt from */ + /* the FEC. */ + + cyg_drv_interrupt_attach(MCF5272_fec_rx_interrupt_handle); + cyg_drv_interrupt_attach(MCF5272_fec_tx_interrupt_handle); + + + + put_reg(MCF5272_SIM->gpio.pbcnt, 0x55550000 | + (get_reg(MCF5272_SIM->gpio.pbcnt) & 0x0000FFFF)); + + + /* Reset the FEC - equivalent to a hard reset. */ + + put_reg(MCF5272_SIM->enet.ecr, MCF5272_FEC_ECR_RESET); + + /* Wait for the reset sequence to complete. */ + + while(get_reg(MCF5272_SIM->enet.ecr) & MCF5272_FEC_ECR_RESET); + + /* Set the Ethernet control register to zero to disable the FEC. */ + + put_reg(MCF5272_SIM->enet.ecr, 0); + + /* Set the source address for the controller. */ + + /* Initialize physical address register by copying our adapter */ + /* address from the device's permanent storage. */ + + enaddr = (cyg_uint8*)db_get_eth_address(); + + put_reg(MCF5272_SIM->enet.malr,0 + | (enaddr[0] <<24) + | (enaddr[1] <<16) + | (enaddr[2] <<8) + | (enaddr[3] <<0)); + put_reg(MCF5272_SIM->enet.maur,0 + | (enaddr[4] <<24) + | (enaddr[5] <<16)); + + /* Initialize the hash table registers to ignore hash checking to */ + /* detect multicast Etherhet addresses. */ + + put_reg(MCF5272_SIM->enet.htur, 0); + put_reg(MCF5272_SIM->enet.htlr, 0); + + /* Set Receive Buffer Size. This is the size for each receive */ + /* buffer. */ + + put_reg(MCF5272_SIM->enet.emrbr, (uint16)RX_BUFFER_SIZE); + + /* Point to the start of the circular Rx buffer descriptor queue. */ + + put_reg(MCF5272_SIM->enet.erdsr, nbuf_get_start(PBUF_INFO(sc), Rx)); + + /* Point to the start of the circular Tx buffer descriptor queue. */ + + put_reg(MCF5272_SIM->enet.etdsr, nbuf_get_start(PBUF_INFO(sc), Tx)); + + /* Set the FIFO transmit highwater mark to 128 bytes. Frame */ + /* transmission begins when the number of bytes selected by this field */ + /* are written into the transmit FIFO, if an end of frame has been */ + /* written to the FIFIO, or if the FIFO is full before selected number */ + /* of bytes are written. */ + + put_reg(MCF5272_SIM->enet.tfwr, MCF5272_FEC_XWMRK_128); + + /* Clear any interrupts by setting all bits in the EIR register. */ + + put_reg(MCF5272_SIM->enet.eir, 0xFFFFFFFF); + + /* Set the tranceiver interface to MII mode. */ + + put_reg(MCF5272_SIM->enet.rcr, 0 | MCF5272_FEC_RCR_MII_MODE); + // | MCF5272_FEC_RCR_DRT); + + /* Set the mode is ETH_MODE_SIMPLEX. We are assuming the device is */ + /* half-duplex mode. */ + + PMCF5272_FEC_DATA(sc)->duplex = ETH_MODE_SIMPLEX; + + /* The default speed is 10 Mbs. */ + + PMCF5272_FEC_DATA(sc)->speed = ETH_SPEED_10MB; + + /* Write the maximum frame length and setup so we can receive */ + /* broadcast packets. */ + + put_reg(MCF5272_SIM->enet.mflr, MCF5272_FEC_MFLR_BRDCAST | + sizeof(eth_frame_hdr)); + + /* Check for heartbeat count and enable full-duplex transmit. The */ + /* hearbeat check is performed following end of transmission and the HB */ + /* bit in the status reguster is set if the collision input does not */ + /* assert within the heartbeat window. */ + + /* NOTE: We disable full duplex mode because we notice that we're */ + /* getting Receive CRC erors. */ + + + put_reg(MCF5272_SIM->enet.tcr, 0 |MCF5272_FEC_TCR_HBC); + //| MCF5272_FEC_TCR_FDEN); + + /* Set the MII frequency divider. The MII_SPEED controls the */ + /* frequency of the MII management interface clock relative to the */ + /* system clock. We set MII speed to 7 because the system clock */ + /* frequency is 66 Mhz. */ + + put_reg(MCF5272_SIM->enet.mscr, 7<<1); + + /* Initialize upper level driver. */ + + (sc->funs->eth_drv->init)(sc, (unsigned char *)enaddr); + + /* Return true to indicate that the driver initialization has */ + /* completed successfully. */ + + return true; + +} + +/* This function is called to "start up" the interface. It may be */ +/* called multiple times, even when the hardware is already running. It */ +/* will be called whenever something "hardware oriented" changes and should */ +/* leave the hardware ready to send/receive packets. */ + +static void +MCF5272_fec_start(struct eth_drv_sc *sc, cyg_uint8 *enaddr, int flags) +{ + + /* Initialize the buffers structure. This strucre contains transmit */ + /* and receive buffer descriptor managment information. We initialize */ + /* again here becuase we don't know the internal state of the buffer */ + /* descriptor pointer in the FEC if the FEC was disabled after calling */ + /* MCF5272_fec_stop. */ + + if (PMCF5272_FEC_DATA(sc)->operational != ETH_DEV_UP) + { + nbuf_init(PBUF_INFO(sc)); + } + + /* Unmask the Transmit and Receive frame interrupt to handle the */ + /* interrupts. */ + + /* Unmask the Internal Bus Errorso we can detect any internal bus */ + /* error when the FEC tries to acess the internal bus. */ + + put_reg(MCF5272_SIM->enet.eimr, + get_reg(MCF5272_SIM->enet.eimr) | MCF5272_FEC_INTERRUPT_MASK); + + /* Enable FEC. */ + + put_reg(MCF5272_SIM->enet.ecr, MCF5272_FEC_ECR_ETHER_EN); + + /* Indicate that there have been empty receive buffers produced. */ + + put_reg(MCF5272_SIM->enet.rdar, MCF5272_FEC_RDAR_DESTACT); + + + /* Set the flag to indicate that the device is up and running. */ + + PMCF5272_FEC_DATA(sc)->operational = ETH_DEV_UP; + +} + +/* A routine to halt the FEC. */ +static void +MCF5272_fec_stop(struct eth_drv_sc *sc) +{ + + /* Stop the packet transmission gracefully. */ + + /* Set the Graceful Transmit Stop bit. */ + + put_reg(MCF5272_SIM->enet.tcr, get_reg(MCF5272_SIM->enet.tcr) + | MCF5272_FEC_TCR_GTS); + + /* Wait for the current transmission to complete. */ + + while( !(get_reg(MCF5272_SIM->enet.eir) & MCF5272_FEC_EIR_GRA)); + + /* Clear the GRA event. */ + + put_reg(MCF5272_SIM->enet.eir, MCF5272_FEC_EIR_GRA); + + /* Disable all FEC interrupts by clearing the IMR register. */ + + put_reg(MCF5272_SIM->enet.eimr, 0); + + /* Clear the GTS bit so frames can be tranmitted when restarted */ + + put_reg(MCF5272_SIM->enet.tcr, get_reg(MCF5272_SIM->enet.tcr) & + ~MCF5272_FEC_TCR_GTS); + + /* Set the Ethernet control register to zero to disable the FEC. */ + + put_reg(MCF5272_SIM->enet.ecr, 0); + + /* Deliver any pending frames and acknowledge any transmitted frames. */ + + MCF5272_fec_deliver(sc); + + /* Set the flag to indicate that the device is down. */ + + PMCF5272_FEC_DATA(sc)->operational = ETH_DEV_DOWN; + +} + +/* This routine is called to perform special "control" opertions. */ + +static int +MCF5272_fec_control(struct eth_drv_sc *sc, unsigned long key, + void *data, int data_length) +{ + switch (key) + { + + case ETH_DRV_SET_MAC_ADDRESS: + + { + /* Set the hardware address of the Ethernet controller. */ + + struct ifreq* p_ifreq = data; + + /* If the length of the strcutre is not equal to the size of */ + /* ifreq, then exit with an error. */ + + if (data_length != sizeof(*p_ifreq)) + { + return 0; + } + + /* Set the lower 4-byte address. */ + + put_reg(MCF5272_SIM->enet.malr,0 + | (p_ifreq->ifr_ifru.ifru_hwaddr.sa_data[0] <<24) + | (p_ifreq->ifr_ifru.ifru_hwaddr.sa_data[1] <<16) + | (p_ifreq->ifr_ifru.ifru_hwaddr.sa_data[2] <<8) + | (p_ifreq->ifr_ifru.ifru_hwaddr.sa_data[3] <<0)); + + /* Set the upper 2-byte address. */ + + put_reg(MCF5272_SIM->enet.maur, + 0 + | (p_ifreq->ifr_ifru.ifru_hwaddr.sa_data[4] <<24) + | (p_ifreq->ifr_ifru.ifru_hwaddr.sa_data[5] <<16)); + + + /* Return 1 to indicate that programming of the new MAC */ + /* address is successful. */ + + return 1; + } + + + break; + #ifdef CYGPKG_NET + + case ETH_DRV_GET_IF_STATS: + case ETH_DRV_GET_IF_STATS_UD: + + #if 0 + { + + struct ether_drv_stats* pstats = (struct ether_drv_stats*) + data; + MCF5272_FEC_DIAG diag; + + /* Retrieve the driver defined diagnostic structure. */ + MCF5272_get_stats(sc, &diag); + + strcpy(pstats->description, ether_device_name); + pstats->duplex = ETH_MODE_UNKNWON; + pstats->operational = (unsigned char )PMCF5272_FEC_DATA(sc)->operational; + pstats->speed = 0; + + /* Translate the device specific diagnostic values to the */ + /* generic ether_drv_stats values. */ + + /* Get the receive bytes count. */ + pstats->rx_count = diag.rx_bytes_cnt; + + /* Get the number of successful packet received. */ + pstats->rx_good = diag.rx_pk_cnt; + + /* Get the receive CRC error count. */ + pstats->rx_crc_errors = diag.rx_crc_err_cnt; + + /* Get the receive overrun error count. */ + pstats->rx_overrun_errors = diag.rx_overrun_err_cnt; + + /* Get the received short frame error count. */ + pstats->rx_short_frames = diag.rx_short_frm_err_cnt; + + /* Get the received long frame error count. */ + pstats->rx_too_long_frames = diag.rx_long_frm_err_cnt; + + /* Get the number of transmitted bytes. */ + pstats->tx_count = diag.tx_bytes_cnt; + + /* Get the number of defered packets. */ + pstats->tx_deferred = diag.tx_def_cnt; + + /* The number of successfully transmitted packets. */ + pstats->tx_good = diag.tx_pk_cnt; + + /* Get the transmit late collision count. */ + pstats->tx_late_collisions = diag.tx_late_col_cnt; + + /* Get the transmit underrun count. */ + pstats->tx_underrun = diag.tx_underrun_cnt; + + /* Get the transmit late collision count. */ + pstats->tx_total_collisions = diag.tx_late_col_cnt; + return 1; + } + #else + { + + /* Copy the ethernet name device over. */ + + strcpy(((struct mcf5272_ether_drv_stats*)data)->description, + ether_device_name); + + /* Get the stats. */ + MCF5272_get_stats(sc, + &((struct mcf5272_ether_drv_stats*)data)->stats); + + /* Copy the mode over. */ + + ((struct mcf5272_ether_drv_stats*)data)->duplex = + PMCF5272_FEC_DATA(sc)->duplex; + + /* The ethernet driver is operational. */ + + ((struct mcf5272_ether_drv_stats*)data)->operational = + PMCF5272_FEC_DATA(sc)->operational; + + /* Copy the speed over. */ + + ((struct mcf5272_ether_drv_stats*)data)->speed = + PMCF5272_FEC_DATA(sc)->speed; + + return 1; + } + + #endif + break; + + #endif /* CYGPKG_NET */ + default: + return 1; + break; + } + +} + + +/* This routine is called to see if it is possible to send another */ +/* packet. It will return non-zero if a transmit is possible, zero */ +/* otherwise. */ + +static int +MCF5272_fec_can_send(struct eth_drv_sc *sc) +{ + const int buffer_window = 5; /* Specifies the minimum empty buffer descrpitors */ + + if ((NUM_TXBDS - PBUF_INFO(sc)->num_busy_bd) > buffer_window) + { + return 1; + } + else + { + PMCF5272_FEC_DATA(sc)->diag_counters.tx_full_cnt++; + return 0; + } +} + + +/* This routine is called by eCos to send a frame to the ethernet */ +/* controller. */ + +static void +MCF5272_fec_send(struct eth_drv_sc *sc, + struct eth_drv_sg *sg_list, + int sg_len, + int total_len, + unsigned long key) +{ + + /* Call eth_tx_check() routine for any packet transmitted by eCos. */ + + eth_tx_check(sg_list, sg_len); + + + /* If we do have enough buffer to send we call */ + /* MCF5272_fec_common_send routine to send the packet. Otherwise, we */ + /* throw away the packet and call eCos's tx_done rutine to notify that */ + /* the packet has been sent. */ + + if (NUM_TXBDS - PBUF_INFO(sc)->num_busy_bd > sg_len) + { + MCF5272_fec_common_send(sc, sg_list, sg_len, total_len, key, TX_KEY_ECOS); + + + } + else + { + + CYG_ASSERT(false, "ETH: Send buffer full"); + + /* Inform the upper layer of a completion of the packet. */ + + (sc->funs->eth_drv->tx_done)(sc, + key, + 0); + } + +} + +/* This routine is called to send a frame to the ethernet controller. */ +/* This is a generic send routine. */ +/* + + INPUT: + sc - Ethernet driver sc. + sg_glist - scatter gather list. + sg_len - The number of scattter gather entries in the list. + total_len - The total length of the frame. + +*/ + + +static void +MCF5272_fec_common_send(struct eth_drv_sc *sc, + struct eth_drv_sg *sg_list, + int sg_len, + int total_len, + unsigned long key, + tx_key_type_t key_type) +{ + int i = 0; + NBUF *pBD = NULL; + NBUF *first_bd; + buf_info_t* p_buf = PBUF_INFO(sc); + + + CYG_ASSERT(sg_len > 0, "ETH: sg_len cannot be zero"); + + + /* Update the number of used transmitted buffer desciptors. */ + + p_buf->num_busy_bd += sg_len; + + /* Keep track of the maximum number of busy transmit buffer */ + /* descriptors. */ + + if (p_buf->num_busy_bd > p_buf->max_num_busy_bd) + { + p_buf->max_num_busy_bd = p_buf->num_busy_bd; + } + + /* Enqueue the key, the index to first and last buffer desriptor, the */ + /* number of buffer descriptors, the packet length and the type of */ + /* packet to the transmit queue. */ + + nbuf_enq_tx_key(p_buf, (p_buf->iTxbd + sg_len - 1) % NUM_TXBDS, + key, + p_buf->iTxbd, + sg_len, + total_len, + key_type); + + /* Get the pointer to the first buffer descriptor of the packet. We */ + /* don't set the R bit for the first packet until we have allocated and */ + /* initialized all the buffer descriptors. */ + + first_bd = pBD = nbuf_tx_allocate(p_buf); + + do + { + + CYG_ASSERT(pBD != NULL, "ETH: nbuf_tx_allocate() returned NULL"); + + + /* Copy the address of the buffer and the length to the allocated */ + /* buffer descriptor. Note that buf_index indexes to the buffer */ + /* descriptor it returns. */ + + pBD->data = (uint8*)sg_list[i].buf; + pBD->length = sg_list[i].len; + + if (i == sg_len - 1) + { + + /* Set the the L, TC and R bit to indicate that the buffer */ + /* descriptor is the last buffer descriptor, the CRC is */ + /* appended by the FEC and the buffer descriptor is ready for */ + /* transmission. */ + + pBD->status |= TX_BD_L | TX_BD_TC | TX_BD_R; + + /* When we have reached the last buffer scatther list, we */ + /* break from the loop. */ + + break; + + } + else + { + + if (i) + { + + /* If the buffer descriptor is not the first buffer */ + /* descriptor, then set the R bit to notify the FEC that */ + /* the buffer descriptor is read for transmission. FEC */ + /* must reset R bit after transmitted for buffer. */ + + pBD->status |= TX_BD_R; + + } + + /* Allocate the next buffer descriptor. */ + + pBD = nbuf_tx_allocate(p_buf); + + } + + /* Advance to the next index. */ + + i++; + + }while(1); + + /* Set the R bit in the first buffer descriptor to indicate that the */ + /* buffer is ready for transmission if there are more than one buffer */ + /* descriptors. */ + + if (sg_len > 1) + first_bd->status |= TX_BD_R; + + /* Indicate that there is a transmit buffer ready. */ + + put_reg(MCF5272_SIM->enet.tdar, 1); + +} + + +/* This function is called as a result of the "eth_drv_recv()" call */ +/* above. It's job is to actually fetch data for a packet from the */ +/* hardware once memory buffers have been allocated for the packet. Note */ +/* that the buffers may come in pieces, using a scatter-gather list. This */ +/* allows for more efficient processing in the upper layers of the stack. */ + +/* Note that the total buffer allocated for the scatter-gather list */ +/* can be smaller than the packet or the buffer that in the scatter gather */ +/* list is invalid. This happens when the upper layer driver runs out of */ +/* buffers for the scatter-gather list. */ + +static void +MCF5272_fec_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) +{ + uint_t fill_count = 0, buf_count; + uint_t frame_length = 0, buf_len; + NBUF *pNbuf = NULL; + cyg_uint8* buf = NULL; + cyg_bool_t done = false; + uint_t sg_index = 0; + + /* If the scatter-gather list is zero, set buf to NULL so that this */ + /* routine would not copy the buffer to the scatter-gatther buffer. */ + + if (sg_len > 0) + { + buf = (cyg_uint8*)sg_list[0].buf; + } + + do + { + + /* Get the next buffer descriptor (bd). */ + + pNbuf = nbuf_rx_get_next(PBUF_INFO(sc)); + + CYG_ASSERT(pNbuf != NULL, "Cannot get the next bd"); + + if (pNbuf->status & TX_BD_L) + { + + /* Calculate the remaining numer of bytes in the packet that */ + /* needed to be copied out since the the length of the in the */ + /* last BD contains the total length of the packet and not the */ + /* length of the buffer. */ + + buf_len = (uint_t)pNbuf->length - frame_length; + + /* Since the last bd, set done to true in order to exit the */ + /* loop. */ + + done = true; + } + else + { + buf_len = RX_BUFFER_SIZE; + + /* Update the frame length. */ + + frame_length += RX_BUFFER_SIZE; + } + + + /* Copy the packet to the scatter gather list if there is a buffer */ + /* to copy the packet to. */ + + for (buf_count = 0; buf_count < buf_len && buf != NULL;) + { + + uint_t copy_len; + + /* Retrieve the minimum copy length. We basically copy based */ + /* on the smaller size: the buffer from the scatther list or the */ + /* from the buffer descriptor. */ + + copy_len = (((uint_t)sg_list[sg_index].len - fill_count) < + (buf_len - buf_count) ? + (uint_t)sg_list[sg_index].len - fill_count : + (buf_len - buf_count)); + + /* Copy the buffer to the upper layer driver buffer. */ + + memcpy(&buf[fill_count], + &pNbuf->data[buf_count], + copy_len); + + /* Update the counts to reflect the number of bytes copied. */ + + fill_count += copy_len; + buf_count += copy_len; + + /* If the buffer in the scatter-gather list is full, we */ + /* attempt to retrieve the next buffer in the list. */ + + if (fill_count >= sg_list[sg_index].len) + { + + /* If there is no more buffer, set the buf to NULL and */ + /* exit the loop. */ + + if (++sg_index >= sg_len) + { + buf = NULL; + break; + } + else + { + buf = (cyg_uint8*)sg_list[sg_index].buf; + fill_count = 0; + } + } + } + + + /* Release the buffer scriotor so it cab be used to receive other */ + /* packets. */ + + nbuf_rx_release(pNbuf); + + }while(done == false); + + /* Notify the FEC that there are receive buffer descriptors available */ + /* for the FEC. */ + + put_reg(MCF5272_SIM->enet.rdar, MCF5272_FEC_RDAR_DESTACT); +} + +/******************************************************************************* +MCF5252_fec_recv_handler() - Receive handler to read the received +buffer descriptors and inform the upper layer driver of the arrival +of the packet. +*/ +inline static +bool MCF5252_fec_recv_handler(struct eth_drv_sc * sc) +{ + + /* Receive interrupt has occurred informing driver that a frame has */ + /* been written to the buffer. */ + + NBUF* pNBuf; + buf_info_t* p_buf_info = PBUF_INFO(sc); + MCF5272_fec_priv_data_t* eth_data = PMCF5272_FEC_DATA(sc); + uint_t len; + + /* Pointer to the first buffer descriptor. */ + + NBUF* p_first_bd; + + /* Check to see if the buffer descrpitor is not busy. */ + + if (nbuf_rx_next_ready(p_buf_info)) + { + + /* Flag that indicates whether the buffer is wrapped. */ + + cyg_bool_t wrap = false; + + /* Get the index of the buffer desrciptor of the next frame. */ + + uint_t index = nbuf_rx_get_index(p_buf_info); + cyg_bool_t error = false; + len = 0; + + /* Get the pointer to the first buffer descriptor. */ + + p_first_bd = nbuf_rx_get(p_buf_info, index); + + do + { + pNBuf = nbuf_rx_get(p_buf_info, index); + + if (pNBuf->status & RX_BD_E) + { + + /* The buffer is empty or the FEC is stll writing to the */ + /* buffer. then exit. */ + + return false; + + } + + /* Advance the index to the next buffer descriptor in the */ + /* ring buffer. */ + + index = (index + 1) % NUM_RXBDS; + + if ((pNBuf->status & (RX_BD_L | RX_BD_W)) == RX_BD_W) + { + + /* If the buffer descriptor wraps, set the wrap flag and */ + /* initalize the index pointer to the first buffer */ + /* descriptor in the ring. */ + + wrap = true; + + } + + if (pNBuf->status & RX_BD_TR) + { + + /* Packet truncate count. */ + + eth_data->diag_counters.rx_trunc_error_cnt++; + + /* Release the bds. */ + + nbuf_rx_release_pkt(p_buf_info); + + /* Update the receive error count. */ + + eth_data->diag_counters.rx_err_cnt++; + + /* Notify the FEC that there are receive buffer */ + /* descriptors available from the FEC. */ + + put_reg(MCF5272_SIM->enet.rdar, MCF5272_FEC_RDAR_DESTACT); + + error = true; + break; + } + + if (pNBuf->status & RX_BD_L) + { + + /* Get the length of frame contain in the buffers. */ + + len = pNBuf->length; + + /* If there is an error in receiving the packet, we */ + /* proceed to update the counters. Otherwise, we just fall */ + /* through. */ + + if (pNBuf->status & (RX_BD_LG | RX_BD_SH | RX_BD_CR | + RX_BD_OV)) + { + + /* Update the diagnostic counters. */ + + if (pNBuf->status & RX_BD_LG) + { + /* Larget frame error count. */ + eth_data->diag_counters.rx_long_frm_err_cnt++; + } + + if (pNBuf->status & RX_BD_SH) + { + /* Short frame error count. */ + eth_data->diag_counters.rx_short_frm_err_cnt++; + } + + if (pNBuf->status & RX_BD_CR) + { + /* CRC error count. */ + eth_data->diag_counters.rx_crc_err_cnt++; + } + + if (pNBuf->status & RX_BD_OV) + { + /* Overrun error count. */ + eth_data->diag_counters.rx_overrun_err_cnt++; + } + + /* Release the packet. */ + + nbuf_rx_release_pkt(p_buf_info); + + /* Update the receive error count. */ + + eth_data->diag_counters.rx_err_cnt++; + + /* Notify the FEC that there are receive buffer */ + /* descriptors available for the FEC */ + + put_reg(MCF5272_SIM->enet.rdar, MCF5272_FEC_RDAR_DESTACT); + + /* Set the error flag to true to indicate that there */ + /* is an error. */ + + error = true; + + } + } + }while(!(pNBuf->status & RX_BD_L)); + + if (error == false) + { + cyg_uint8* buf_ptr = p_first_bd->data; + + /* Since there is no error, we update the good statistic */ + /* counters. */ + + /* Update the number of frames received. */ + + eth_data->diag_counters.rx_pk_cnt++; + + /* Update the number of bytes in the frame received. */ + + /* Subract 4 bytes from the length because the packet */ + /* includes the 4-byte FCS. */ + + eth_data->diag_counters.rx_bytes_cnt += (len - 4); + + + /* If the packet wraps then copy the packet to the a */ + /* temporary buffer in order to make the packet contigous */ + /* packet in memory. */ + + if (wrap) + { + + uint_t count_len = 0; + uint_t pk_len; + + /* Set p_buf the pointer to temporary packet biffer which */ + /* we will use to copy the packet. */ + + u8_t* p_buf = (u8_t*)ð_data->pkt_buf; + + /* Get the index of the buffer desrcitor of the next frame. */ + + uint_t index = nbuf_rx_get_index(p_buf_info); + + do + { + + /* Get the buffer descriptor. */ + + pNBuf = nbuf_rx_get(p_buf_info, index); + + /* Calculate the length of the data in the buffer */ + /* descriptor. If we reach the last buffer descriptor, */ + /* the the actual data size in the last buffer */ + /* descriptor is the number of bytes we have copied */ + /* less from the value of the length field of the last */ + /* buffer descriptor. */ + + if (pNBuf->status & RX_BD_L) + { + pk_len = len - count_len; + } + else + { + pk_len = RX_BUFFER_SIZE; + } + + /* Copy the content of the buffer to the temporary */ + /* packet buffer. */ + + memcpy(&p_buf[count_len], pNBuf->data, pk_len); + + + /* Keep count of the number of bytes read from the */ + /* buffer descriptor. */ + + count_len += pk_len; + + /* Advance to the to next buffer descriptor. */ + + index = (index + 1) % NUM_RXBDS; + + }while(!(pNBuf->status & RX_BD_L)); + + buf_ptr = (u8_t*)ð_data->pkt_buf; + + + } + + /* If there is a copy wrap error or the Rx packet filter */ + /* rejected the packet, pass it to the upper layer. Otherwise, */ + /* release the buffer descriptors. */ + + if (!eth_rx_pkt_filter(buf_ptr, len)) + { + + /* Inform the upper layer of a complete packet. */ + + (sc->funs->eth_drv->recv)(sc, len); + } + else + { + + /* Release the buffer descriptors. */ + + nbuf_rx_release_good_pkt(p_buf_info); + + + /* Notify the FEC that there is at least a receive buffer */ + /* descriptos available for the FEC. */ + + put_reg(MCF5272_SIM->enet.rdar, MCF5272_FEC_RDAR_DESTACT); + + } + + } + + } + else + { + + /* Indicates that there are no more receive packets. */ + + return false; + } + return true; + +} +/******************************************************************************* +MCF5272_fec_transmit_handler() - Transmit handler informs the upper +layer packet of a completion of a transmit packet. +*/ + +static +bool MCF5272_fec_transmit_handler(struct eth_drv_sc * sc) + +/* If the FEC has successfull transmitted a packet, then realease the */ +/* buffer used for the packet so that the buffer can be reused. */ + +{ + + /* Check to see which frame has completed sending so we can tell the */ + /* upper layer to free up ts buffer. */ + + buf_info_t* p_buf_info = PBUF_INFO(sc); + MCF5272_fec_priv_data_t* eth_data = PMCF5272_FEC_DATA(sc); + NBUF* pNbd = NULL; + int_t index, i; + tx_keys_t key_entry; + bool result = true; + NBUF* next_bd; + + + /* Check wether there is any pending transmit buffer descriptors that */ + /* are to deallocated. */ + + if ((index = nbuf_peek_tx_key(p_buf_info)) != -1) + { + + /* Get the pointer to the buffer descriptor so that the flags in */ + /* the status word in the buffer descriptor can be examined. */ + + NBUF* pNbuf = nbuf_tx_get(p_buf_info, index); + + CYG_ASSERT(pNbuf->status & TX_BD_L, "Index to BD is not the last BD"); + + if (pNbuf->status & TX_BD_R) + { + + + /* Increment the number of times the device driver discovers */ + /* that the buffer descriptor is still in use by the FEC and it */ + /* has been skipped. */ + + if ((next_bd = nbuf_peek_bd_ahead(p_buf_info))) + { + if (!(next_bd->status & TX_BD_R) && + pNbuf->status & TX_BD_R) + { + + eth_data->diag_counters.tx_not_complete_cnt++; + goto RELEASE_BUF; + + } + } + + /* If the buffer not ready we return immediatly. */ + + return false; + + } + +RELEASE_BUF: + + /* Dequeue the packet from the trasnmt packet queue to indicate */ + /* that the packet is not being transmitted by the FEC. */ + + nbuf_deq_tx_key(p_buf_info, &key_entry); + + /* Release the used buffers. */ + + for ( i = 0; i < key_entry.num_dbufs; i++) + + { + + /* Get the BD based on the index. */ + + pNbd = nbuf_tx_get(p_buf_info, + (key_entry.start_index + i) % NUM_TXBDS); + + /* The last buffer descriptor of the packet. */ + + if (pNbd->status & TX_BD_L) + { + + if (pNbd->status & TX_BD_RL) + { + + /* Update the number of retries. */ + + eth_data->diag_counters.tx_retry_cnt += 16; + eth_data->diag_counters.tx_err_cnt++; + eth_data->diag_counters.tx_exes_retry_cnt++; + } + else + { + + /* Check for error status. If there is an error */ + /* proceed the increment the appropriate statistic */ + /* counter. */ + + if (pNbd->status & (TX_BD_UN | + TX_BD_LC | + TX_BD_CSL | + TX_BD_HB)) + { + + if (pNbd->status & TX_BD_HB) + { + + /* Heartbeat error count. */ + + eth_data->diag_counters.tx_hb_err_cnt++; + } + + if (pNbd->status & TX_BD_UN) + { + + /* Transmit underrun error count. */ + + eth_data->diag_counters.tx_underrun_cnt++; + } + + if (pNbd->status & TX_BD_CSL) + { + + /* Transmit carrier loss count. */ + + eth_data->diag_counters.tx_carrrier_loss_cnt++; + } + + if (pNbd->status & TX_BD_LC) + { + + /* Update the late collision counter. */ + + eth_data->diag_counters.tx_late_col_cnt++; + } + + /* Update the number transmit error count. */ + + eth_data->diag_counters.tx_err_cnt++; + } + else + { + /* Update the diagnostic counters */ + + if (pNbd->status & TX_BD_DEF) + { + /* Defer indication count. */ + eth_data->diag_counters.tx_def_cnt++; + } + + /* Update the number of transmitted packets. */ + + eth_data->diag_counters.tx_pk_cnt++; + + /* Update the transmitted packet size. If the */ + /* size is less than the minimum size then take the */ + /* minimum size as the actual frame length. This */ + /* is because we take account of the pad bytes that */ + /* the FEC appends when it sends out frames that */ + /* has less than the minimum length. */ + + eth_data->diag_counters.tx_bytes_cnt += + key_entry.pk_len < ETH_MIN_SIZE ? ETH_MIN_SIZE : + key_entry.pk_len; + } + + /* Get the number of retries. */ + + eth_data->diag_counters.tx_retry_cnt += + (pNbd->status >> 2) & 0xF; + } + + } + + /* Release the buffer descriptor so that it can be reused to */ + /* transmit the next packet. */ + + nbuf_tx_release(pNbd); + + /* If the start_index is the same as the index to the last */ + /* buffer descriptor, then quit the loop. */ + + } + + /* Decrement the number of busy descriptors. */ + + p_buf_info->num_busy_bd -= key_entry.num_dbufs; + + switch(key_entry.key_type) + { + case TX_KEY_ECOS: + + /* Inform the upper layer of a completion of the packet. */ + + (sc->funs->eth_drv->tx_done)(sc, + key_entry.tx_key, + 0); + break; + case TX_KEY_USER: + + /* Inform the application of the completion of the packet. */ + + eth_send_done(key_entry.tx_key); + break; + } + + } + else + { + + /* Retrun false to indicate that the transmit buffer is empty. */ + + result = false; + } + + /* Indicate that the packet at the transmit buffer has been */ + /* successfully handled. */ + + return result; +} + + +/* This routine informs the upper layer of a completion of a sent */ +/* frame and a reception of a frame. */ + +static void +MCF5272_fec_deliver(struct eth_drv_sc * sc) +{ + u32_t event; + + + /* Clear the event register. */ + + put_reg(MCF5272_SIM->enet.eir, + (event = (get_reg(MCF5272_SIM->enet.eir) & + MCF5272_FEC_INTERRUPT_MASK))); + + while(event & MCF5272_FEC_INTERRUPT_MASK) + { + + /* This flag will specifies whether we need to service the */ + /* transmit or receive sides of the Ethernet controller. */ + + bool packet_status; + + + /* Keep count of any bus error that might occur when the FEC */ + /* attempts while the FEC accessing the internal bus. */ + + if (event & MCF5272_FEC_EIR_EBERR) + { + PMCF5272_FEC_DATA(sc)->diag_counters.internal_bus_error_cnt++; + } + + do + { + packet_status = false; + + /* Call receive the handler to receive packets. */ + + packet_status |= MCF5252_fec_recv_handler(sc); + + /* Call transit the handed to release the transmit buffers. */ + + packet_status |= MCF5272_fec_transmit_handler(sc); + + /* Loop back up until all the receive and transmit buffers */ + /* are empty. */ + + }while(packet_status); + + /* Retrieve the next interrupt event. */ + + /* Clear the event register. */ + + put_reg(MCF5272_SIM->enet.eir, + event = (get_reg(MCF5272_SIM->enet.eir) & + MCF5272_FEC_INTERRUPT_MASK)); + + } + + /* NOTE: If the a bit in the eir is set after clearing the bit in the */ + /* eir, unmasking the bit in the imr will generate an interrupt. This */ + /* assumption is true only if the interrupt line to the microprocessor */ + /* core is level sensitive. */ + + /* Allow interrupts by setting IMR register. */ + + put_reg(MCF5272_SIM->enet.eimr, get_reg(MCF5272_SIM->enet.eimr) | + MCF5272_FEC_INTERRUPT_MASK + ); + +} + +/* Generic Interrupt Service Routine. This routine wakes up the DSR */ +/* for further processing. */ + +static int +MCF5272_fec_isr(cyg_vector_t vector, cyg_addrword_t data, + HAL_SavedRegisters *regs) +{ + + /* Mask the FEC's interrupts so that it won't generate these */ + /* interrupts anymore as the driver reads the packets or acknowledges */ + /* packets. */ + + put_reg(MCF5272_SIM->enet.eimr, get_reg(MCF5272_SIM->enet.eimr) & + ~(MCF5272_FEC_INTERRUPT_MASK)); + + return CYG_ISR_CALL_DSR; +} + + +/* Call MCF5272_fec_deliver() to poll the FEC. */ + +static void +MCF5272_fec_int(struct eth_drv_sc *sc) +{ + MCF5272_fec_deliver(sc); +} + +static int +MCF5272_fec_int_vector(struct eth_drv_sc *sc) +{ + + /* How do you return multiple interrupt vector? */ + + return CYGNUM_HAL_VECTOR_ERX; +} + +/* This routine updates the Ethernet statistics counters. This method */ +/* is called by eCos every second. */ + +static void one_second_alarm_func(cyg_handle_t alarm, cyg_addrword_t data) +{ + #define WRAP_SUBTRACT(_VAL1_,_VAL2_) \ + ({unsigned long val;if (_VAL1_ >= _VAL2_) val = _VAL1_ - _VAL2_; \ + else val=(0-_VAL2_)+_VAL1_; val;}) + + ((MCF5272_fec_priv_data_t*)data)->diag_counters.rx_bytes_cnt_sec = + WRAP_SUBTRACT( + ((MCF5272_fec_priv_data_t*)data)->diag_counters.rx_bytes_cnt, + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_rx_bytes_cnt); + + ((MCF5272_fec_priv_data_t*)data)->diag_counters.tx_bytes_cnt_sec = + WRAP_SUBTRACT( + ((MCF5272_fec_priv_data_t*)data)->diag_counters.tx_bytes_cnt, + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_tx_bytes_cnt); + + ((MCF5272_fec_priv_data_t*)data)->diag_counters.rx_pk_cnt_sec = + WRAP_SUBTRACT( + ((MCF5272_fec_priv_data_t*)data)->diag_counters.rx_pk_cnt, + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_rx_pk_cnt); + + ((MCF5272_fec_priv_data_t*)data)->diag_counters.tx_pk_cnt_sec = + WRAP_SUBTRACT( + ((MCF5272_fec_priv_data_t*)data)->diag_counters.tx_pk_cnt, + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_tx_pk_cnt); + + + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_rx_bytes_cnt = + ((MCF5272_fec_priv_data_t*)data)->diag_counters.rx_bytes_cnt; + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_tx_bytes_cnt = + ((MCF5272_fec_priv_data_t*)data)->diag_counters.tx_bytes_cnt; + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_rx_pk_cnt = + ((MCF5272_fec_priv_data_t*)data)->diag_counters.rx_pk_cnt; + ((MCF5272_fec_priv_data_t*)data)->diag_info_sup.old_tx_pk_cnt = + ((MCF5272_fec_priv_data_t*)data)->diag_counters.tx_pk_cnt; +} + +/* Retrieve the stats information. */ + +void MCF5272_get_stats(struct eth_drv_sc *sc, MCF5272_FEC_DIAG* stats) +{ + memcpy(stats, &PMCF5272_FEC_DATA(sc)->diag_counters, + sizeof (MCF5272_FEC_DIAG)); + + /* Retrieve the number of available buffer descriptors and the */ + /* minimum value. */ + + PMCF5272_FEC_DATA(sc)->diag_counters.tx_free_bd_cnt = + NUM_TXBDS - PBUF_INFO(sc)->num_busy_bd; + PMCF5272_FEC_DATA(sc)->diag_counters.tx_free_min_bd_cnt = + NUM_TXBDS - PBUF_INFO(sc)->max_num_busy_bd; +} + + +/***************************************************************************** + + The following functions provide an interface directly to the +ethernet driver for applications that wish to circumvent the IP stack. + + Applications that wish to take advantage of this should override +these routine with their own. Leaving these routines as default routes +all data through the IP stack. + +*****************************************************************************/ + +/***************************************************************************** +eth_rx_pkt_filter -- Ethernet receive packet filter + + This is an ethernet packet filter function that allows the application +to receive raw ethernet frames from the driver. The return value of this +function determines whether or not to pass the packet to the IP stack. + + We declare it weak so that other routine can override it. + +INPUT: + + pkt: Pointer to the packet. + + pkt_len: The length of the packet including all headers, the 32-bit +Ethernet CRC, and any Ethernet frame padding. + +OUTPUT: + +RETURN VALUE: + + true: Do not send the packet to the IP stack. + + false: Send the packet to the IP stack. + +*****************************************************************************/ +int_t eth_rx_pkt_filter(u8_t * pkt, uint_t pkt_len) +{ + + /* Always return false by default. */ + + return false; +} + +/***************************************************************************** +eth_tx_check -- Watch transmitting Ethernet packets + + The driver calls this routine before transmitting packets from the +IP stack. It provides a hook for applications to watch all packets that +the IP stack transmits. + + We declare it weak so that other routine can override it. + +INPUT: + + sg_list: Pointer to the scatter-gather list. + + sg_len: The number of scatter-gather entries in the list. + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void eth_tx_check(struct eth_drv_sg * sg_list, unsigned int sg_len) +{ + + /* Do nothing by default. */ + +} + +/***************************************************************************** +eth_send -- Transmit a raw Ethernet packet + + This function sends a packet to the Ethernet controller thus +passing the eCos IP stack. + + Note that the application must reuse the buffer parameters to this +function until the driver releases the buffer with the eth_send_done() +function. + +INPUT: + + sg_list: Pointer to the scatter-gather list to send. + + sg_len: The size of the scatter-gather list. + + tag: A value that we pass as a parameter to eth_send_done() +function when the FEC has completed sending the packet. + +OUTPUT: + +RETURN VALUE: + + true: if the packet is successfully queued to the device driver's +queue. + + false : If the routine fails to send the packet. + +*****************************************************************************/ +int_t eth_send(struct eth_drv_sg* sg_list, unsigned int sg_len, + int total_len, + unsigned long tag) +{ + int_t success; + cyg_uint32 s; + + s = cyg_splsoftnet(); + + /* If there is enough buffer descriptors, then send the packet. */ + /* Otherwise, throw the packet away and return a false value. */ + + if (NUM_TXBDS - PBUF_INFO(&MCF5272_fec_sc)->num_busy_bd > sg_len) + { + + /* Call the common send routine to send the packet. */ + + MCF5272_fec_common_send(&MCF5272_fec_sc, + sg_list, + sg_len, + total_len, + tag, + TX_KEY_USER); + + success = true; + } + else + { + + /* Fail to send the packet. */ + + success = false; + } + + /* Release the Ethernet driver lock. */ + + cyg_splx(s); + + return success; +} + +/***************************************************************************** +eth_send_done -- eth_send callback + + The driver calls this function when it has sent out the packet. The +parameter tag is the same value as the tag value when the caller calls the +eth_send to send the packet. + + We declare it weak so that other routine can override it. + +INPUT: + + tag: A value that we pass as a parameter to eth_send_done() +function when the FEC has completed sending the packet. + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void eth_send_done(unsigned long tag) +{ + +} + + +#if 0 + + +/* Defined Ethernet Frame Types */ +#define FRAME_IP (0x0800) +#define FRAME_ARP (0x0806) +#define FRAME_RARP (0x8035) + +/* Offset and size of protocol headers */ +#define ETH_HDR_OFFSET 0 /* Ethernet header at the top of the frame */ +#define ETH_HDR_SIZE 14 + +/* Assign a protocol number for the loop test */ +static uint16 eth_type = 0x0300; + +/* Global variable containing length of data to transmit */ +static uint16 data_length = 512; + +/* Transmit data size of each transmti buffer descriptor. */ + +#define TX_BUFFER_SIZE (576) /* must be divisible by 16 */ + + +void +fec_start_loopback_test(void) +{ + /* Initalize the buffer descriptors. */ + + nbuf_init(&MCF5272_fec_priv_data.nbuffer); + + /* Initalize the Ethernet controllder device. */ + + MCF5272_fec_init(&MCF5272_fec_netdev); + + +} + +/********************************************************************/ +static void +loop_fill_buffers(void) +{ + /* Fill all the buffers in the TX buffer ring with a unique data pattern */ + uint16 index, pattern, i; + static unsigned char output_buffer[NUM_TXBDS][TX_BUFFER_SIZE]; + + + uint_t data_length = TX_BUFFER_SIZE; + + for (i = 0; i < NUM_TXBDS; i++) + { + + MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data = output_buffer[i]; + switch (i % 8) + { + /* Load buffers 0 through 3 with a single data patterns */ + case (0): + memset(&MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[ETH_HDR_SIZE],0x55,data_length); + break; + case (1): + memset(&MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[ETH_HDR_SIZE],0xAA,data_length); + break; + case (2): + memset(&MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[ETH_HDR_SIZE],0x00,data_length); + break; + case (3): + memset(&MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[ETH_HDR_SIZE],0xFF,data_length); + break; + + /* Buffer[4]: Load increasing walking ones */ + case (4): + pattern = 1; + for (index = 0; index < data_length; index++) + { + if (pattern == 0x0100) + pattern = 0x01; + MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[index] = (uint8)pattern; + pattern <<= 1; + } + break; + + /* Buffer[5]: Load decreasing walking ones */ + case(5): + pattern = 0x80; + for (index = 0; index < data_length; index++) + { + if (pattern == 0x00) + pattern = 0x80; + MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[index] = (uint8)pattern; + pattern >>= 1; + } + break; + + /* Buffer[6]: Load "Increment from 0" pattern */ + case (6): + for (index = 0; index < data_length; index++) + MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[index] = (uint8) ((index-14)%256); + break; + + /* Buffer[7]: Load "Decrement from 255" pattern */ + case (7): + for (index = 0; index < data_length; index++) + MCF5272_fec_priv_data.nbuffer.TxNBUF[i].data[index] = (uint8)(255- ((index-14)%256)); + break; + } + } +} + +/********************************************************************/ +void +loop_handler(void) +{ + + /* This is the loop specific RX handler called from the interrupt */ + /* receive routine. This routine gets bound to the loop protocol */ + /* (0x0300) by a call to nif_bind_protocol() and is then called in */ + /* fec_receive(). This function simply checks to make sure that the */ + /* receive buffer matches the transmit buffer. */ + + int i; + + /* Compare what I received to what I transmitted */ + for (i = 0; i < (data_length + ETH_HDR_SIZE); i++) + { + if (TxBuffer[fec_nif->f_rx % NUM_TXBDS].data[i] != pNbuf->data[i]) + { + /* Increment reception error count */ + fec_nif->f_rx_err++; + } + } + + /* Increment reception count */ + fec_nif->f_rx++; + + /* Update progress indicator */ + if (!(fec_nif->f_rx % 200)) + { + ihash = (ihash + 1) % 4; + diag_printf("\b%c",hash[ihash]); + } + + return; +} + +#endif + +
new file mode 100644 --- /dev/null +++ b/packages/devs/eth/mcf52xx/mcf5272/current/src/nbuf.c @@ -0,0 +1,98 @@ +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/devs/eth/nbuf.h> +/* + * Functions to manipulate the network buffers. + */ + +#include <cyg/hal/hal_intr.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/devs/eth/if_mcf5272.h> +#include <cyg/devs/eth/nbuf.h> +#include <cyg/infra/cyg_ass.h> + +/******************************************************************************* +nbuf_init() - Initalize the networ buffers. + +INPUT: pBuf - Pointer to the network buffer data. +*/ +void +nbuf_init (buf_info_t* pBuf) +{ + uint_t i = 0; + uint8 *buf = (uint8*)&(pBuf->RxBuffer); + buf = (uint8*)((((uint32)buf+15)/16)*16); + + /* Initialize RxNBUF and TxNBUF */ + pBuf->RxNBUF = (NBUF*)((((uint32)(&pBuf->nrxbuf[0])+3)/4)*4); + pBuf->TxNBUF = (NBUF*)((((uint32)(&pBuf->ntxbuf[0])+3)/4)*4); + + /* Initialize receive descriptor ring */ + for (i = 0; i < NUM_RXBDS; i++) + { + pBuf->RxNBUF[i].status = RX_BD_E; + pBuf->RxNBUF[i].length = 0; + pBuf->RxNBUF[i].data = buf; + buf += RX_BUFFER_SIZE; + } + /* Set the Wrap bit on the last one in the ring */ + pBuf->RxNBUF[NUM_RXBDS - 1].status |= RX_BD_W; + + /* Initialize transmit descriptor ring */ + for (i = 0; i < NUM_TXBDS; i++) + { + pBuf->TxNBUF[i].length = 0; + pBuf->TxNBUF[i].data = 0L; + pBuf->TxNBUF[i].status = 0; + } + /* Set the Wrap bit on the last one in the ring */ + pBuf->TxNBUF[NUM_TXBDS - 1].status |= TX_BD_W; + + /* Initialize the buffer descriptor indexes */ + pBuf->iTxbd = pBuf->iRxbd = 0; + + /* Intiaize the transmit key queue to zero. */ + pBuf->tq_front = pBuf->tq_rear = 0; + + // Initalize the nubmer of transmit buffer descriptors used to zero. + + pBuf->num_busy_bd = 0; +} + + + +
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mcf52xx/mcf5272/current/cdl/ser_mcf5272_uart.cdl @@ -0,0 +1,143 @@ +# ==================================================================== +# +# ser_MCF5272_uart.cdl +# +# eCos serial driver for MCF5272 UART +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_IO_SERIAL_MCF5272_UART { + display "Serial driver for MCF5272 UART" + + parent CYGPKG_IO_SERIAL_DEVICES + active_if CYGPKG_IO_SERIAL + requires CYGPKG_ERROR + include_dir cyg/io + description " + This option enables the serial device drivers for the + GMPU boards." + doc redirect/ecos-device-drivers.html + + compile -library=libextras.a ser_mcf5272_uart.c + + #define_proc { + # puts $::cdl_system_header "/***** serial driver proc output start *****/" + # puts $::cdl_system_header "#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_MCF52xx_ser_MFC5272_uart.h>" + # puts $::cdl_system_header "/***** serial driver proc output end *****/" + #} + + + cdl_component CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 { + display "MCF5272 UART serial port 0 driver" + flavor bool + default_value 1 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description "This option includes the serial device driver for the MCF5272 UART port 0." + + cdl_option CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL0_NAME { + display "Device name for the MCF5272 UART serial port 0 driver" + flavor data + default_value {"\"/dev/ser0\""} + description " + This option specifies the name of serial device for the + MCF5272 UART port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD { + display "Baud rate for the MCF5272 UART serial port 0 driver" + flavor data + legal_values {1200 2400 4800 9600 14400 19200 38400 115200} + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + MCF5272 UART port 0." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE { + display "Buffer size for the MCF5272 UART serial port 0 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MCF5272 UART port 0." + } + } + + cdl_component CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 { + display "MCF5272 UART serial port 1 driver" + flavor bool + default_value 0 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + description "This option includes the serial device driver for the MCF5272 UART port 1." + + cdl_option CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL1_NAME { + display "Device name for the MCF5272 UART serial port 1 driver" + flavor data + default_value {"\"/dev/ser1\""} + description " + This option specifies the name of serial device for the + MCF5272 UART port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BAUD { + display "Baud rate for the MCF5272 UART serial port 1 driver" + flavor data + legal_values {1200 2400 4800 9600 14400 19200 38400 115200} + default_value 9600 + description " + This option specifies the default baud rate (speed) for the + MCF5272 UART port 1." + } + + cdl_option CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE { + display "Buffer size for the MCF5272 UART serial port 1 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the MCF5272 UART port 1." + } + } +} +
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mcf52xx/mcf5272/current/include/ser_mcf5272_uart.h @@ -0,0 +1,130 @@ +#ifndef _SER_MCF5272_H_ +#define _SER_MCF5272_H_ +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/io_serial_mcf5272_uart.h> + +/* Bit level definitions and macros */ +#define MCF5272_UART_UMR1_RXRTS (0x80) +#define MCF5272_UART_UMR1_RXIRQ (0x40) +#define MCF5272_UART_UMR1_ERR (0x20) +#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C) +#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18) +#define MCF5272_UART_UMR1_PM_NONE (0x10) +#define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C) +#define MCF5272_UART_UMR1_PM_FORCE_LO (0x08) +#define MCF5272_UART_UMR1_PM_ODD (0x04) +#define MCF5272_UART_UMR1_PM_EVEN (0x00) +#define MCF5272_UART_UMR1_BC_5 (0x00) +#define MCF5272_UART_UMR1_BC_6 (0x01) +#define MCF5272_UART_UMR1_BC_7 (0x02) +#define MCF5272_UART_UMR1_BC_8 (0x03) + +#define MCF5272_UART_UMR2_CM_NORMAL (0x00) +#define MCF5272_UART_UMR2_CM_ECHO (0x40) +#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80) +#define MCF5272_UART_UMR2_CM_REMOTE_LOOP (0xC0) +#define MCF5272_UART_UMR2_TXRTS (0x20) +#define MCF5272_UART_UMR2_TXCTS (0x10) +#define MCF5272_UART_UMR2_STOP_BITS_1 (0x07) +#define MCF5272_UART_UMR2_STOP_BITS_15 (0x08) +#define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F) +#define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */ + +//#define MCF5272_UART_USR_RB (0x80) +//#define MCF5272_UART_USR_FE (0x40) +//#define MCF5272_UART_USR_PE (0x20) +//#define MCF5272_UART_USR_OE (0x10) +//#define MCF5272_UART_USR_TXEMP (0x08) +//#define MCF5272_UART_USR_TXRDY (0x04) +#define MCF5272_UART_USR_FFULL (0x02) +#define MCF5272_UART_USR_RXRDY (0x01) + +#define MCF5272_UART_UCSR_RCS(a) (((a)&0x0f)<<4) /* Rx Clk Select */ +#define MCF5272_UART_UCSR_TCS(a) ((a)&0x0f) /* Tx Clk Select */ + + +#define MCF5272_UART_UCR_NONE (0x00) +#define MCF5272_UART_UCR_ENAB (0x80) +#define MCF5272_UART_UCR_STOP_BREAK (0x70) +#define MCF5272_UART_UCR_START_BREAK (0x60) +#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50) +#define MCF5272_UART_UCR_RESET_ERROR (0x40) +#define MCF5272_UART_UCR_RESET_TX (0x30) +#define MCF5272_UART_UCR_RESET_RX (0x20) +#define MCF5272_UART_UCR_RESET_MR (0x10) +#define MCF5272_UART_UCR_TX_DISABLED (0x08) +#define MCF5272_UART_UCR_TX_ENABLED (0x04) +#define MCF5272_UART_UCR_RX_DISABLED (0x02) +#define MCF5272_UART_UCR_RX_ENABLED (0x01) + +#define MCF5272_UART_UCCR_COS (0x10) +#define MCF5272_UART_UCCR_CTS (0x01) + +#define MCF5272_UART_UACR_BRG (0x80) +#define MCF5272_UART_UACR_CTMS_TIMER (0x60) +#define MCF5272_UART_UACR_IEC (0x01) + +#define MCF5272_UART_UISR_COS (0x80) +#define MCF5272_UART_UISR_ABC (0x40) +#define MCF5272_UART_UISR_DB (0x04) +#define MCF5272_UART_UISR_RXRDY (0x02) +#define MCF5272_UART_UISR_TXRDY (0x01) + +#define MCF5272_UART_UIMR_COS (0x80) +#define MCF5272_UART_UIMR_ABC (0x40) +#define MCF5272_UART_UIMR_DB (0x04) +#define MCF5272_UART_UIMR_FFULL (0x02) +#define MCF5272_UART_UIMR_TXRDY (0x01) + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 +unsigned long MCF5272_uart_get_channel_0_baud_rate(void); +#endif /* CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 */ + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 +unsigned long MCF5272_uart_get_channel_1_baud_rate(void); +#endif /* CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 */ + +#endif /* _SER_MCF5272_H_ */ +
new file mode 100644 --- /dev/null +++ b/packages/devs/serial/mcf52xx/mcf5272/current/src/ser_mcf5272_uart.c @@ -0,0 +1,946 @@ +//========================================================================== +// +// devs/serial/MCF52xx/MCF5282 +// +// MCF5272 UART Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/io/io.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_memmap.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/drv_api.h> +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <pkgconf/io_serial_mcf5272_uart.h> +#include <cyg/io/ser_mcf5272_uart.h> + + +/* The UART priority level */ +#define MCF5272_UART_PRIORITY_LEVEL 2 + + +/* Autobaud states */ +typedef enum autobaud_states_t +{ + AB_IDLE = 0, /* Normal state. Autobaud process hasn't been initiated yet. */ + AB_BEGIN_BREAK, /* Detected a start of the break */ + AB_BEGIN, /* Detected the end of the break and has set up the autobaud.*/ + +}autobaud_states_t; + +#define FIELD_OFFSET(type,field) (cyg_uint32)(&(((type*)0)->field)) + +typedef struct MCF5272_uart_info_t +{ + + volatile mcf5272_sim_uart_t* base; // Base address of the UART registers + uint32 uart_vector; // UART interrupt vector number + + cyg_interrupt serial_interrupt; // Interrupt context + cyg_handle_t serial_interrupt_handle; // Interrupt handle + + volatile uint8 imr_mirror; // Interrupt mask register mirror + + cyg_serial_info_t config; // The channel configuration + + autobaud_states_t autobaud_state; // The autobaud state + + +} MCF5272_uart_info_t; + +/* Function prtoftyps for the MCF5272 UART ISR and DSR. */ +static cyg_uint32 MCF5272_uart_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void MCF5272_uart_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + + +/* Function prototypes for the serial functions. */ +static bool MCF5272_uart_init(struct cyg_devtab_entry * tab); +static Cyg_ErrNo MCF5272_uart_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static bool MCF5272_uart_putc(serial_channel *chan, unsigned char c); +static unsigned char MCF5272_uart_getc(serial_channel *chan); +Cyg_ErrNo MCF5272_uart_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len); +static void MCF5272_uart_start_xmit(serial_channel *chan); +static void MCF5272_uart_stop_xmit(serial_channel * chan); + + +/* Declare the serial functions that are called by the common serial driver layer. */ +static SERIAL_FUNS +( + MCF5272_uart_funs, + MCF5272_uart_putc, + MCF5272_uart_getc, + MCF5272_uart_set_config, + MCF5272_uart_start_xmit, + MCF5272_uart_stop_xmit +); + + +/* Definition for channel 0 UART configuration. */ +/************************************************/ +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 + +/* Data structure contains + channel informtion. + */ +static MCF5272_uart_info_t MCF5272_uart_channel_info_0; + +/* If the channel buffer size is zero, do not include interrupt UART processing */ +#if CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE > 0 + +/* Allocated receive and transmit buffer. The size of the buffer is */ +/* configured by the configtool. */ + +static unsigned char MCF5272_uart_out_buf0[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE]; +static unsigned char MCF5272_uart_in_buf0[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BUFSIZE]; + +/* Channel function table. We register the UART functions here so */ +/* that uppper serial drivers can call the serial driver's routines. */ + +static SERIAL_CHANNEL_USING_INTERRUPTS( + MCF5272_uart_channel_0, + MCF5272_uart_funs, + MCF5272_uart_channel_info_0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + MCF5272_uart_out_buf0, sizeof(MCF5272_uart_out_buf0), + MCF5272_uart_in_buf0, sizeof(MCF5272_uart_in_buf0) +); +#else +/* Don't use interrupt processing for the UART. */ +static SERIAL_CHANNEL( + MCF5272_uart_channel_0, + MCF5272_uart_funs, + MCF5272_uart_channel_info_0, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT +); +#endif + +DEVTAB_ENTRY( + MCF5272_uart_io0, + CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL0_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, // The table of I/O functions. + MCF5272_uart_init, // UART initialization function. + MCF5272_uart_lookup, // The UART lookup function. This function typically sets + // up the device for actual use, turing on interrupts, configuring the port, etc. + &MCF5272_uart_channel_0 +); +#endif // CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0 + +/* Definition for channel 1 UART configuration. */ +/************************************************/ + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 + + +/* Data structure contains + channel informtion. + */ +static MCF5272_uart_info_t MCF5272_uart_channel_info_1; + +/* If the channel buffer size is zero, do not include interrupt UART processing */ +#if CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE > 0 + +/* Allocated receive and transmit buffer. The size of the buffer is */ +/* configured by the configtool. */ + +static unsigned char MCF5272_uart_out_buf1[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE]; +static unsigned char MCF5272_uart_in_buf1[CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BUFSIZE]; + +/* Channel function table. We register the UART functions here so */ +/* that uppper serial drivers can call the serial driver's routines. */ + +static SERIAL_CHANNEL_USING_INTERRUPTS( + MCF5272_uart_channel_1, + MCF5272_uart_funs, + MCF5272_uart_channel_info_1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + MCF5272_uart_out_buf1, sizeof(MCF5272_uart_out_buf1), + MCF5272_uart_in_buf1, sizeof(MCF5272_uart_in_buf1) +); + +#else +static SERIAL_CHANNEL(MCF5272_uart_channel_1, + MCF5272_uart_funs, + MCF5272_uart_channel_info_1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL0_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +DEVTAB_ENTRY( + MCF5272_uart_io1, + CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL1_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, // The table of I/O functions. + MCF5272_uart_init, // UART initialization function. + MCF5272_uart_lookup, // The UART lookup function. This function typically sets + // up the device for actual use, turing on interrupts, configuring the port, etc. + &MCF5272_uart_channel_1 +); +#endif // CYGNUM_IO_SERIAL_MCF5272_UART_CHANNEL1 + + + +/* Definition of macros that access the UART's SIM registers */ +/* Read from a register */ + +#define MCF5272_UART_WRITE(_addr_,_value_) \ + *((volatile CYG_BYTE*)&(_addr_)) = (CYG_BYTE)(_value_) +/* Write to a register */ +#define MCF5272_UART_READ(_addr_) \ + *(volatile CYG_BYTE*)&(_addr_) + + +/* Function Prototypes */ +/* =================== */ +/* Internal function to actually configure the hardware to desired baud rate, etc. */ +static bool MCF5272_uart_config_port(serial_channel*, cyg_serial_info_t*); +static void MCF5272_uart_start_xmit(serial_channel*); + + +/* Baudrate conversion table. */ +static unsigned long baud_rates_table[]= +{ + 0, + 50, // CYGNUM_SERIAL_BAUD_50 = 1 + 75, // CYGNUM_SERIAL_BAUD_75 + 110, // CYGNUM_SERIAL_BAUD_110 + 134, // CYGNUM_SERIAL_BAUD_134_5 + 150, // CYGNUM_SERIAL_BAUD_150 + 200, // CYGNUM_SERIAL_BAUD_200 + 300, // CYGNUM_SERIAL_BAUD_300 + 600, // CYGNUM_SERIAL_BAUD_600 + 1200, // CYGNUM_SERIAL_BAUD_1200 + 1800, // CYGNUM_SERIAL_BAUD_1800 + 2400, // CYGNUM_SERIAL_BAUD_2400 + 3600, // CYGNUM_SERIAL_BAUD_3600 + 4800, // CYGNUM_SERIAL_BAUD_4800 + 7200, // CYGNUM_SERIAL_BAUD_7200 + 9600, // CYGNUM_SERIAL_BAUD_9600 + 14400, // CYGNUM_SERIAL_BAUD_14400 + 19200, // CYGNUM_SERIAL_BAUD_19200 + 38400, // CYGNUM_SERIAL_BAUD_38400 + 57600, // CYGNUM_SERIAL_BAUD_57600 + 115200, // CYGNUM_SERIAL_BAUD_115200 + 230400 // CYGNUM_SERIAL_BAUD_230400 +}; + +/* The table contains divers to divide the clock to configre a */ +/* approppriate for the UART. */ + +static unsigned long dividers_table[]= +{ + 0, + 46080, // 50 + 30720, // 75 + 20945, // 110 + 17130, // 134_5 + 15360, // 150 + 11520, // 200 + 7680, // 300 + 3840, // 600 + 1920, // 1200 + 1280, // 1800 + 960, // 2400 + 640, // 3600 + 480, // 4800 + 320, // 7200 + 240, // 9600 + 160, // 14400 + 120, // 19200 + 60, // 38400 + 40, // 57600 + 20, // 115200 + 10 // 230400 +}; + +/******************************************************************************* + MCF5272_uart_init() - This routine is called during bootstrap to set up the + UART driver. + + INPUT: + Pointer to the the device table. + + RETURN: + Returns true if the initialization is successful. Otherwise, it retuns false +*/ +static bool MCF5272_uart_init(struct cyg_devtab_entry * tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + MCF5272_uart_info_t *MCF5272_uart_chan = (MCF5272_uart_info_t *)chan->dev_priv; + + #ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 + + /* Instantiation of the UART channel 0 data strucutre. This data */ + /* structure contains channel information. */ + + if (strcmp(tab->name, CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL0_NAME) == 0) + { + + /* Initiliaze the UART information data to all zeros. */ + + memset(MCF5272_uart_chan, sizeof(MCF5272_uart_info_t), 0); + + /* Set the base address of the UART registers to differentiate */ + /* itself from the different regusters for the other UART port. */ + + MCF5272_uart_chan->base = (mcf5272_sim_uart_t*)&MCF5272_SIM->uart[0]; + + /* Set the UART interrupt vector number. */ + + MCF5272_uart_chan->uart_vector = CYGNUM_HAL_VECTOR_UART1; + + /* Set the autobaud state to idle. */ + + MCF5272_uart_chan->autobaud_state = AB_IDLE; + + /* Initilize the UART 0 output pins */ + + MCF5272_SIM->gpio.pbcnt = MCF5272_GPIO_PBCNT_URT0_EN | + ((MCF5272_SIM->gpio.pbcnt) & ~MCF5272_GPIO_PBCNT_URT0_MSK); + } + #endif + + #ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 + + /* Instantiation of the UART channel 1 data strucutre. This data structure contains + channel information. + */ + if (strcmp(tab->name, CYGDAT_IO_SERIAL_MCF5272_UART_CHANNEL1_NAME) == 0) + { + + /* Initiliaze the UART information data to all zeros. */ + + memset(MCF5272_uart_chan, sizeof(MCF5272_uart_info_t), 0); + + /* Set the base address of the UART registers to differentiate */ + /* itself from the different regusters for the other UART port. */ + + MCF5272_uart_chan->base = (mcf5272_sim_uart_t*)&MCF5272_SIM->uart[1]; + + /* Set the UART interrupt vector number. */ + + MCF5272_uart_chan->uart_vector = CYGNUM_HAL_VECTOR_UART2; + + /* Set the autobaud state to idle. */ + + MCF5272_uart_chan->autobaud_state = AB_IDLE; + + /* Initilize the UART 1 output pins */ + + MCF5272_SIM->gpio.pdcnt = MCF5272_GPIO_PDCNT_URT1_EN | + ((MCF5272_SIM->gpio.pdcnt) & ~MCF5272_GPIO_PDCNT_URT1_MSK); + + } + #endif + + + if (chan->out_cbuf.len > 0) { + + /* If the the buffer is greater than zero, then the driver will */ + /* use interrupt driven I/O. Hence, the driver creates an */ + /* interrupt context for the UART device. */ + + cyg_drv_interrupt_create(MCF5272_uart_chan->uart_vector, + MCF5272_UART_PRIORITY_LEVEL, // Priority - Level 2 + (cyg_addrword_t)chan, // Data item passed to interrupt handler + MCF5272_uart_ISR, + MCF5272_uart_DSR, + &MCF5272_uart_chan->serial_interrupt_handle, + &MCF5272_uart_chan->serial_interrupt); + + cyg_drv_interrupt_attach(MCF5272_uart_chan->serial_interrupt_handle); + + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + } + + // Configure Serial device. + return(MCF5272_uart_config_port(chan, &chan->config)); +} + +/****************************************************************************************************** + MCF5272_uart_config_port() - Configure the UART port. + + Internal function to actually configure the hardware to desired baud rate, etc. + + INPUT: + chan - The channel information + new_confg - The port configuration which include the desired baud rate, etc. + + RETURN: + Returns true if the port configuration is successful. Otherwise, it retuns false + + */ +static bool MCF5272_uart_config_port(serial_channel *chan, + cyg_serial_info_t *new_config) +{ + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + uint8 mode_reg = 0; + uint32 ubgs; + unsigned int baud_divisor; + + + /* Get the divisor from the baudrate table which will use to */ + /* configure the port's baud rate. */ + + baud_divisor = baud_rates_table[new_config->baud]; + + /* If the divisor is zeor, we dont' configure the port. */ + + if (baud_divisor == 0) return false; + + /* Save the configuration value for later use. */ + + port->config = *new_config; + + /* We first write the reset values into the device and then configure */ + /* the device the we way we want to use it. */ + + /* Reset Transmitter */ + + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_TX); + + /* Reset Receiver */ + + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_RX); + + /* Reset Mode Register */ + + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_MR); + + /* Translate the parity configuration to UART mode bits. */ + + switch(port->config.parity) + { + default: + case CYGNUM_SERIAL_PARITY_NONE: + mode_reg = 0 | MCF5272_UART_UMR1_PM_NONE; + break; + case CYGNUM_SERIAL_PARITY_EVEN: + mode_reg = 0 | MCF5272_UART_UMR1_PM_EVEN; + break; + case CYGNUM_SERIAL_PARITY_ODD: + mode_reg = 0 | MCF5272_UART_UMR1_PM_ODD; + break; + case CYGNUM_SERIAL_PARITY_MARK: + mode_reg = 0 | MCF5272_UART_UMR1_PM_FORCE_HI; + break; + case CYGNUM_SERIAL_PARITY_SPACE: + mode_reg = 0 | MCF5272_UART_UMR1_PM_FORCE_LO; + break; + } + + /* Translate the number of bits per character configuration to UART mode bits. */ + + switch(port->config.word_length) + { + + case CYGNUM_SERIAL_WORD_LENGTH_5: + mode_reg |= MCF5272_UART_UMR1_BC_5; + break; + case CYGNUM_SERIAL_WORD_LENGTH_6: + mode_reg |= MCF5272_UART_UMR1_BC_6; + break; + case CYGNUM_SERIAL_WORD_LENGTH_7: + mode_reg |= MCF5272_UART_UMR1_BC_7; + break; + default: + case CYGNUM_SERIAL_WORD_LENGTH_8: + mode_reg |= MCF5272_UART_UMR1_BC_8; + break; + } + + /* Configure the parity and the bits per character */ + + MCF5272_UART_WRITE(port->base->umr, mode_reg); + + /* Translate the stop bit length to UART mode bits. */ + + switch(port->config.stop) + { + default: + case CYGNUM_SERIAL_STOP_1: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_1; + break; + case CYGNUM_SERIAL_STOP_1_5: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_15; + break; + case CYGNUM_SERIAL_STOP_2: + mode_reg = MCF5272_UART_UMR2_STOP_BITS_2; + break; + } + + /* No echo or loopback */ + + MCF5272_UART_WRITE(port->base->umr, 0 | MCF5272_UART_UMR2_CM_NORMAL | mode_reg); + + /* Set Rx and Tx baud by timer */ + + MCF5272_UART_WRITE(port->base->ucr, 0 | MCF5272_UART_UCSR_RCS(0xD) | + MCF5272_UART_UCSR_TCS(0xD)); + + /* Mask all USART interrupts */ + + MCF5272_UART_WRITE(port->base->uisr_uimr, 0); + + /* Calculate baud settings */ + + ubgs = (uint16)((CYGHWR_HAL_SYSTEM_CLOCK_MHZ*1000000)/ + (baud_divisor * 32)); + + /* Program the baud settings to the device. */ + + MCF5272_UART_WRITE(port->base->udu, (uint8)((ubgs & 0xFF00) >> 8)); + MCF5272_UART_WRITE(port->base->udl, (uint8)(ubgs & 0x00FF)); + + /* Enable receiver and transmitter */ + + MCF5272_UART_WRITE(port->base->ucr, 0 | MCF5272_UART_UCR_TXRXEN); + + /* Enable both transmit and receive interrupt. */ + + port->imr_mirror = MCF5272_UART_UIMR_TXRDY | MCF5272_UART_UIMR_FFULL | + MCF5272_UART_UIMR_DB; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + + return true; /* Returns true to indicate a successful configuration */ + +} + +/******************************************************************************* + MCF5272_uart_lookup() - This routine is called when the device is "looked" up + (i.e. attached) + + INPUT: + tab - pointer to a pointer of the device table + sub_tab - Pointer to the sub device table. + name - name of the device + + RETURN: + always return ENOERR + +*/ +static Cyg_ErrNo MCF5272_uart_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +/******************************************************************************* + MCF5272_uart_putc() - Send a character to the device output buffer. + + INPUT: + chan - pointer to the serial private data. + c - the character to output + + RETURN: + 'true' if character is sent to device, return 'false' when we've + ran out of buffer space in the device itself. + +*/ + +static bool MCF5272_uart_putc(serial_channel *chan, unsigned char c) +{ + CYG_INTERRUPT_STATE int_state; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *)chan->dev_priv; + + /* Make sure the transmitter is not full. If it is full, return false. */ + if (!(MCF5272_UART_READ(port->base->usr_ucsr) & MCF5272_UART_USR_TXRDY)) + return false; + + /* Enable transmit interrupt. */ + HAL_DISABLE_INTERRUPTS(int_state); + port->imr_mirror |= MCF5272_UART_UIMR_TXRDY; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + HAL_RESTORE_INTERRUPTS(int_state); + + /* Enable the UART transmit. */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_TXRXEN); + + /* Send the character */ + MCF5272_UART_WRITE(port->base->urb_utb, c); + + return true ; +} + + +/****************************************************************************************************** + MCF5272_uart_getc() - Fetch a character from the device input bufferand return it to the alling + routine. Wait until there is a character ready. + + INPUT: + chan - pointer to the serial private data. + + RETURN: + the character read from the UART. + + */ +static unsigned char MCF5272_uart_getc(serial_channel *chan) +{ + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *)chan->dev_priv; + + /* Wait until character has been received */ + + while (!(MCF5272_UART_READ(port->base->usr_ucsr) & MCF5272_UART_USR_RXRDY)) + { + diag_printf("ready poll"); + } + + /* Read the character from the FIFO queue. */ + + return MCF5272_UART_READ(port->base->urf); + +} + + +/******************************************************************************* + MCF5272_uart_set_config() - Set up the device characteristics; baud rate, etc. + + INPUT: + chan - pointer to the serial private data. + key - configuration key (command). + xbuf - pointer to the configuration buffer + len - the length of the configuration buffer + + RETURN: + NOERR - If the configuration is successful + EINVAL - If the argument is invalid + +*/ + +Cyg_ErrNo MCF5272_uart_set_config(serial_channel *chan, cyg_uint32 key, + const void *xbuf, cyg_uint32 *len) +{ + cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + + switch (key) { + case CYG_IO_SET_CONFIG_SERIAL_INFO: + { + /* Set serial configuration. */ + if ( *len < sizeof(cyg_serial_info_t) ) { + return EINVAL; + } + *len = sizeof(cyg_serial_info_t); + + if (!MCF5272_uart_config_port(chan, config)) + return EINVAL; + } + break; + + case CYG_IO_GET_CONFIG_SERIAL_INFO: + // Retrieve UART configuration + *config = port->config; + break; + + default: + return EINVAL; + } + return ENOERR; +} + + +/******************************************************************************* + MCF5272_uart_start_xmit() - Enable the transmitter on the device. + + INPUT: + chan - pointer to the serial private data. + +*/ +static void MCF5272_uart_start_xmit(serial_channel *chan) +{ + CYG_INTERRUPT_STATE int_state; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + /* Enable the UART transmit. */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_TXEN); + + /* Enable transmit interrupt */ + HAL_DISABLE_INTERRUPTS(int_state); + port->imr_mirror |= MCF5272_UART_UIMR_TXRDY; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + HAL_RESTORE_INTERRUPTS(int_state); + + +} + + +/****************************************************************************************************** + MCF5272_uart_stop_xmit() - Disable the transmitter on the device + + INPUT: + chan - pointer to the serial private data. + +*/ +static void MCF5272_uart_stop_xmit(serial_channel * chan) +{ + CYG_INTERRUPT_STATE int_state; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + /* Disable transmit interrupt */ + HAL_DISABLE_INTERRUPTS(int_state); + port->imr_mirror &= ~MCF5272_UART_UIMR_TXRDY; + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + HAL_RESTORE_INTERRUPTS(int_state); + + /* Disable the UART transmit. + !!!!!!!!!!!!! + !!!WARNING!!! + !!!!!!!!!!!!! + If the transmit the disabe + the diag_printf routines will poll forever to transmit the + a character. Hence, don't ever disable the transmit if + we want it to work with diag_printf. + */ + //MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_TXDE); + + +} + + +/****************************************************************************************************** + MCF5272_uart_ISR() - UART I/O interrupt interrupt service routine (ISR). + + INPUT: + vector - the interrupt vector number + data - user parameter. + + + RETURN: + returns CYG_ISR_CALL_DSR to call the DSR. + + */ +static cyg_uint32 MCF5272_uart_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *) data; + MCF5272_uart_info_t * port = (MCF5272_uart_info_t *) chan->dev_priv; + + + /* Write the value in the interrupt status register back + to the mask register to disable the interrupt temporarily. + */ + + MCF5272_UART_WRITE(port->base->uisr_uimr, 0); + + return CYG_ISR_CALL_DSR; // Cause DSR to run +} + + + +/****************************************************************************************************** + MCF5272_uart_DSR() - Defered Service Routine (DSR) - This routine processes the interrupt + from the device. + + INPUT: + vector - The interrupt vector number + count - The nunber of DSR requests. + data - Device specific information + +*/ + +static void MCF5272_uart_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + MCF5272_uart_info_t *port = (MCF5272_uart_info_t *)chan->dev_priv; + volatile u8_t isr; + + + /* Retrieve the interrupt status bits. We use these status bits to figure out + what process shouled we perform: read from the UART or inform of a completion + of a data transmission. + */ + + /* Retrieve the interrupt status register so + * the DSR can look it up. + */ + + + while((isr = (MCF5272_UART_READ(port->base->uisr_uimr) & port->imr_mirror))) + { + switch (port->autobaud_state) + { + default: + case AB_IDLE: + if (isr & MCF5272_UART_UISR_DB) + { + /* Detected the begin of a break, set the state to AB_BEGIN_BREAK + */ + port->autobaud_state = AB_BEGIN_BREAK; + + /* Reset the Delta Break bit in the UISR */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_BKCHGINT); + + } + break; + case AB_BEGIN_BREAK: + if (isr & MCF5272_UART_UISR_DB) + { + /* Detected the end of a break, set the state to AB_BEGIN, and + setup autobaud detection. + */ + port->autobaud_state = AB_BEGIN; + + /* Reset the Delta Break bit in the UISR and Enable autobaud */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_RESET_BKCHGINT | + MCF5272_UART_UCR_ENAB); + + /* Enable autobaud completion interrupt */ + port->imr_mirror |= MCF5272_UART_UIMR_ABC; + /* Disable the delta break interrupt so we can't receive + anymore break interrupt. + */ + port->imr_mirror &= ~MCF5272_UART_UIMR_DB; + + } + break; + + case AB_BEGIN: + if (isr & MCF5272_UART_UISR_ABC) + { + int count; + // Retrieve the baudrate that we're using now. + u16_t divider = (port->base->uabu << 8) + port->base->uabl; + // Search in the list to find a match. + for (count = sizeof(dividers_table)/sizeof(unsigned long) - 1; + count >= 0; + count--) + { + if (divider < dividers_table[count]) break; + } + + // Set the baud. + port->config.baud = count; + + /* Autobaud completion */ + port->autobaud_state = AB_IDLE; + + /* Disable autobaud */ + MCF5272_UART_WRITE(port->base->ucr, MCF5272_UART_UCR_NONE); + + /* Ignore autobaud completion interrupt. */ + port->imr_mirror &= ~MCF5272_UART_UIMR_ABC; + + /* Reenable begin break change and receive interrupt. */ + port->imr_mirror |= MCF5272_UART_UIMR_DB; + + } + break; + + } + + + /* Receive character interrupt */ + if ((isr & MCF5272_UART_UISR_RXRDY)) + /* Ignore all receive interrupt when we're autobauding. */ + { + // Read all the characters in the fifo. + while ((MCF5272_UART_READ(port->base->uisr_uimr) & MCF5272_UART_UISR_RXRDY)) + { + char c; + /* Read the character from the UART. */ + c = MCF5272_UART_READ(port->base->urb_utb); + /* Pass the read character to the upper layer. */ + (chan->callbacks->rcv_char)(chan, c); + } + } + + /* Transmit complete interrupt */ + + if ((isr & MCF5272_UART_UISR_TXRDY)) + { + + /* Transmit holding register is empty */ + (chan->callbacks->xmt_char)(chan); + + } + + } + + /* Unmask all the DUART interrupts that were masked in the ISR, so */ + /* that we can receive the next interrupt. */ + + MCF5272_UART_WRITE(port->base->uisr_uimr, port->imr_mirror); + +} + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 +unsigned long MCF5272_uart_get_channel_0_baud_rate() +{ + /* return the baud rate for the first serial port */ + + return baud_rates_table[MCF5272_uart_channel_info_0.config.baud]; +} +#endif + +#ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 +unsigned long MCF5272_uart_get_channel_1_baud_rate() +{ + /* return the baud rate for the second serial port */ + + return baud_rates_table[MCF5272_uart_channel_info_1.config.baud]; +} +#endif + +
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -892,6 +892,15 @@ package CYGPKG_IO_SERIAL_H8300_SCI { description "H8/300 SCI serial device drivers" } +package CYGPKG_IO_SERIAL_MCF5272_UART { + alias { "MCF5272 Serial UART Drivers" + devs_MCF5272_uart_driver } + hardware + directory devs/serial/mcf52xx/mcf5272 + script ser_mcf5272_uart.cdl + description "Serial MCF5272 UART Drivers." +} + package CYGPKG_IO_SERIAL_LOOP { alias { "Loop serial device drivers" devs_serial_loop loop_serial_driver } @@ -1295,6 +1304,14 @@ package CYGPKG_DEVS_ETH_H8300_AKI3068NET micom board." } +package CYGPKG_DEVS_ETH_MCF5272 { + alias { "MCF5272 Fast Ethernet Controller driver" mcf5272_eth_driver} + hardware + directory devs/eth/mcf52xx/mcf5272 + script mcf5272_eth_driver.cdl + description "Ethernet driver for the MCF5272." +} + package CYGPKG_IO_PCI { alias { "PCI configuration library" io_pci } @@ -2709,6 +2726,65 @@ evaluation board." } # -------------------------------------------------------------------------- +# m68k packages + +package CYGPKG_HAL_M68K { + alias { "m68k common HAL" hal_m68k m68k_hal m68k_arch_hal } + directory hal/m68k/arch + script hal_m68k.cdl + hardware + + description "The m68k architecture HAL package provides generic + support for this processor architecture. It is also + necessary to select a specific target platform HAL + package." + +} + +package CYGPKG_HAL_M68K_MCF52xx { + alias { "68k/Coldfire version 2 core variant HAL" + hal_m68k_mcf52xx + m68k_mcf52xx_hal } + directory hal/m68k/mcf52xx/var + script hal_m68k_mcf52xx.cdl + hardware + + description "The 68k/Coldfire version 2 core variant HAL package + provides generic support for the version 2 Coldfire core. + It is also necessary to select a specific target platform + HAL package." +} + +package CYGPKG_HAL_M68K_MCF52xx_MCF5272 { + alias { "mcf5272 68k/Coldfire processor variant HAL" + hal_m68k_mcf52xx_mcf5272 + m68k_mcf52xx_mcf5272_hal } + directory hal/m68k/mcf52xx/mcf5272/proc + script hal_m68k_mcf52xx_mcf5272.cdl + hardware + + description "The mcf5272 68k/Coldfire processor variant HAL package + provides generic support for this processor architecture. + It is also necessary to select a specific target platform + HAL package." + +} + +package CYGPKG_HAL_M68K_MCF52xx_MCF5272_MCF5272C3 { + alias { "Motorola mcf5272c3 evaluation board platform HAL" + hal_m68k_mcf52xx_mcf5272_mcf5272c3 + m68k_mcf52xx_mcf5272_mcf5272c3_hal } + directory hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf + script hal_m68k_mcf52xx_mcf5272_mcf5272c3.cdl + hardware + + description "The Motorola mcf5272c3 evaluation board platform HAL + package should be used when targeting the actual hardware + for the Motorola mcf5272c3 evaluation board platform." + +} + +# -------------------------------------------------------------------------- # CalmRISC16 packages package CYGPKG_HAL_CALM16 { @@ -3751,6 +3827,27 @@ Cosmo CEB-V850 evaluation board fitted w } # -------------------------------------------------------------------------- +# m68k targets + +target mcf5272c3 { + alias { "Motorola mcf5272c3 evaluation board" } + packages { + CYGPKG_HAL_M68K + CYGPKG_HAL_M68K_MCF52xx + CYGPKG_HAL_M68K_MCF52xx_MCF5272 + CYGPKG_HAL_M68K_MCF52xx_MCF5272_MCF5272C3 + CYGPKG_DEVS_ETH_MCF5272 + CYGPKG_IO_SERIAL_MCF5272_UART + } + + description "The mcf5272c3 target provides the packages needed to run + eCos on the Motorola mcf5272c3 evaluation board." + +} + +# -------------------------------------------------------------------------- + +# -------------------------------------------------------------------------- # H8 targets target h8300h_sim {
--- a/packages/hal/arm/at91/current/ChangeLog +++ b/packages/hal/arm/at91/current/ChangeLog @@ -1,3 +1,7 @@ +2002-05-28 Thomas Koeller <Thomas.Koeller@baslerweb.com> + + * include/plf_io.h: Add watchdog definitions. + 2002-05-08 Gary Thomas <gthomas@redhat.com> * misc/redboot_ROMRAM.ecm:
--- a/packages/hal/arm/at91/current/include/plf_io.h +++ b/packages/hal/arm/at91/current/include/plf_io.h @@ -298,7 +298,7 @@ #define AT91_EBI 0xFFE00000 #define AT91_EBI_RCR 0x20 // Reset control -// Power Saveings control +// Power Savings control #define AT91_PS 0xFFFF4000 #define AT91_PS_CR 0x000 // Control @@ -306,6 +306,25 @@ #define AT91_PS_PCDR 0x004 // Peripheral clock disable #define AT91_PS_PCSR 0x004 // Peripheral clock status +// Watchdog + +#define AT91_WD 0xFFFF8000 +#define AT91_WD_OMR 0x00 +#define AT91_WD_OMR_WDEN 0x00000001 +#define AT91_WD_OMR_RSTEN 0x00000002 +#define AT91_WD_OMR_IRQEN 0x00000004 +#define AT91_WD_OMR_EXTEN 0x00000008 +#define AT91_WD_OMR_OKEY (0x00000234 << 4) +#define AT91_WD_CMR 0x04 +#define AT91_WD_CMR_WDCLKS 0x00000003 +#define AT91_WD_CMR_HPCV 0x0000003C +#define AT91_WD_CMR_CKEY (0x0000006E << 7) +#define AT91_WD_CR 0x08 +#define AT91_WD_CR_RSTKEY 0x0000C071 +#define AT91_WD_SR 0x0C +#define AT91_WD_SR_WDOVF 0x00000001 + + //----------------------------------------------------------------------------- // end of plf_io.h #endif // CYGONCE_HAL_PLF_IO_H
--- a/packages/hal/arm/integrator/current/ChangeLog +++ b/packages/hal/arm/integrator/current/ChangeLog @@ -1,3 +1,7 @@ +2002-05-27 Jesper Skov <jskov@redhat.com> + + * cdl/hal_arm_integrator.cdl: Don't run cache tests. + 2002-05-07 Gary Thomas <gthomas@redhat.com> * cdl/hal_arm_integrator.cdl:
--- a/packages/hal/arm/integrator/current/cdl/hal_arm_integrator.cdl +++ b/packages/hal/arm/integrator/current/cdl/hal_arm_integrator.cdl @@ -64,6 +64,7 @@ cdl_package CYGPKG_HAL_ARM_INTEGRATOR { implements CYGINT_HAL_DEBUG_GDB_STUBS implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_TESTS_NO_CACHES define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
--- a/packages/hal/arm/iq80310/current/ChangeLog +++ b/packages/hal/arm/iq80310/current/ChangeLog @@ -1,3 +1,9 @@ +2002-05-24 Jonathan Larmour <jlarmour@redhat.com> + + * src/hal_diag.c: Support dynamic getting and setting of baud rates. + * cdl/hal_arm_iq80310.cdl: implements + CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + 2002-05-14 Jesper Skov <jskov@redhat.com> * include/plf_io.h (CYGARC_VIRT_TO_BUS, CYGARC_UNCACHED_ADDRESS):
--- a/packages/hal/arm/iq80310/current/cdl/hal_arm_iq80310.cdl +++ b/packages/hal/arm/iq80310/current/cdl/hal_arm_iq80310.cdl @@ -65,6 +65,7 @@ cdl_package CYGPKG_HAL_ARM_IQ80310 { implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT implements CYGINT_HAL_ARM_MEM_REAL_REGION_TOP implements CYGINT_HAL_ARM_ARCH_XSCALE + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
--- a/packages/hal/arm/iq80310/current/src/hal_diag.c +++ b/packages/hal/arm/iq80310/current/src/hal_diag.c @@ -94,32 +94,19 @@ cyg_hal_plf_comms_init(void) #define CYG_DEV_SERIAL_BASE_B 0xfe810000 // port B //----------------------------------------------------------------------------- -// Default baud rate is 38400 // Based on 3.6864 MHz xtal -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x0c -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x06 -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x03 -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x02 -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x01 -#endif +struct baud_config { + cyg_int32 baud_rate; + cyg_uint8 msb; + cyg_uint8 lsb; +}; -#ifndef CYG_DEV_SERIAL_BAUD_MSB -#error Missing/incorrect serial baud rate defined - CDL error? -#endif +struct baud_config baud_conf[] = { + {9600, 0x00, 0x0c}, + {19200, 0x00, 0x06}, + {38400, 0x00, 0x03}, + {57600, 0x00, 0x02}, + {115200, 0x00, 0x01}}; //----------------------------------------------------------------------------- // Define the serial registers. The Cogent board is equipped with a 16552 @@ -190,24 +177,41 @@ typedef struct { cyg_uint8* base; cyg_int32 msec_timeout; int isr_vector; + cyg_int32 baud_rate; } channel_data_t; //----------------------------------------------------------------------------- +static int +set_baud( channel_data_t *chan ) +{ + cyg_uint8* base = chan->base; + cyg_uint8 i; + + for (i=0; i<(sizeof(baud_conf)/sizeof(baud_conf[0])); i++) + { + if (chan->baud_rate == baud_conf[i].baud_rate) { + cyg_uint8 lcr; + HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr); + HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr|SIO_LCR_DLAB); + HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, baud_conf[i].lsb); + HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, baud_conf[i].msb); + HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr); + return 1; + } + } + return -1; +} + static void init_serial_channel(const channel_data_t* __ch_data) { cyg_uint8* base = __ch_data->base; - cyg_uint8 lcr; + channel_data_t* chan = (channel_data_t*)__ch_data; // 8-1-no parity. - lcr = SIO_LCR_WLS0 | SIO_LCR_WLS1; - - lcr |= SIO_LCR_DLAB; - HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr); - HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB); - HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB); - lcr &= ~SIO_LCR_DLAB; - HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr); + HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1); + chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; + set_baud( chan ); HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO } @@ -349,6 +353,18 @@ cyg_hal_plf_serial_control(void *__ch_da va_end(ap); } + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + { + va_list ap; + va_start(ap, __func); + chan->baud_rate = va_arg(ap, cyg_int32); + va_end(ap); + ret = set_baud(chan); + break; + } default: break; }
--- a/packages/hal/arm/xscale/iq80321/current/ChangeLog +++ b/packages/hal/arm/xscale/iq80321/current/ChangeLog @@ -1,3 +1,9 @@ +2002-05-24 Jonathan Larmour <jlarmour@redhat.com> + + * src/hal_diag.c: Support dynamic getting and setting of baud rates. + * cdl/hal_arm_xscale_iq80321.cdl: implements + CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + 2002-05-07 Gary Thomas <gthomas@redhat.com> * cdl/hal_arm_xscale_iq80321.cdl:
--- a/packages/hal/arm/xscale/iq80321/current/cdl/hal_arm_xscale_iq80321.cdl +++ b/packages/hal/arm/xscale/iq80321/current/cdl/hal_arm_xscale_iq80321.cdl @@ -63,6 +63,7 @@ cdl_package CYGPKG_HAL_ARM_XSCALE_IQ8032 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT implements CYGINT_HAL_ARM_MEM_REAL_REGION_TOP + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
--- a/packages/hal/arm/xscale/iq80321/current/src/hal_diag.c +++ b/packages/hal/arm/xscale/iq80321/current/src/hal_diag.c @@ -72,31 +72,20 @@ //----------------------------------------------------------------------------- // Based on 1.8432 MHz xtal -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x0c -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x06 -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x03 -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x02 -#endif -#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200 -#define CYG_DEV_SERIAL_BAUD_MSB 0x00 -#define CYG_DEV_SERIAL_BAUD_LSB 0x01 -#endif + +struct baud_config { + cyg_int32 baud_rate; + cyg_uint8 msb; + cyg_uint8 lsb; +}; -#ifndef CYG_DEV_SERIAL_BAUD_MSB -#error Missing/incorrect serial baud rate defined - CDL error? -#endif - +struct baud_config baud_conf[] = { + {9600, 0x00, 0x0c}, + {19200, 0x00, 0x06}, + {38400, 0x00, 0x03}, + {57600, 0x00, 0x02}, + {115200, 0x00, 0x01}}; + // Define the serial registers. #define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0 #define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0 @@ -157,26 +146,43 @@ typedef struct { cyg_uint8* base; cyg_int32 msec_timeout; int isr_vector; + cyg_int32 baud_rate; } channel_data_t; //----------------------------------------------------------------------------- +static int +set_baud( channel_data_t *chan ) +{ + cyg_uint8* base = chan->base; + cyg_uint8 i; + + for (i=0; i<(sizeof(baud_conf)/sizeof(baud_conf[0])); i++) + { + if (chan->baud_rate == baud_conf[i].baud_rate) { + cyg_uint8 lcr; + HAL_READ_UINT8(base+CYG_DEV_LCR, lcr); + HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr|SIO_LCR_DLAB); + HAL_WRITE_UINT8(base+CYG_DEV_DLL, baud_conf[i].lsb); + HAL_WRITE_UINT8(base+CYG_DEV_DLM, baud_conf[i].msb); + HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr); + return 1; + } + } + return -1; +} + static void cyg_hal_plf_serial_init_channel(void* __ch_data) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; - cyg_uint8 lcr; - + channel_data_t* chan = (channel_data_t*)__ch_data; + // 8-1-no parity. HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1); - HAL_READ_UINT8(base+CYG_DEV_LCR, lcr); - lcr |= SIO_LCR_DLAB; - HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr); - HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEV_SERIAL_BAUD_LSB); - HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEV_SERIAL_BAUD_MSB); - lcr &= ~SIO_LCR_DLAB; - HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr); + chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; + set_baud( chan ); HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO } @@ -308,6 +314,18 @@ cyg_hal_plf_serial_control(void *__ch_da va_end(ap); } + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + { + va_list ap; + va_start(ap, __func); + chan->baud_rate = va_arg(ap, cyg_int32); + va_end(ap); + ret = set_baud(chan); + break; + } default: break; }
--- a/packages/hal/arm/xscale/verde/current/ChangeLog +++ b/packages/hal/arm/xscale/verde/current/ChangeLog @@ -1,3 +1,9 @@ +2002-05-24 Jonathan Larmour <jlarmour@redhat.com> + + * cdl/hal_arm_xscale_verde.cdl: Remove implement of + CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT since platforms should + define whether baud rate changes are possible. + 2002-04-01 Rory Bolt <rorybolt@pacbell.net> * include/hal_var_ints.h: Fix definition for DMA1_ERR.
--- a/packages/hal/arm/xscale/verde/current/cdl/hal_arm_xscale_verde.cdl +++ b/packages/hal/arm/xscale/verde/current/cdl/hal_arm_xscale_verde.cdl @@ -61,7 +61,6 @@ cdl_package CYGPKG_HAL_ARM_XSCALE_VERDE package." implements CYGINT_HAL_ARM_ARCH_XSCALE - implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT # Let the architectural HAL see this variant's interrupts file define_proc {
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/cdl/hal_m68k.cdl @@ -0,0 +1,77 @@ +# ==================================================================== +# +# hal_m68k.cdl +# +# m68k architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_HAL_M68K { + display "m68k architecture" + parent CYGPKG_HAL + hardware + include_dir cyg/hal + define_header hal_m68k.h + description " + The m68k architecture HAL package provides generic + support for this processor architecture. It is also + necessary to select a specific target platform HAL + package." + + cdl_interface CYGINT_HAL_M68K_VARIANT { + display "Number of variant implementations in this configuration" + requires 1 == CYGINT_HAL_M68K_VARIANT + } + + compile hal_startup.c hal_misc.c m68k_stub.c hal_arch.S + + make { + <PREFIX>/lib/target.ld: <PACKAGE>/src/m68k.ld + $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/m68k.ld" } + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/basetype.h @@ -0,0 +1,91 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H + +//============================================================================= +// +// basetype.h +// +// Standard types for this architecture. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +// Include variant specific types. +#include <cyg/hal/var_basetype.h> + +// Include the standard variable sizes. +#include <cyg/hal/gen_types.h> + +//----------------------------------------------------------------------------- +// Characterize the architecture + +#define CYG_BYTEORDER CYG_MSBFIRST // Big endian + +//----------------------------------------------------------------------------- +// 68k does not usually use labels with underscores. Some labels generated +// by the linker do, so add an underscore where required. + +#define CYG_LABEL_NAME(_name_) _##_name_ + +// The 68k architecture uses the default definitions of the base types, +// so we do not need to define any here. + +//----------------------------------------------------------------------------- +// Override the alignment definitions from cyg_type.h. +// Most 68k variants use a 4 byte alignment. +// A few variants (68000) may override this setting to use a 2 byte alignment. +#ifndef CYGARC_ALIGNMENT +#define CYGARC_ALIGNMENT 4 +#endif +// the corresponding power of two alignment +#ifndef CYGARC_P2ALIGNMENT +#define CYGARC_P2ALIGNMENT 2 +#endif + + +//----------------------------------------------------------------------------- +// Define a compiler-specific rune for saying a function doesn't return + +// WARNING: There is a bug in some versions of gcc for the m68k that does +// not handle the noreturn attribute correctly. It is safe to just disable +// this attribute. + +#ifndef CYGBLD_ATTRIB_NORET +# define CYGBLD_ATTRIB_NORET +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_BASETYPE_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/gen_types.h @@ -0,0 +1,136 @@ +#ifndef _GEN_TYPES_H +#define _GEN_TYPES_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +/***************************************************************************** + + ********************* + * * + * General Types * + * * + ********************* + + Define some simple variable sizes for this platform. + + Note that these types are useful for making user threads that are +not eCos-specific. + +*****************************************************************************/ + +// Include some architecture variant specific types. + +#include <cyg/hal/var_gen_types.h> + +// Define types to use for specific sized variables. Note that the above +// include file could have defined some of these types differently. If the +// type is already defined, always use the previous definition. + +#ifndef _GEN_TYPES_I8_T +#define _GEN_TYPES_I8_T char +#endif +#ifndef _GEN_TYPES_I16_T +#define _GEN_TYPES_I16_T short +#endif +#ifndef _GEN_TYPES_I32_T +#define _GEN_TYPES_I32_T int +#endif +#ifndef _GEN_TYPES_I64_T +#define _GEN_TYPES_I64_T long long +#endif +#ifndef _GEN_TYPES_S8_T +#define _GEN_TYPES_S8_T signed _GEN_TYPES_I8_T +#endif +#ifndef _GEN_TYPES_S16_T +#define _GEN_TYPES_S16_T signed _GEN_TYPES_I16_T +#endif +#ifndef _GEN_TYPES_S32_T +#define _GEN_TYPES_S32_T signed _GEN_TYPES_I32_T +#endif +#ifndef _GEN_TYPES_S64_T +#define _GEN_TYPES_S64_T signed _GEN_TYPES_I64_T +#endif +#ifndef _GEN_TYPES_U8_T +#define _GEN_TYPES_U8_T unsigned _GEN_TYPES_I8_T +#endif +#ifndef _GEN_TYPES_U16_T +#define _GEN_TYPES_U16_T unsigned _GEN_TYPES_I16_T +#endif +#ifndef _GEN_TYPES_U32_T +#define _GEN_TYPES_U32_T unsigned _GEN_TYPES_I32_T +#endif +#ifndef _GEN_TYPES_U64_T +#define _GEN_TYPES_U64_T unsigned _GEN_TYPES_I64_T +#endif +#ifndef _GEN_TYPES_ADDR_T +#define _GEN_TYPES_ADDR_T void * +#endif + +typedef _GEN_TYPES_I8_T i8_t; +typedef _GEN_TYPES_I16_T i16_t; +typedef _GEN_TYPES_I32_T i32_t; +typedef _GEN_TYPES_I64_T i64_t; +typedef _GEN_TYPES_S8_T s8_t; +typedef _GEN_TYPES_S16_T s16_t; +typedef _GEN_TYPES_S32_T s32_t; +typedef _GEN_TYPES_S64_T s64_t; +typedef _GEN_TYPES_U8_T u8_t; +typedef _GEN_TYPES_U16_T u16_t; +typedef _GEN_TYPES_U32_T u32_t; +typedef _GEN_TYPES_U64_T u64_t; +typedef _GEN_TYPES_ADDR_T addr_t; + +// Use int_t and uint_t for fast counter variables. The size of these +// types depends on the architecture but it will always be at least 16 bits. +// For example, 16-bit numbers are faster on the 68000 but 32-bit numbers are +// faster on the mcf5200. If you need to assume the size of the variable use +// u16_t or u32_t instead. + +#ifndef _GEN_TYPES_INT_T +#define _GEN_TYPES_INT_T i32_t +#endif +#ifndef _GEN_TYPES_SINT_T +#define _GEN_TYPES_SINT_T s32_t +#endif +#ifndef _GEN_TYPES_UINT_T +#define _GEN_TYPES_UINT_T u32_t +#endif + +typedef _GEN_TYPES_INT_T int_t; +typedef _GEN_TYPES_SINT_T sint_t; +typedef _GEN_TYPES_UINT_T uint_t; + +#endif // _GEN_TYPES_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/hal_arch.h @@ -0,0 +1,390 @@ +#ifndef CYGONCE_HAL_ARCH_H +#define CYGONCE_HAL_ARCH_H + +//============================================================================= +// +// hal_arch.h +// +// Architecture specific abstractions +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// Include some variant specific architectural defines. +#include <cyg/hal/var_arch.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +#include <cyg/hal/m68k_stub.h> +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#ifndef HAL_NORMAL_SAVED_CONTEXT +/***************************************************************************** +HAL_NORMAL_SAVED_CONTEXT -- Saved by a normal context switch + + Define a generic structure to save a thread context. Some +architecture variants will want to redefine this. + +*****************************************************************************/ +typedef struct +{ + + // Data regs D0-D7 + + #define HAL_NORMAL_SAVED_NUM_D_REGS 8 + CYG_WORD32 d[HAL_NORMAL_SAVED_NUM_D_REGS]; + + // Address regs A0-A6 + + #define HAL_NORMAL_SAVED_NUM_A_REGS 7 + CYG_ADDRESS a[HAL_NORMAL_SAVED_NUM_A_REGS]; + + // Program Counter + + CYG_ADDRESS pc; + +} __attribute__ ((aligned, packed)) HAL_SavedRegisters_normal; +#endif // HAL_NORMAL_SAVED_CONTEXT + +#ifndef HAL_GENERIC_SAVED_CONTEXT +/***************************************************************************** +HAL_GENERIC_SAVED_CONTEXT -- Generic saved context structure + + This is a generic structure that should describe various saved +processor contexts on this platform. + + If the variant HAL does not define this, just define a saved register +structure with a normal context. + +*****************************************************************************/ +#define HAL_GENERIC_SAVED_CONTEXT \ +typedef union \ +{ \ + HAL_SavedRegisters_normal normal; \ +} __attribute__ ((aligned, packed)) HAL_SavedRegisters; +#endif // HAL_GENERIC_SAVED_CONTEXT +HAL_GENERIC_SAVED_CONTEXT; + +#ifndef HAL_THREAD_SWITCH_CONTEXT +/***************************************************************************** +HAL_THREAD_SWITCH_CONTEXT + + This macro saves the state of the currently running thread and writes +its stack pointer to *(_fspptr_). + + It then switches to the thread context that *(_tspptr_) points to. + +INPUT: + + _fspptr_: A pointer to the location to save the current thread's stack +pointer to. + + _tspptr_: A pointer to the location containing the stack pointer of +the thread context to switch to. + +OUTPUT: + + *(_fspptr_): Contains the stack pointer of the previous thread's +context. + +*****************************************************************************/ +#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ +CYG_MACRO_START \ + asm volatile (" pea 1f(%%pc)\n" \ + " lea -(8+7)*4(%%sp),%%sp\n" \ + " movem.l %%d0-%%d7/%%a0-%%a6,(%%sp)\n" \ + " move.l %%sp,%0\n" \ + " move.l %1,%%sp\n" \ + " movem.l (%%sp),%%d0-%%d7/%%a0-%%a6\n" \ + " lea (8+7)*4(%%sp),%%sp\n" \ + " rts\n" \ + "1:\n" \ + : "=g" (*(_fspptr_)) \ + : "g" (*(_tspptr_)) \ + : "memory"); \ +CYG_MACRO_END +#if HAL_NORMAL_SAVED_NUM_D_REGS != 8 + #error +#endif +#if HAL_NORMAL_SAVED_NUM_A_REGS != 7 + #error +#endif +#endif // HAL_THREAD_SWITCH_CONTEXT + +#ifndef HAL_THREAD_LOAD_CONTEXT +/***************************************************************************** +HAL_THREAD_LOAD_CONTEXT + + This macro loads the thread context that *(_tspptr_) points to. + + This macro does not return. + +INPUT: + + _tspptr_: A pointer to the location containing the stack pointer of +the thread context to switch to. + +*****************************************************************************/ +#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ +CYG_MACRO_START \ + asm volatile (" move.l %0,%%sp\n" \ + " movem.l (%%sp),%%d0-%%d7/%%a0-%%a6\n" \ + " lea (8+7)*4(%%sp),%%sp\n" \ + " rts\n" \ + : \ + : "g" (*(_tspptr_)) \ + : "memory"); \ +CYG_MACRO_END +#if HAL_NORMAL_SAVED_NUM_D_REGS != 8 + #error +#endif +#if HAL_NORMAL_SAVED_NUM_A_REGS != 7 + #error +#endif +#endif // HAL_THREAD_LOAD_CONTEXT + +#ifndef HAL_THREAD_INIT_CONTEXT +/***************************************************************************** +HAL_THREAD_INIT_CONTEXT -- Context Initialization + + Initialize the context of a thread. + +INPUT: + + _sparg_: The name of the variable containing the current sp. This +will be written with the new sp. + + _thread_: The thread object address, passed as argument to entry +point. + + _entry_: The thread's entry point address. + + _id_: A bit pattern used in initializing registers, for debugging. + +OUTPUT: + + _sparg_: Updated with the value of the new sp. + +*****************************************************************************/ +#define HAL_THREAD_INIT_CONTEXT(_sparg_, _thread_, _entry_, _id_) \ + CYG_MACRO_START \ + CYG_WORD32 * _sp_ = ((CYG_WORD32*)((CYG_WORD32)(_sparg_) & ~15)); \ + HAL_SavedRegisters_normal * _regs_; \ + int _i_; \ + \ + *(--_sp_) = (CYG_WORD32)(_thread_); /* Thread's parameter. */ \ + *(--_sp_) = (CYG_WORD32)0xDEADC0DE; /* Thread's return addr. */ \ + \ + _regs_ = (HAL_SavedRegisters_normal*) \ + ((CYG_WORD32)_sp_ - sizeof(HAL_SavedRegisters_normal)); \ + \ + for (_i_=0; _i_ < HAL_NORMAL_SAVED_NUM_A_REGS; _i_++) \ + _regs_->a[_i_] = _regs_->d[_i_] = (_id_); \ + _regs_->d[_i_] = (_id_); /* D7 */ \ + /* A6, initial frame pointer should be null */ \ + _regs_->a[HAL_NORMAL_SAVED_NUM_A_REGS-1] = (CYG_ADDRESS)0; \ + /* Thread's starting PC */ \ + _regs_->pc = (CYG_ADDRESS)(_entry_); \ + \ + (_sparg_) = (CYG_ADDRESS)_regs_; \ + CYG_MACRO_END +#endif // HAL_THREAD_INIT_CONTEXT + +//----------------------------------------------------------------------------- +// Bit manipulation routines + +externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); +externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); + +#define HAL_LSBIT_INDEX(index, mask) (index) = hal_lsbit_index(mask); + +#define HAL_MSBIT_INDEX(index, mask) (index) = hal_msbit_index(mask); + +//----------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. + +externC void hal_idle_thread_action(cyg_uint32 loop_count); + +#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) + +//----------------------------------------------------------------------------- +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. + +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +//----------------------------------------------------------------------------- +// Breakpoint support +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen +// if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. + +#define HAL_BREAKPOINT(_label_) \ +asm volatile (" .globl " #_label_ ";" \ + #_label_":" \ + " trap #1" \ + ); + +#define HAL_BREAKINST 0x4E41 + +#define HAL_BREAKINST_SIZE 2 + +#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYGPKG_HAL_EXCEPTIONS) + +//----------------------------------------------------------------------------- +// Exception handling function. +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. + +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); + +#endif /* defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) */ + +//----------------------------------------------------------------------------- +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. + +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! + +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// Stack frame overhead per call. 6 data registers, 5 address registers, +// frame pointer, and return address. We can't guess the local variables so +// just assume that using all of the registers averages out. + +#define CYGNUM_HAL_STACK_FRAME_SIZE ((6 + 5 + 1 + 1) * 4) + +// Stack needed for a context switch. +// All registers + pc + sr + vector + +#ifndef CYGNUM_HAL_STACK_CONTEXT_SIZE +#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((8+8+1+1+1)*4) +#endif // CYGNUM_HAL_STACK_CONTEXT_SIZE + +// Interrupt + call to ISR, interrupt_end() and the DSR + +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ + ((CYGNUM_HAL_STACK_CONTEXT_SIZE) + (8*CYGNUM_HAL_STACK_FRAME_SIZE)) + +// We define a minimum stack size as the minimum any thread could ever +// legitimately get away with. We can throw asserts if users ask for less +// than this. Allow enough for four interrupt sources - clock, serial, +// nic, and one other + +// No separate interrupt stack exists. Make sure all threads contain +// a stack sufficiently large + +#define CYGNUM_HAL_STACK_SIZE_MINIMUM \ + ((4*CYGNUM_HAL_STACK_INTERRUPT_SIZE) \ + + (16*CYGNUM_HAL_STACK_FRAME_SIZE)) + +// Now make a reasonable choice for a typical thread size. Pluck figures +// from thin air and say 30 call frames with an average of 16 words of +// automatic variables per call frame + +#define CYGNUM_HAL_STACK_SIZE_TYPICAL \ + (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ + (30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4)))) + +//-------------------------------------------------------------------------- +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +#ifndef HAL_SETJMP +#define HAL_SETJMP +/***************************************************************************** +hal_setjmp/hal_longjmp + + We do the best we can to define generic setjmp and longjmp routines +for the m68k architecture. Some architectures will need to override this. + +*****************************************************************************/ + +// We must save all of the registers that are preserved across routine +// calls. The assembly code assumes that this structure is defined in the +// following format. Any changes to this structure will result in changes to +// the assembly code!! + +typedef struct { + cyg_uint32 d2; + cyg_uint32 d3; + cyg_uint32 d4; + cyg_uint32 d5; + cyg_uint32 d6; + cyg_uint32 d7; + cyg_uint32 a2; + cyg_uint32 a3; + cyg_uint32 a4; + cyg_uint32 a5; + cyg_uint32 a6; + cyg_uint32 sp; + cyg_uint32 pc; +} hal_jmp_buf_t; + +// This type is used by normal routines to pass the address of the +// structure into our routines without having to explicitly take the address +// of the structure. + +typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)]; + +// Define the generic setjmp and longjmp routines. + +externC int hal_m68k_setjmp(hal_jmp_buf env); +externC void hal_m68k_longjmp(hal_jmp_buf env, int val); +#define hal_setjmp(_env) hal_m68k_setjmp(_env) +#define hal_longjmp(_env, _val) hal_m68k_longjmp(_env, _val) +#endif // HAL_SETJMP + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_ARCH_H +// End of hal_arch.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/hal_cache.h @@ -0,0 +1,52 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/var_cache.h> + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/hal_diag.h @@ -0,0 +1,89 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####UNSUPPORTEDBEGIN#### +// +// ------------------------------------------- +// This source file has been contributed to eCos/Red Hat. It may have been +// changed slightly to provide an interface consistent with those of other +// files. +// +// The functionality and contents of this file is supplied "AS IS" +// without any form of support and will not necessarily be kept up +// to date by Red Hat. +// +// All inquiries about this file, or the functionality provided by it, +// should be directed to the 'ecos-discuss' mailing list (see +// http://sourceware.cygnus.com/ecos/intouch.html for details). +// +// Maintained by: <Unmaintained> +// ------------------------------------------- +// +//####UNSUPPORTEDEND#### +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(cyg_int8 c); + +externC cyg_int8 hal_diag_read_char(void); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) ((_c_) = hal_diag_read_char()) + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/hal_intr.h @@ -0,0 +1,259 @@ +#ifndef CYGONCE_HAL_HAL_INTR_H +#define CYGONCE_HAL_HAL_INTR_H + +//========================================================================== +// +// hal_intr.h +// +// m68k Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_arch.h> + +#include <cyg/hal/var_intr.h> + +//-------------------------------------------------------------------------- +// m68k exception vectors. These correspond to VSRs and are the values +// to use for HAL_VSR_GET/SET +#define CYGNUM_HAL_VECTOR_SSP 0 +#define CYGNUM_HAL_VECTOR_RESET 1 +#define CYGNUM_HAL_VECTOR_BUSERR 2 +#define CYGNUM_HAL_VECTOR_ADDERR 3 +#define CYGNUM_HAL_VECTOR_ILLINST 4 +#define CYGNUM_HAL_VECTOR_ZERODIV 5 +#define CYGNUM_HAL_VECTOR_CHKINST 6 +#define CYGNUM_HAL_VECTOR_TRAPVINST 7 +#define CYGNUM_HAL_VECTOR_PRIVVIOLATION 8 +#define CYGNUM_HAL_VECTOR_TRACE 9 +#define CYGNUM_HAL_VECTOR_L1010 10 +#define CYGNUM_HAL_VECTOR_L1111 11 +#define CYGNUM_HAL_VECTOR_UNINITINT 15 +#define CYGNUM_HAL_VECTOR_SPURINT 24 +#define CYGNUM_HAL_VECTOR_AUTOVEC1 25 +#define CYGNUM_HAL_VECTOR_AUTOVEC2 26 +#define CYGNUM_HAL_VECTOR_AUTOVEC3 27 +#define CYGNUM_HAL_VECTOR_AUTOVEC4 28 +#define CYGNUM_HAL_VECTOR_AUTOVEC5 29 +#define CYGNUM_HAL_VECTOR_AUTOVEC6 30 +#define CYGNUM_HAL_VECTOR_AUTOVEC7 31 +#define CYGNUM_HAL_VECTOR_NMI CYGNUM_HAL_VECTOR_AUTOVEC7 +#define CYGNUM_HAL_VECTOR_TRAPFIRST 32 +#define CYGNUM_HAL_VECTOR_NUMTRAPS 16 +#define CYGNUM_HAL_VECTOR_TRAPLAST (CYGNUM_HAL_VECTOR_TRAPFIRST+CYGNUM_HAL_VECTOR_NUMTRAPS-1) +#define CYGNUM_HAL_VECTOR_INTRFIRST 64 +#define CYGNUM_HAL_VECTOR_NUMINTRS 192 +#define CYGNUM_HAL_VECTOR_INTRLAST (CYGNUM_HAL_VECTOR_INTRFIRST+CYGNUM_HAL_VECTOR_NUMINTRS-1) + +#define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_SSP +#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTRLAST +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +#ifndef CYGNUM_HAL_ISR_MAX +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 255 +#define CYGNUM_HAL_ISR_COUNT (7+CYGNUM_HAL_VECTOR_NUMINTRS) +#endif /* CYGNUM_HAL_ISR_MAX */ + +#ifndef CYGNUM_HAL_EXCEPTION_COUNT +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VECTOR_BUSERR +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_SPURINT +#define CYGNUM_HAL_EXCEPTION_COUNT ((CYGNUM_HAL_EXCEPTION_MAX-CYGNUM_HAL_EXCEPTION_MIN)+1) +#endif /* CYGNUM_HAL_EXCEPTION_COUNT */ + +//-------------------------------------------------------------------------- +// Static data used by HAL + +// ISR tables +externC volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +externC volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +// VSR table +externC volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; + +//--------------------------------------------------------------------------- +// Translate a vector number into an ISR table index. + +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ + CYG_MACRO_START \ + switch ((_vector_)) \ + { \ + case CYGNUM_HAL_VECTOR_AUTOVEC1 ... CYGNUM_HAL_VECTOR_AUTOVEC7: \ + (_index_) = ((_vector_) - CYGNUM_HAL_VECTOR_AUTOVEC1); \ + break; \ + case CYGNUM_HAL_VECTOR_INTRFIRST ... CYGNUM_HAL_VECTOR_INTRLAST: \ + (_index_) = ((_vector_) \ + - CYGNUM_HAL_VECTOR_INTRFIRST \ + + (CYGNUM_HAL_VECTOR_AUTOVEC7 \ + - CYGNUM_HAL_VECTOR_AUTOVEC1 \ + + 1)); \ + break; \ + default: \ + CYG_FAIL("Unknown Interrupt!!!"); \ + (_index_) = (typeof(_index_))-1; \ + } \ + CYG_MACRO_END + +//-------------------------------------------------------------------------- +// Interrupt state storage + +typedef cyg_uint16 CYG_INTERRUPT_STATE; + +//--------------------------------------------------------------------------- +// Interrupt and VSR attachment macros + +externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); +externC void hal_default_exception_handler(CYG_WORD vector, + HAL_SavedRegisters *regs); + +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if (cyg_hal_interrupt_handlers[_index_] \ + ==(CYG_ADDRESS)&hal_default_isr) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR((_vector_), _index_); \ + \ + if (cyg_hal_interrupt_handlers[_index_] \ + ==(CYG_ADDRESS)&hal_default_isr) \ + { \ + cyg_hal_interrupt_handlers[_index_] = (CYG_ADDRESS)(_isr_); \ + cyg_hal_interrupt_data[_index_] = (CYG_ADDRWORD)(_data_); \ + cyg_hal_interrupt_objects[_index_] = (CYG_ADDRESS)(_object_); \ + } \ + CYG_MACRO_END + +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ +CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_INTERRUPT_MASK(_vector_); \ + HAL_TRANSLATE_VECTOR((_vector_), _index_); \ + if (cyg_hal_interrupt_handlers[_index_] \ + == (CYG_ADDRESS)(_isr_)) \ + { \ + cyg_hal_interrupt_handlers[_index_] = \ + (CYG_ADDRESS)&hal_default_isr; \ + cyg_hal_interrupt_data[_index_] = 0; \ + cyg_hal_interrupt_objects[_index_] = 0; \ + } \ +CYG_MACRO_END + +#define HAL_VSR_GET( _vector_, _pvsr_ ) \ + *((CYG_ADDRESS *)(_pvsr_)) = cyg_hal_vsr_table[(_vector_)]; + + +#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \ + CYG_MACRO_START \ + if( (_poldvsr_) != NULL ) \ + *(CYG_ADDRESS *)(_poldvsr_) = cyg_hal_vsr_table[(_vector_)]; \ + cyg_hal_vsr_table[(_vector_)] = (CYG_ADDRESS)(_vsr_); \ + CYG_MACRO_END + +//-------------------------------------------------------------------------- +// Interrupt control macros + +// The following interrupt control macros are the default for the 68k +// architecture. Some architectures will override these definitions by +// defining them in their var_intr.h file. Some architectures support +// instructions like andi.w #xxxx,%sr but others (Coldfire) do not. +// Architectures that support these other instructions will want to define +// their own macros. + +#define HAL_M68K_SET_SR(__newsr__) \ + CYG_MACRO_START \ + asm volatile ("move.w %0,%%sr\n" \ + : \ + : "g" ((CYG_INTERRUPT_STATE)(__newsr__))); \ + CYG_MACRO_END + +#ifndef HAL_ENABLE_INTERRUPTS +#define HAL_ENABLE_INTERRUPTS() \ + CYG_MACRO_START \ + CYG_INTERRUPT_STATE _msk_; \ + HAL_QUERY_INTERRUPTS(_msk_); \ + HAL_M68K_SET_SR((_msk_ & (CYG_INTERRUPT_STATE)0xf8ff)); \ + CYG_MACRO_END +#endif // HAL_ENABLE_INTERRUPTS + +#ifndef HAL_DISABLE_INTERRUPTS +#define HAL_DISABLE_INTERRUPTS(_old_) \ + CYG_MACRO_START \ + HAL_QUERY_INTERRUPTS(_old_); \ + HAL_M68K_SET_SR((_old_ | (CYG_INTERRUPT_STATE)0x0700)); \ + CYG_MACRO_END +#endif //HAL_DISABLE_INTERRUPTS + +#define HAL_RESTORE_INTERRUPTS(_prev_) \ + CYG_MACRO_START \ + CYG_INTERRUPT_STATE _msk_; \ + HAL_QUERY_INTERRUPTS(_msk_); \ + _msk_ &= (CYG_INTERRUPT_STATE)0xf8ff; \ + _msk_ |= (((CYG_INTERRUPT_STATE)(_prev_)) \ + & (CYG_INTERRUPT_STATE)0x0700); \ + asm volatile ("move.w %0,%%sr\n" \ + : \ + : "g" (_msk_)); \ + CYG_MACRO_END + +// Use the extra assignment to avoid warnings. +// The compiler should optimize it out. +#define HAL_QUERY_INTERRUPTS(__oldmask__) \ + CYG_MACRO_START \ + CYG_INTERRUPT_STATE _omsk_ = (CYG_INTERRUPT_STATE)(__oldmask__); \ + asm volatile ("move.w %%sr,%0\n" \ + : "=g" (_omsk_) \ + : ); \ + (__oldmask__) = (typeof(__oldmask__))_omsk_; \ + CYG_MACRO_END + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_INTR_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/hal_io.h @@ -0,0 +1,146 @@ +#ifndef CYGONCE_HAL_HAL_IO_H +#define CYGONCE_HAL_HAL_IO_H + +//============================================================================= +// +// hal_io.h +// +// HAL device IO register support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// IO Register address. +// This type is for recording the address of an IO register. + +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +#define HAL_READ_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +#define HAL_READ_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))); \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + CYG_MACRO_START \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \ + CYG_MACRO_END + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ + } \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ + } \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_HAL_IO_H +// End of hal_io.h
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/hal_startup.h @@ -0,0 +1,15 @@ +#ifndef _HAL_STARTUP_H +#define _HAL_STARTUP_H + +#include <cyg/infra/cyg_type.h> + +// Include the variant-specific startup header. + +#include <cyg/hal/var_startup.h> + +// Declare the routine to call to simulate a hardware reset. + +externC void hal_hw_reset(void); + +#endif // _HAL_STARTUP_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/include/m68k_stub.h @@ -0,0 +1,129 @@ +#ifndef CYGONCE_HAL_M68K_STUB_H +#define CYGONCE_HAL_M68K_STUB_H +//======================================================================== +// +// m68k_stub.h +// +// M68K-specific definitions for generic stub +// +//======================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//======================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + + + +#ifdef CYGPKG_IO_SERIAL +#include <pkgconf/io_serial.h> +#endif + +#include <cyg/hal/hal_diag.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC + +#define HAL_STUB_PLATFORM_INIT_SERIAL() HAL_DIAG_INIT() + +#define HAL_STUB_PLATFORM_GET_CHAR() \ +((cyg_int8)({ \ + cyg_int8 _ch_; \ + HAL_DIAG_READ_CHAR(_ch_); \ + _ch_; \ +})) + +#define HAL_STUB_PLATFORM_PUT_CHAR(c) HAL_DIAG_WRITE_CHAR((c)) + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int,(baud)) + +#define HAL_STUB_PLATFORM_RESET() HAL_DIAG_INIT() + +#define HAL_STUB_PLATFORM_INIT() HAL_DIAG_INIT() + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + + + +#define NUMREGS 18 + +#define REGSIZE( _x_ ) (4) + +typedef unsigned long target_register_t; + +enum regnames { + D0, D1, D2, D3, D4, D5, D6, D7, + A0, A1, A2, A3, A4, A5, FP, SP, + PS, PC, +}; + +typedef enum regnames regnames_t; + +/* Given a trap value TRAP, return the corresponding signal. */ +externC int __computeSignal (unsigned int trap_number); + +/* Return the SPARC trap number corresponding to the last-taken trap. */ +externC int __get_trap_number (void); + +/* Return the currently-saved value corresponding to register REG. */ +externC target_register_t get_register (regnames_t reg); + +/* Store VALUE in the register corresponding to WHICH. */ +externC void put_register (regnames_t which, target_register_t value); + +/* Set the currently-saved pc register value to PC. This also updates NPC + as needed. */ +externC void set_pc (target_register_t pc); + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ +externC void __single_step (void); + +/* Clear the single-step state. */ +externC void __clear_single_step (void); + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ +externC int __is_breakpoint_function (void); + +/* Skip the current instruction. */ +externC void __skipinst (void); + +externC void __install_breakpoints (void); + +externC void __clear_breakpoints (void); + +#endif // ifndef CYGONCE_HAL_M68K_STUB_H
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/src/hal_arch.S @@ -0,0 +1,156 @@ +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +/***************************************************************************** +hal_arch.S -- m68k architecture code +*****************************************************************************/ + +#include <pkgconf/hal.h> + +/***************************************************************************** +FUNC_START -- Function declaration macro +*****************************************************************************/ +#define FUNC_START(name) \ + .text; \ + .even; \ + .globl name; \ +name: + +/***************************************************************************** + The following routines assume the hal_jmp_buf structure is defined as +shown below. + +typedef struct { + cyg_uint32 d2; + cyg_uint32 d3; + cyg_uint32 d4; + cyg_uint32 d5; + cyg_uint32 d6; + cyg_uint32 d7; + cyg_uint32 a2; + cyg_uint32 a3; + cyg_uint32 a4; + cyg_uint32 a5; + cyg_uint32 a6; + cyg_uint32 sp; + cyg_uint32 pc; +} hal_jmp_buf_t; +typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)]; +*****************************************************************************/ + +/***************************************************************************** +hal_m68k_setjmp -- Generic setjmp for the m68k architecture + +externC int hal_m68k_setjmp(hal_jmp_buf env); + +INPUT: + + 0(%sp): return address + + 4(%sp): env - address of a hal_jmp_buf structure + +OUTPUT: + + d0, d1, a0, a1 are ours to abuse. + +RETURN VALUE: + + This routine always returns zero in d0.l. + +*****************************************************************************/ +FUNC_START(hal_m68k_setjmp) + + lea.l 4(%sp),%a1 /* Get a pointer to the position */ + /* of the stack pointer before this */ + /* call was made. IMPORTANT: The */ + /* longjmp routine and the */ + /* exception handler assume that */ + /* saved stack pointers point to */ + /* the location of the stack before */ + /* the routine/exception occurred. */ + + move.l (%a1),%a0 /* Get a pointer to the buffer to */ + /* save our state into. */ + + movem.l %d2-%d7/%a2-%a6,(%a0) /* Write all of the preserved */ + lea (11*4)(%a0),%a0 /* registers, the stack pointer, */ + move.l %a1,(%a0)+ /* and the return address into the */ + move.l (%sp),(%a0) /* structure. */ + + moveq.l #0,%d0 /* Load a zero return value and */ + rts /* return. */ + +/***************************************************************************** +hal_m68k_longjmp -- Generic longjmp for the m68k architecture + +externC void hal_m68k_longjmp(hal_jmp_buf env, int val); + +INPUT: + + 0(%sp): return address + + 4(%sp): env - address of a hal_jmp_buf structure + + 8(%sp): val - the non-zero value to return + +OUTPUT: + + d0, d1, a0, a1 are ours to abuse. + +RETURN VALUE: + + This routine always returns the value from the val parameter in d0.l +and to the location of the PC in the env structure. + +*****************************************************************************/ +FUNC_START(hal_m68k_longjmp) + + move.l 8(%sp),%d0 /* Load the return value */ + /* parameter. */ + + move.l 4(%sp),%a0 /* Get a pointer to the buffer to */ + /* read our state from. */ + + movem.l (%a0),%d2-%d7/%a2-%a6 /* Load our preserved registers, */ + lea (11*4)(%a0),%a0 /* stack pointer and return address */ + move.l (%a0)+,%d1 /* from the structure. */ + move.l (%a0),%a1 + + move.l %d1,%sp /* Set the stack pointer from the */ + jmp (%a1) /* structure as out current stack */ + /* pointer and jump to the return */ + /* address from the structure. */ + + +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/src/hal_misc.c @@ -0,0 +1,195 @@ +//========================================================================== +// +// hal_misc.c +// +// HAL miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/infra/diag.h> // diag_printf + +#include <cyg/hal/hal_arch.h> // HAL header + +#include <cyg/hal/hal_intr.h> // VSR/ISR defines + +//-------------------------------------------------------------------------- +// ISR tables +volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +//-------------------------------------------------------------------------- +// VSR table + +// The cyg_hal_vsr_table table is variant-specific. Some processors must +// have the VSR table at specific locations. + +/***************************************************************************** +hal_default_exception_handler -- First level C exception handler + + The assembly default VSR handler calls this routine to handler the +exception. When this routine returns, the state is restored to the state +pointed to by regs. + + We declare this routine as weak so that other handlers can easily +become the default exception handler. + +INPUT: + + vector: The exception vector number. + + regs: A pointer to the saved state. + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ + +externC void +hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs) + __attribute__ ((weak)); + +void hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs) +{ + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + externC void __handle_exception(void); + externC HAL_SavedRegisters * _hal_registers; + + // Set the pointer to the registers of the current exception + // context. At entry the GDB stub will expand the + // HAL_SavedRegisters structure into a (bigger) register array. + _hal_registers = regs; + + __handle_exception(); + +#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ + defined(CYGPKG_HAL_EXCEPTIONS) + + // We should decode the vector and pass a more appropriate + // value as the second argument. For now we simply pass a + // pointer to the saved registers. We should also divert + // breakpoint and other debug vectors into the debug stubs. + + cyg_hal_deliver_exception(vector, (CYG_ADDRWORD)regs); + +#else + + CYG_FAIL("Exception!!!"); + +#endif + + return; +} + +//--------------------------------------------------------------------------- +// Default ISRs + +externC cyg_uint32 +hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + diag_printf("Spurious Interrupt: %d\n", vector); + +// CYG_FAIL("Spurious Interrupt!!!"); + return 0; +} + +//--------------------------------------------------------------------------- +// Idle thread action + +void +hal_idle_thread_action( cyg_uint32 count ) +{ +} + +//--------------------------------------------------------------------------- +// Determine the index of the ls bit of the supplied mask. + +cyg_uint32 +hal_lsbit_index(cyg_uint32 mask) +{ + cyg_uint32 n = mask; + + static const signed char tab[64] = + { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10, + 4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11, + 5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0, + 0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0 + }; + + n &= ~(n-1UL); + n = (n<<16)-n; + n = (n<<6)+n; + n = (n<<4)+n; + + return tab[n>>26]; +} + +//--------------------------------------------------------------------------- +// Determine the index of the ms bit of the supplied mask. + +cyg_uint32 +hal_msbit_index(cyg_uint32 mask) +{ + cyg_uint32 x = mask; + cyg_uint32 w; + + // Phase 1: make word with all ones from that one to the right. + x |= x >> 16; + x |= x >> 8; + x |= x >> 4; + x |= x >> 2; + x |= x >> 1; + + // Phase 2: calculate number of "1" bits in the word. + w = (x & 0x55555555) + ((x >> 1) & 0x55555555); + w = (w & 0x33333333) + ((w >> 2) & 0x33333333); + w = w + (w >> 4); + w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F); + return (cyg_uint32)((w + (w >> 16)) & 0xFF); + +} + +//--------------------------------------------------------------------------- +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/src/hal_startup.c @@ -0,0 +1,262 @@ +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_startup.h> +#include <cyg/hal/hal_memmap.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_diag.h> // hal_diag_init +#include <cyg/infra/diag.h> // diag_printf +#include <string.h> // memcpy, memset + +externC void cyg_start(void); +externC void hw_vsr_reset(void); + +#define CYG_HAL_RESET_DEBUG_ENABLE +#ifdef CYG_HAL_RESET_DEBUG_ENABLE +#define CYG_HAL_RESET_DEBUG diag_printf +#else +#define CYG_HAL_RESET_DEBUG() +#endif // CYG_HAL_RESET_DEBUG_ENABLE + +/***************************************************************************** +hal_vsr_init -- Initialize the vector table + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +static void hal_vsr_init(void) +{ + + /* Initialize the HAL's vector table with the ROM vector table. */ + + memcpy((void*)cyg_hal_vsr_table, __romvec_start, + (size_t)sizeof(cyg_hal_vsr_table)); + +} + +/***************************************************************************** +hal_vsr_init -- Initialize the ISRs + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +static void hal_isr_init(void) +{ + int_t i; + + // Initialize all ISR entries to default. + + for (i = 0; i < CYGNUM_HAL_ISR_COUNT; i++) + { + cyg_hal_interrupt_handlers[i] = (CYG_ADDRESS) &hal_default_isr; + cyg_hal_interrupt_data[i] = (CYG_ADDRWORD)0; + cyg_hal_interrupt_objects[i] = (CYG_ADDRESS)0; + } +} + +/***************************************************************************** +hal_init_ram_sections -- Initialize the RAM sections + + Initialize all RAM sections that the C code relies on. data, bss, +sbss. + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +static void hal_init_ram_sections(void) +{ + + // Initialize the RAM data section from the ROM image of the data + // section. + + memcpy(__ram_data_start, __rom_data_start, (size_t)__ram_data_size); + + // Initialize the bss and sbss sections to zero. + + memset(__bss_start, 0, (size_t)__bss_size); + memset(__sbss_start, 0, (size_t)__sbss_size); +} + +/***************************************************************************** +cyg_hal_invoke_constructors -- Call static constructors + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +cyg_bool cyg_hal_stop_constructors; +#endif + +typedef void (*pfunc) (void); +extern pfunc __CTOR_LIST__[]; +extern pfunc __CTOR_END__[]; + +static void cyg_hal_invoke_constructors(void) +{ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + static pfunc *p = &__CTOR_END__[-1]; + + cyg_hal_stop_constructors = 0; + for (; p >= __CTOR_LIST__; p--) { + (*p) (); + if (cyg_hal_stop_constructors) { + p--; + break; + } + } +#else + pfunc *p; + + for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) + (*p) (); +#endif +} + +/***************************************************************************** +hal_reset -- Reset vector routine + + This routine must be called with interrupts disabled and will never +return. + + Only the assembly reset vector routine should call this routine. + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void hal_reset(void) CYGBLD_ATTRIB_NORET; +void hal_reset(void) +{ + const char * fname; + + fname = __FUNCTION__; + + // Initialize the RAM sections that the rest of the C code requires. + + hal_init_ram_sections(); + + // It is now safe to call C functions which may rely on initialized + // data. + + // Initialize the ISR and VSR tables. + + hal_isr_init(); + hal_vsr_init(); + + // Do any variant-specific reset initialization. + + var_reset(); + + // Initialize the diagnostics IO. + + HAL_DIAG_INIT(); + CYG_HAL_RESET_DEBUG("%s: RESET\r\n", fname); + + // Call C++ constructors. + + CYG_HAL_RESET_DEBUG("%s: calling cyg_hal_invoke_constructors\r\n", fname); + cyg_hal_invoke_constructors(); + + // It should be safe to enable interrupts now. + + CYG_HAL_RESET_DEBUG("%s: lowering interrupt mask\r\n", fname); + HAL_ENABLE_INTERRUPTS(); + + // Call cyg_start. This routine should not return. + + CYG_HAL_RESET_DEBUG("%s: calling cyg_start\r\n", fname); + cyg_start(); + + // If we return, loop and print out a message. + + HAL_DIAG_INIT(); + for (;;) + { + CYG_HAL_RESET_DEBUG("%s: cyg_start returned!\r\n", fname); + } +} + +/***************************************************************************** +hal_hw_reset -- Simulate a hardware reset + + This routine will never return. + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void hal_hw_reset(void) +{ + + // Give control to the reset vector handler. + + hw_vsr_reset(); +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/src/m68k.ld @@ -0,0 +1,200 @@ +/*========================================================================== +// +// m68k.ld +// +// Linker script +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +*/ + +STARTUP(vectors.o) +ENTRY(__exception_reset) +#ifdef EXTRAS +INPUT(extras.o) +#endif +GROUP(libtarget.a libgcc.a) + +#define ALIGN_LMA 4 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#ifndef CYG_LABEL_DEFN +# define CYG_LABEL_DEFN(_label) _label +#endif + +#define SECTIONS_BEGIN + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { _stext = .; \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \ + > _region_ \ + _etext = .; PROVIDE (etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fini) } \ + > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata1) } \ + > _region_ + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata*) } \ + > _region_ + +#define SECTION_fixup(_region_, _vma_, _lma_) \ + .fixup _vma_ : _lma_ \ + { __FIXUP_START__ = ABSOLUTE(.); *(.fixup) __FIXUP_END__ = ABSOLUTE(.);}\ + > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { __EXCEPT_START__ = ABSOLUTE(.); *(.gcc_except_table) \ + __EXCEPT_END__ = ABSOLUTE(.);} \ + > _region_ + +#define SECTION_data(_region_, _vma_, _lma_, _rom_data_addr_) \ + .data _vma_ : _lma_ \ + { \ + __ram_data_start = ABSOLUTE(.); \ + *(.data*) \ + __GOT1_START__ = ABSOLUTE(.); *(.got1) __GOT1_END__ = ABSOLUTE(.); \ + . = ALIGN (4); \ + KEEP(*( SORT (.ecos.table.*))); \ + . = ALIGN (4); \ + __CTOR_LIST__ = ABSOLUTE(.); \ + KEEP(*(SORT(.ctors*))); \ + __CTOR_END__ = ABSOLUTE(.); \ + __DTOR_LIST__ = ABSOLUTE(.); \ + KEEP(*(SORT(.dtors*))) \ + __DTOR_END__ = ABSOLUTE(.); \ + . = ALIGN(8); \ + __GOT2_START__ = ABSOLUTE(.); *(.got2) __GOT2_END__ = ABSOLUTE(.); \ + __GOT_START = ABSOLUTE(.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE(. + 32768); \ + _SDA_BASE_ = ABSOLUTE(.); *(.got.plt) *(.got) \ + __GOT_END__ = ABSOLUTE(.); *(.dynamic) \ + /* We want the small data sections together, so single-instruction */ \ + /* offsets can access them all, and initialized data all before */ \ + /* uninitialized, so we can shorten the on-disk segment size. */ \ + __SDATA_START__ = ABSOLUTE(.); *(.sdata) \ + __ram_data_end = ABSOLUTE(.); \ + __ram_data_size = ABSOLUTE (.) - ABSOLUTE(__ram_data_start); \ + } \ + > _region_ \ + __rom_data_start = ABSOLUTE(_rom_data_addr_); \ + __rom_data_size = SIZEOF(.data); \ + __rom_data_end = __rom_data_start + __rom_data_size; + +#define SECTION_sbss(_region_, _vma_, _lma_) \ + .sbss _vma_ : _lma_ \ + { __sbss_start = ABSOLUTE (.); \ + __SBSS_START__ = ABSOLUTE(.); *(.sbss) __SBSS_END__ = ABSOLUTE(.); \ + *(.scommon) \ + __sbss_end = ABSOLUTE (.); \ + __sbss_size = ABSOLUTE (.) - ABSOLUTE(__sbss_start); \ + } \ + > _region_ + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { __bss_start = ABSOLUTE (.); \ + FORCE_OUTPUT; *(.dynbss) *(.bss) *(COMMON) \ + __bss_end = ABSOLUTE (.); \ + __bss_size = ABSOLUTE (.) - ABSOLUTE(__bss_start); \ + } \ + > _region_ + +#define SECTION_stab \ + .stab 0 (NOLOAD) : \ + { \ + *(.stab) \ + } + +#define SECTION_stabstr \ + .stabstr 0 (NOLOAD) : \ + { \ + *(.stabstr) \ + } + +#define SECTION_comment \ + .comment 0 (NOLOAD) : \ + { \ + *(.comment) \ + } + +#define SECTION_heap1(_region_, _vma_, _lma_, _minsize_) \ + .heap1 _vma_ : _lma_ \ + { __heap1_start = ABSOLUTE (.); \ + . += (_minsize_); \ + __heap1_end = ABSOLUTE (.); \ + __heap1_size = ABSOLUTE (.) - ABSOLUTE(__heap1_start); \ + } \ + > _region_ + +#define SECTION_uninvar(_region_, _vma_, _lma_) \ + .uninvar _vma_ : _lma_ \ + { __uninvar_start = ABSOLUTE (.); \ + FORCE_OUTPUT; *(.uninvar) \ + __uninvar_end = ABSOLUTE (.); \ + __uninvar_size = ABSOLUTE (.) - ABSOLUTE(__uninvar_start); \ + } \ + > _region_ + +#define GENERIC_SECTION(_name_, _region_, _vma_, _lma_, _minsize_) \ + . ## _name_ _vma_ : _lma_ \ + { __ ## _name_ ## _start = ABSOLUTE (.); \ + FORCE_OUTPUT; *(. ## _name_ ## ) \ + __ ## _name_ ## _datasize = (ABSOLUTE (.) - ABSOLUTE(__ ## _name_ ## _start)); \ + . += (_minsize_) > (__ ## _name_ ## _datasize) ? (_minsize_) - (__ ## _name_ ## _datasize) : 0; \ + __ ## _name_ ## _end = ABSOLUTE (.); \ + __ ## _name_ ## _size = (ABSOLUTE (.) - ABSOLUTE(__ ## _name_ ## _start)); \ + } \ + > _region_ + +#define SECTIONS_END \ + SECTION_stab \ + SECTION_stabstr \ + SECTION_comment \ + . = ALIGN(4); _end = .; PROVIDE (end = .); + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_LDI +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/arch/current/src/m68k_stub.c @@ -0,0 +1,191 @@ +//======================================================================== +// +// m68k_stub.c +// +// Helper functions for stub +// +//======================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//======================================================================== + +#include <stddef.h> + +#include <pkgconf/hal.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +#include <cyg/hal/hal_stub.h> + +#include <cyg/hal/hal_stub.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT +#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id +#endif + +/* Given a trap value TRAP, return the corresponding signal. */ + +int __computeSignal (unsigned int trap_number) +{ + switch (trap_number) + { + + case CYGNUM_HAL_VECTOR_BUSERR: + case CYGNUM_HAL_VECTOR_ADDERR: + return SIGBUS; + + case CYGNUM_HAL_VECTOR_ILLINST: + return SIGILL; + + case CYGNUM_HAL_VECTOR_ZERODIV: + /* This isn't quite accurate: this is integer division only. */ + return SIGFPE; + + case CYGNUM_HAL_VECTOR_CHKINST: + case CYGNUM_HAL_VECTOR_TRAPVINST: + return SIGTRAP; + + case CYGNUM_HAL_VECTOR_PRIVVIOLATION: + return SIGILL; + case CYGNUM_HAL_VECTOR_TRACE: + /* Instruction trace */ + return SIGTRAP; + + case CYGNUM_HAL_VECTOR_L1010: + case CYGNUM_HAL_VECTOR_L1111: + case CYGNUM_HAL_VECTOR_UNINITINT: + case CYGNUM_HAL_VECTOR_SPURINT: + return SIGTRAP; + + case CYGNUM_HAL_VECTOR_TRAPFIRST ... CYGNUM_HAL_VECTOR_TRAPLAST: + return SIGTRAP; + + case CYGNUM_HAL_VECTOR_AUTOVEC1 ... CYGNUM_HAL_VECTOR_AUTOVEC7: + case CYGNUM_HAL_VECTOR_INTRFIRST ... CYGNUM_HAL_VECTOR_INTRLAST: + /* External interrupt */ + return SIGINT; + + default: + return SIGTERM; + } +} + + +/* Return the trap number corresponding to the last-taken trap. */ + +int __get_trap_number (void) +{ + //extern int hal_m68k_trap_number; + + // The vector is not not part of the GDB register set so get it + // directly from the save context. + //return hal_m68k_trap_number; + + return 1; +} + +/* Set the currently-saved pc register value to PC. This also updates NPC + as needed. */ + +void set_pc (target_register_t pc) +{ + put_register (PC, pc); +} + + +/*---------------------------------------------------------------------- + * Single-step support + */ + +/* Set things up so that the next user resume will execute one instruction. + This may be done by setting breakpoints or setting a single step flag + in the saved user registers, for example. */ + +#define SR_TRACE 0x8000 + +void __single_step (void) +{ + target_register_t sr = get_register (PS); + + // Set trace flag in the exception context. + sr |= SR_TRACE; + + put_register (PS, sr); +} + +/* Clear the single-step state. */ + +void __clear_single_step (void) +{ + target_register_t sr = get_register (PS); + + // Clear single-step flag in the exception context. + sr &= ~SR_TRACE; + + put_register (PS, sr); +} + + +void __install_breakpoints (void) +{ + /* NOP since single-step HW exceptions are used instead of + breakpoints. */ +} + +void __clear_breakpoints (void) +{ +} + + +/* If the breakpoint we hit is in the breakpoint() instruction, return a + non-zero value. */ + +int +__is_breakpoint_function () +{ + return get_register (PC) == (target_register_t)&CYG_LABEL_NAME(breakinst); +} + + +/* Skip the current instruction. Since this is only called by the + stub when the PC points to a breakpoint or trap instruction, + we can safely just skip 4. */ + +void __skipinst (void) +{ + put_register (PC, get_register (PC) + 4); +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/cdl/hal_m68k_mcf52xx_mcf5272_mcf5272c3.cdl @@ -0,0 +1,270 @@ +# ==================================================================== +# +# hal_m68k_mcf52xx_mcf5272_mcf5272c3.cdl +# +# Motorola mcf5272c3 evaluation board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_HAL_M68K_MCF52xx_MCF5272_MCF5272C3 { + display "Motorola mcf5272c3 evaluation board" + parent CYGPKG_HAL_M68K_MCF52xx_MCF5272 + define_header hal_m68k_mcf52xx_mcf5272_mcf5272c3.h + include_dir cyg/hal + + description "The Motorola mcf5272c3 evaluation board platform HAL + package should be used when targeting the actual hardware for + the Motorola mcf5272c3 evaluation board platform." + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_m68k_mcf52xx_mcf5272.h>" + } + + compile plf_startup.c hal_diag.c + +# implements CYGINT_HAL_DEBUG_GDB_STUBS +# implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_m68k.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_m68k_mcf52xx_mcf5272.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_m68k_mcf52xx_mcf5272_mcf5272c3.h>" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + + description "When targeting the Motorola mcf5272c3 evaluation board + it is expected that the image will be downloaded into RAM + via the Motorola dBUG monitor." + + } + + cdl_option CYGHWR_HAL_SYSTEM_CLOCK_MHZ { + display "System clock speed in MHz" + flavor data + legal_values 66 + default_value 66 + + description "This option identifies the system clock that the + processor uses. This value is used to set clock dividers + for some devices." + + } + + cdl_option CYGHWR_HAL_M68K_MCF52xx_MCF5272_MCF5272C3_DIAG_BAUD { + display "Diagnostic Serial Port Baud Rate" + flavor data + legal_values 9600 19200 38400 115200 + default_value 9600 + + description "This option selects the baud rate used for the + diagnostic port. Note: this should match the value chosen + for the GDB port if the diagnostic and GDB port are the + same." + + } + + cdl_option CYGHWR_HAL_M68K_MCF52xx_MCF5272_MCF5272C3_GDB_BAUD { + display "GDB Serial Port Baud Rate" + flavor data + legal_values 9600 19200 38400 115200 + default_value 9600 + + description "This option controls the baud rate used for the GDB + connection." + + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + flavor none + + description "Set the periodic timer on the mcf5272 to 1 ms or + 1000000 ns." + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + calculated 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + calculated 1000 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + calculated 1000000 + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + + description "Global build options including control over compiler + flags, linker flags and choice of toolchain." + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "m68k-elf" } + + description "This option specifies the command prefix used + when invoking the build tools." + + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-m5200 -malign-int -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-thunks=3 -finit-priority -fomit-frame-pointer" } + description "This option controls the global compiler flags + which are used to compile all packages by default. + Individual packages may define options which + override these global flags." + + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-m5200 -g -nostdlib -Wl,--gc-sections -Wl,-static" } + + description "This option controls the global linker flags. + Individual packages may define options which + override these global flags." + + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + + description "This option enables the building of the GDB + stubs for the board. The common HAL controls + takes care of most of the build process, but the + final conversion from ELF image to binary data is + handled by the platform CDL, allowing relocation + of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "m68k_mcf52xx_mcf5272_mcf5272c3_ram" : \ + "m68k_mcf52xx_mcf5272_mcf5272c3_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.ldi>" : \ + "<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.h>" : \ + "<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + requires { CYG_HAL_STARTUP == "RAM" } + parent CYGPKG_HAL_ROM_MONITOR + + description "Support can be enabled for boot ROMs or ROM + monitors which contain GDB stubs. This support + changes various eCos semantics such as the encoding of + diagnostic output, and the overriding of hardware + interrupt vectors." + + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + + description "Enable this option if this program is to be used as + a ROM monitor, i.e. applications will be loaded into + RAM on the board, and this ROM monitor may process + exceptions or interrupts generated from the + application. This enables features such as utilizing + a separate interrupt stack when exceptions are + generated." + + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/include/hal_memmap.h @@ -0,0 +1,66 @@ +#ifndef HAL_MEMMAP_H +#define HAL_MEMMAP_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> + +// WARNING: DO NOT CHANGE THE TYPES OF THESE LABELS. THE LINKER DEFINES +// THESE AND WE WANT TO USE THE VARIABLES NOT THE VARIABLES THEMSELVES. + +#define SECTION_DEC(_name_) \ + externC unsigned char __ ## _name_ ## _start[]; \ + externC unsigned char __ ## _name_ ## _end[]; \ + externC unsigned char __ ## _name_ ## _size[]; + +SECTION_DEC(rom) +SECTION_DEC(ram) +SECTION_DEC(bss) +SECTION_DEC(sbss) +SECTION_DEC(ram_data) +SECTION_DEC(rom_data) +SECTION_DEC(heap1) +SECTION_DEC(uninvar) +SECTION_DEC(romvec) +SECTION_DEC(ramvec) + +/***************************************************************************** +On-chip registers, System Integration Module (SIM) +*****************************************************************************/ + +#define MCF5272_MBAR (0x10000000) + +#endif /* HAL_MEMMAP_H */ +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/include/pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.h @@ -0,0 +1,50 @@ +#ifndef _MLT_M68K_RAM_H +#define _MLT_M68K_RAM_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +// eCos memory layout + +#ifndef __ASSEMBLER__ + +#include <cyg/hal/hal_memmap.h> + +#endif + +#define CYGMEM_SECTION_heap1 (__heap1_start) +#define CYGMEM_SECTION_heap1_SIZE ((size_t)(__heap1_size)) + +#endif // _MLT_M68K_RAM_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/include/pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.ldi @@ -0,0 +1,80 @@ +//=========================================================================== +// +// RAM startup linker control script +// +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + rom (rx) : ORIGIN = 0x00020000, LENGTH = 0x001E0000 + ram (wx) : ORIGIN = 0x00200000, LENGTH = 0x00200000 +} + +SECTIONS +{ + SECTIONS_BEGIN + + GENERIC_SECTION (rom, rom, 0x00020000 (NOLOAD), LMA_EQ_VMA, 0x001E0000) + GENERIC_SECTION (ram, ram, 0x00200000 (NOLOAD), LMA_EQ_VMA, 0x00200000) + + GENERIC_SECTION (romvec, rom, __rom_start, LMA_EQ_VMA, 0x400) + SECTION_text (rom, ALIGN (0x4), FOLLOWING (.romvec)) + SECTION_fini (rom, ALIGN (0x4), FOLLOWING (.text)) + SECTION_rodata1 (rom, ALIGN (0x4), FOLLOWING (.fini)) + SECTION_rodata (rom, ALIGN (0x4), FOLLOWING (.rodata1)) + SECTION_fixup (rom, ALIGN (0x4), FOLLOWING (.rodata)) + + // WARNING: If you change the order of these sections, be sure to change + // the location of the data section. + + SECTION_gcc_except_table (rom, ALIGN (0x4), FOLLOWING (.fixup)) + __rom_data_addr = ABSOLUTE(.); + + GENERIC_SECTION (ramvec, ram, __ram_start (NOLOAD), LMA_EQ_VMA, 0x400) + SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table), __rom_data_addr) + SECTION_sbss (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + SECTION_uninvar (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA) + + // Allocate a heap section. + + SECTION_heap1 (ram, ALIGN (0x4), LMA_EQ_VMA, 0x20000) + // The build tool looks for this "CYG_LABEL_DEFN..." string. + CYG_LABEL_DEFN(__heap1) = ABSOLUTE (__heap1_start); + + SECTIONS_END +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/include/plf_intr.h @@ -0,0 +1,109 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// Platform specific interrupt and clock support +// +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +/* The vector used by the Real time clock */ + +#define CYGNUM_HAL_INTERRUPT_RTC (CYGNUM_HAL_VECTOR_TMR4) + +//--------------------------------------------------------------------------- +// Clock control + +/* The mcf5272 has 4 timers 0-3. Define the timer number that we want */ +/* to use for the OS's clock. */ + +#define CYGNUM_HAL_RTC_TIMER_NUM (3) + +/* Set the timer to generate 1 ms or 1000000 ns period interrupts. */ + +#define HAL_M68K_MCF52xx_MCF5272_CLOCK_NS 1000000 +#if CYGNUM_HAL_RTC_PERIOD != HAL_M68K_MCF52xx_MCF5272_CLOCK_NS +#warning Unexpected clock period for this board!!! +#endif + +/* Initialize the timer to generate an interrupt every 1 ms. Use the */ +/* system clock divided by 16 as the source. Using 11*3 as the prescaler */ +/* gives a 8 us counter. When this counter reaches 125 (1 ms) generate an */ +/* interrupt. */ + +#define HAL_CLOCK_INITIALIZE(_period_) \ +CYG_MACRO_START \ +MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr = 0x0000; \ +MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].trr = 125-1; \ +MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn = 0; \ +MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter = 0x0003; \ +MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr = \ + (((3*11)-1) << MCF5272_TIMER_TMR_PS_BIT) | \ + (0 << MCF5272_TIMER_TMR_CE_BIT) | \ + (0 << MCF5272_TIMER_TMR_OM_BIT) | \ + (1 << MCF5272_TIMER_TMR_ORI_BIT) | \ + (1 << MCF5272_TIMER_TMR_FRR_BIT) | \ + (2 << MCF5272_TIMER_TMR_CLK_BIT) | \ + (1 << MCF5272_TIMER_TMR_RST_BIT); \ +CYG_MACRO_END + +/* We must clear the bit in the timer event register before we can get */ +/* another interrupt. */ + +#define HAL_CLOCK_RESET( _vector_, _period_ ) \ +CYG_MACRO_START \ +MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter = 0x0002; \ +CYG_MACRO_END + +/* Read the current counter from the timer. */ + +#define HAL_CLOCK_READ( _pvalue_ ) \ +CYG_MACRO_START \ +*(_pvalue_) = MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn; \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/include/plf_startup.h @@ -0,0 +1,55 @@ +#ifndef _PLF_STARTUP_H +#define _PLF_STARTUP_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> + +// The following label specifies whether the HAL should enable or disable +// the data transfer acknowledge output pin on the mcf5272 device. + +#define HAL_MCF5272_ENABLE_DATA_TA (false) + +// Platform-specific reset vector initialization routine + +externC void plf_reset(void); + +// Initialize the cache and access control registers for the current +// platform. + +void plf_init_cache_acr(void); + +#endif // _PLF_STARTUP_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/src/hal_diag.c @@ -0,0 +1,149 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_diag.h> // our header. + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // hal_output_gdb_string +#endif + +#include <cyg/infra/cyg_type.h> // base types, externC +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_intr.h> // Interrupt macros + +#include <cyg/hal/hal_arch.h> + +#define CYG_KERNEL_DIAG_SERIAL + +//----------------------------------------------------------------------------- +// Serial diag functions. +#ifdef CYG_KERNEL_DIAG_SERIAL + +// Include the serial driver. + +void hal_diag_init(void) +{ + CYG_WORD16 clk_div; + + /* We must first enable the UART output pins from the general-purpose */ + /* I/O module. */ + + /* Enable the UART0 pins in the port B control register. */ + + MCF5272_SIM->gpio.pbcnt = ((MCF5272_SIM->gpio.pbcnt & + ~(MCF5272_GPIO_PBCNT_URT0_MSK)) | + (MCF5272_GPIO_PBCNT_URT0_EN)); + + /* Before we do anything else, make sure we have enabled CTS (our */ + /* RTS) in case the device we are using relies on hardware flow */ + /* control. Note that this step is our only attempt at hardware flow */ + /* control. */ + + MCF5272_SIM->uart[0].uop1 = 1; + + /* Initialize UART0 */ + + /* Reset Transmitter */ + MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RTX; + + /* Reset Receiver */ + MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RRX; + + /* Reset Mode Register */ + MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RMR; + + MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RES; + MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RBC; + + /* Mode register 1 sets the UART to 8 data bits with no parity, and */ + /* mode register 2 forces 1 stop bit. Reading or write to the mode */ + /* register switches it from umr1 to umr2. To set it to umr1, we must */ + /* write a reset mode register command to the command register. */ + + MCF5272_SIM->uart[0].umr = MCF5272_UART_UMR_8BNP; + MCF5272_SIM->uart[0].umr = MCF5272_UART_UMR_1S; + + /* Select a prescaled (by 1/32) CLKIN for the clock source. */ + + MCF5272_SIM->uart[0].usr_ucsr = MCF5272_UART_UCSR_CLKIN; + + /* Calculate baud settings */ + clk_div = (CYG_WORD16) + ((CYGHWR_HAL_SYSTEM_CLOCK_MHZ*1000000)/ + (CYGHWR_HAL_M68K_MCF52xx_MCF5272_MCF5272C3_DIAG_BAUD * 32)); + MCF5272_SIM->uart[0].udu = clk_div >> 8; + MCF5272_SIM->uart[0].udl = clk_div & 0x00ff; + + /* Enable the transmitter and receiver. */ + MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_TXRXEN; + +} + +void hal_diag_write_char(cyg_int8 ch) +{ + + /* Loop until the transmit data holding register is empty. */ + while (!(MCF5272_SIM->uart[0].usr_ucsr & MCF5272_UART_USR_TXRDY)); + + /* Write the character to the transmit status register. */ + MCF5272_SIM->uart[0].urb_utb = ch; + + /* Loop until the transmit data FIFO and the shift register are */ + /* empty. */ + + while ((MCF5272_SIM->uart[0].utf & MCF5272_UART_UTF_TXB) || + (!(MCF5272_SIM->uart[0].usr_ucsr & MCF5272_UART_USR_TXEMP))); + +} + +cyg_int8 hal_diag_read_char(void) +{ + + return 0; +} + +#endif // ifdef CYG_KERNEL_DIAG_SERIAL + +//----------------------------------------------------------------------------- +// End of hal_diag.c +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/mcf5272c3/plf/current/src/plf_startup.c @@ -0,0 +1,95 @@ +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> +#include <pkgconf/hal.h> +#include <cyg/hal/hal_startup.h> +#include <cyg/hal/hal_memmap.h> +#include <cyg/hal/hal_arch.h> + +/***************************************************************************** +plf_init_cache_acr -- Initialize the cache and access control registers + + The var_init_cache_acr routine already invalidated the cache and ACRs. +This routine only needs to enable the ACRs that it will use. + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void plf_init_cache_acr(void) +{ + + // Enable the instruction cache with the following options: + // Enable CPUSHL invalidation. + // No freeze. + // Invalidate all cache lines (flush). + // No external arbiter control. + // Disable non-cacheable instruction bursting. + // Default memory is cacheable. + // Enable buffered writes. + // Read and write access permitted by default. + // Instruction fetch size is cache line. + + mcf52xx_wr_cacr((CYG_WORD32)0x81000102); + + // Leave the access control registers disabled by default. + +} + +/***************************************************************************** +plf_reset -- Platform-specific reset vector initialization routine + + This routine must be called with interrupts disabled. + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void plf_reset(void) +{ + +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/cdl/hal_m68k_mcf52xx_mcf5272.cdl @@ -0,0 +1,62 @@ +# ==================================================================== +# +# hal_m68k_m68000.cdl +# +# M68K/M68000 variant architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_HAL_M68K_MCF52xx_MCF5272 { + display "mcf5272 68k/Coldfire variant HAL" + parent CYGPKG_HAL_M68K_MCF52xx + requires CYGPKG_HAL_M68K_MCF52xx + implements CYGINT_HAL_M68K_VARIANT + hardware + include_dir cyg/hal + define_header hal_m68k_mcf52xx_mcf5272.h + + description "The mcf5272 68k/Coldfire variant HAL package provides + generic support for this processor architecture. It is also + necessary to select a specific target platform HAL package." + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_m68k_mcf52xx.h>" + } + + compile proc_startup.c proc_arch.S proc_misc.c memcpy.c + +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/mcf5272_sim.h @@ -0,0 +1,568 @@ +#ifndef MCF5272_SIM_H +#define MCF5272_SIM_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +/* + + Defines for the mcf5272 System Integration Module (SIM) + +*/ + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +/* General configuration registers. */ +typedef struct mcf5272_sim_cfg_t +{ + + u32_t mbar; /* Module base address register */ + /* (MBAR), after initialization */ + + u16_t scr; /* System configuration register */ + + u16_t spr; /* System protection register */ + + u32_t pmr; /* Power management register */ + + u16_t res1; + + u16_t alpr; /* Active low power register */ + + u32_t dir; /* Device identification register */ + + u32_t res2[3]; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t; + +/* Interrupt controller registers. */ +typedef struct mcf5272_sim_int_t +{ + + u32_t icr[4]; /* Interrupt control register 1-4 */ + + u32_t isr; /* Interrupt source register */ + + u32_t pitr; /* Programmable interrupt */ + /* transition register */ + + u32_t piwr; /* Programmable interrupt wakeup */ + /* register */ + + u8_t res1[3]; + + u8_t ipvr; /* Programmable interrupt vector */ + /* register */ + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t; + +/* Chip Select Module */ +typedef struct mcf5272_sim_cs_t +{ + + u32_t csbr; /* CS base register. */ + + u32_t csor; /* CS option register. */ + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t; + +/* General Purpose I/O Module */ +typedef struct mcf5272_sim_gpio_t +{ + + /* Use the following labels to initialize the bits in the data */ + /* direction registers. Setting the bit to zero indicates that this */ + /* pin is an input, one indicates an input. */ + +#define MCF5272_GPIO_DDR_IN (0) +#define MCF5272_GPIO_DDR_OUT (1) + + u32_t pacnt; /* Port A control register. */ + + u16_t paddr; /* Port A data direction */ + /* register. */ + + u16_t padat; /* Port A data register. */ + + u32_t pbcnt; /* Port B control register. */ + + /* Set these bits in the port B control register to enable the */ + /* Ethernet, UART0, and data transfer acknowledge pins. */ + +#define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000) +#define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000) +#define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000) + +#define MCF5272_GPIO_PBCNT_TA_EN (0x00000400) +#define MCF5272_GPIO_PBCNT_TA_DE (0x00000000) +#define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00) + +#define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155) +#define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000) +#define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF) + + u16_t pbddr; /* Port B data direction */ + /* register. */ + + u16_t pbdat; /* Port B data register. */ + + u32_t res1; + + u16_t pcddr; /* Port C data direction */ + /* register. */ + + u16_t pcdat; /* Port C data register. */ + + u32_t pdcnt; /* Port D control register. */ + + /* Set these bits in the port D control register to enable the UART1 */ + /* and interrupt 4 pins. */ + +#define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00) +#define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000) +#define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00) + +#define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA) +#define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000) +#define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF) + + u16_t res2; + u16_t res3; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t; + +/* UART Module */ +typedef struct mcf5272_sim_uart_t +{ + + u8_t umr; /* UART mode register. */ + u8_t res1[3]; + +#define MCF5272_UART_UMR_8BNP (0x13) /* Write this value to umr1 to */ + /* program the device for 8 bits */ + /* and no parity. */ + +#define MCF5272_UART_UMR_1S (0x07) /* Write this value to umr2 to */ + /* program the device for 1 stop */ + /* bit. */ + + u8_t usr_ucsr; /* UART status register (R) and */ + u8_t res2[3]; /* UART clock-select register (W). */ + +#define MCF5272_UART_USR_RRDY (1<<0) /* Bit 0 of the device status */ + /* register is set when the receive */ + /* data register contains data. If */ + /* the data is not removed from the */ + /* holding register, additional */ + /* data will be placed in the FIFO */ + /* until the FIFO is overrun. */ + +#define MCF5272_UART_USR_FFUL (1<<1) /* Bit 1 of the device status */ + /* register is set when the receive */ + /* data FIFO is full. If a */ + /* character is not removed before */ + /* the next character is received, */ + /* overrun will occur. */ + +#define MCF5272_UART_USR_TXRDY (1<<2) /* Bit 2 of the device status */ + /* register is set when the */ + /* transmit data holding register */ + /* is empty. Note that this is */ + /* different than the FIFO being */ + /* empty as the FIFO may still */ + /* contain characters even if the */ + /* holding register is empty. */ + +#define MCF5272_UART_USR_TXEMP (1<<3) /* Bit 3 of the device status */ + /* register is set when the */ + /* transmit data FIFO is empty. */ + +#define MCF5272_UART_USR_OE (1<<4) /* Bit 4 of the device status */ + /* register is set when an overrun */ + /* error has occurred. */ + +#define MCF5272_UART_USR_PE (1<<5) /* Bit 5 of the device status */ + /* register is set when a parity */ + /* error has occurred. */ + +#define MCF5272_UART_USR_FE (1<<6) /* Bit 6 of the device status */ + /* register is set when a framing */ + /* error has occurred. */ + +#define MCF5272_UART_USR_RB (1<<7) /* Bit 7 of the device status */ + /* register is set when a change in */ + /* break status has occurred on the */ + /* port. */ + +#define MCF5272_UART_UCSR_CLKIN (0xDD) /* Writing this value to the ucsr */ + /* selects CLKIN/16 as the UART's */ + /* clock source. */ + + u8_t ucr; /* UART command register (W). */ + u8_t res3[3]; + +#define MCF5272_UART_UCR_RMR (0x01<<4) /* Write this value to ucr to */ + /* reset the mode register to umr1. */ + +#define MCF5272_UART_UCR_RRX (0x02<<4) /* Write this value to ucr to */ + /* reset the receiver. */ + +#define MCF5272_UART_UCR_RTX (0x03<<4) /* Write this value to ucr to */ + /* reset the transmitter. */ + +#define MCF5272_UART_UCR_RES (0x04<<4) /* Write this value to ucr to */ + /* reset the error status. */ + +#define MCF5272_UART_UCR_RBC (0x05<<4) /* Write this value to ucr to */ + /* reset the break change */ + /* interrupt. */ + +#define MCF5272_UART_UCR_TXEN (1<<2) /* Write this value to ucr to */ + /* enable the transmitter. */ + +#define MCF5272_UART_UCR_TXDE (1<<3) /* Write this value to ucr to */ + /* disable the transmitter. */ + +#define MCF5272_UART_UCR_RXEN (1<<0) /* Write this value to ucr to */ + /* enable the receiver. */ + +#define MCF5272_UART_UCR_RXDE (1<<1) /* Write this value to ucr to */ + /* disable the receiver. */ + + /* Write this value to the ucr to */ + /* enablt the transmitter and */ + /* receiver. */ + +#define MCF5272_UART_UCR_TXRXEN \ + (MCF5272_UART_UCR_TXEN | \ + MCF5272_UART_UCR_RXEN) + + u8_t urb_utb; /* UART receiver buffers (R) and */ + u8_t res4[3]; /* UART transmitter buffers (W). */ + + u8_t uipcr_uacr; /* UART input port change */ + u8_t res5[3]; /* register (R) and UART auxiliary */ + /* control register (W). */ + + u8_t uisr_uimr; /* UART interrupt status register */ + u8_t res6[3]; /* (R) and UART interrupt mask */ + /* register (W). */ + + u8_t udu; /* UART divider upper register */ + u8_t res7[3]; /* (W). */ + + u8_t udl; /* UART divider lower register */ + u8_t res8[3]; /* (W). */ + + u8_t uabu; /* UART autobaud register MSB */ + u8_t res9[3]; /* (R). */ + + u8_t uabl; /* UART autobaud register LSB */ + u8_t res10[3]; /* (R). */ + + u8_t utf; /* UART transmitter FIFO */ + u8_t res11[3]; /* register. */ + +#define MCF5272_UART_UTF_TXB (0x1F) /* Transmitter buffer data level. */ + /* Indicates the number of bytes */ + /* (0-24) currently stored in the */ + /* transmitter FIFO. */ + + u8_t urf; /* UART receiver FIFO register. */ + u8_t res12[3]; + + u8_t ufpd; /* UART Fractional Precision */ + u8_t res13[3]; /* Divider Control register. */ + + u8_t uip; /* UART input port register (CTS) */ + u8_t res14[3]; /* (R). */ + + u8_t uop1; /* UART output port bit set */ + u8_t res15[3]; /* command register (RTS) (W). */ + + u8_t uop0; /* UART output port bit reset */ + u8_t res16[3]; /* command register (RTS) (W). */ + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_uart_t; + +/* Timer Module */ +typedef struct mcf5272_sim_timer_t +{ + + u16_t tmr; /* Timer Mode Register */ + u16_t res1; + +#define MCF5272_TIMER_TMR_PS 0xFF00 /* Prescaler. Programmed to */ +#define MCF5272_TIMER_TMR_PS_BIT 8 /* divide the clock input by values */ + /* from 1 to 256. The value */ + /* 0000_0000 divides the clock by */ + /* 1; the value 1111_1111 divides */ + /* the clock by 256. */ + +#define MCF5272_TIMER_TMR_CE 0x00C0 /* Capture edge and enable */ +#define MCF5272_TIMER_TMR_CE_BIT 6 /* interrupt. 00 Disable capture */ + /* and interrupt on capture event */ + /* 01 Capture on rising edge only */ + /* and generate interrupt on */ + /* capture event 10 Capture on */ + /* falling edge only and generate */ + /* interrupt on capture event 11 */ + /* Capture on any edge and generate */ + /* interrupt on capture event. */ + +#define MCF5272_TIMER_TMR_OM 0x0020 /* Output mode (TMR0 and TMR1 */ +#define MCF5272_TIMER_TMR_OM_BIT 5 /* only. Reserved in TMR2 and */ + /* TMR3). 0 Active-low pulse for */ + /* one system clock cycle (15 nS at */ + /* 66 MHz). 1 Toggle output; TOUTn */ + /* is high at reset but is */ + /* unavailable externally until the */ + /* appropriate port control */ + /* register is configured for this */ + /* function. */ + +#define MCF5272_TIMER_TMR_ORI 0x0010 /* Output reference interrupt */ +#define MCF5272_TIMER_TMR_ORI_BIT 4 /* enable. 0 Disable interrupt for */ + /* reference reached (does not */ + /* affect interrupt on capture */ + /* function). 1 Enable interrupt */ + /* upon reaching the reference */ + /* value. If ORI is 1 when the */ + /* TER[REF] is set, an immediate */ + /* interrupt occurs. */ + +#define MCF5272_TIMER_TMR_FRR 0x0008 /* Free run/restart. 0 Free run. */ +#define MCF5272_TIMER_TMR_FRR_BIT 3 /* Timer count continues to */ + /* increment after the reference */ + /* value is reached. 1 Restart. */ + /* Timer count is reset immediately */ + /* after the reference value is */ + /* reached. */ + +#define MCF5272_TIMER_TMR_CLK 0x0006 /* Input clock source for the */ +#define MCF5272_TIMER_TMR_CLK_BIT 1 /* timer. 00 Stop count. 01 */ + /* Master system clock. 10 Master */ + /* system clock divided by 16. */ + /* TIN0 and TIN1 are external to */ + /* the MCF5272 and are not */ + /* synchronized to the system */ + /* clock, so successive timeout */ + /* lengths may vary slightly. 11 */ + /* Corresponding TIN pin, TIN0 or */ + /* TIN1 (falling edge), unused in */ + /* TMR2 and TMR3. The minimum high */ + /* and low periods for TIN as the */ + /* clock source is 1 system clock, */ + /* which gives a maximum TIN */ + /* frequency of clock/2. */ + +#define MCF5272_TIMER_TMR_RST 0x0001 /* Reset timer. 0 A transition */ +#define MCF5272_TIMER_TMR_RST_BIT 0 /* from 1 to 0 resets the timer. */ + /* Other register values can be */ + /* written. The */ + /* counter/timer/prescaler are not */ + /* clocked unless the timer is */ + /* enabled. 1 Enable timer. */ + + u16_t trr; /* Timer Reference Register */ + u16_t res2; + + u16_t tcap; /* Timer Capture Register */ + u16_t res3; + + u16_t tcn; /* Timer Counter */ + u16_t res4; + + u16_t ter; /* Timer Event Register */ + u16_t res5; + +#define MCF5272_TIMER_TER_REF (0x0002) /* Output reference event. If */ +#define MCF5272_TIMER_TER_REF_BIT (1) /* the bit is 0, the counter has */ + /* not reached the TRR value; */ + /* otherwise, the counter has */ + /* reached the TRR value. Writing */ + /* a 1 clears this bit. */ + +#define MCF5272_TIMER_TER_CAP (0x0001) /* Captuer event. If this bit is */ +#define MCF5272_TIMER_TER_CAP_BIT (0) /* 0, the counter value has not */ + /* been latched into the TCR; */ + /* otherwise, the counter value is */ + /* latched into the TCR. Writing a */ + /* 1 clears this bit. */ + + u32_t res6[3]; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_timer_t; + +/* Watchdog timer */ +typedef struct mcf5272_sim_wdtmr_t +{ + + u16_t wrrr; /* Watchdog reset reference */ + u16_t res1; /* register. */ + + u16_t wirr; /* Watchdog interrupt reference */ + u16_t res2; /* register. */ + + u16_t wcr; /* Watchdog counter register. */ + u16_t res3; + + u16_t wer; /* Watchdog event register. */ + u16_t res4; + + u32_t res5[28]; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t; + +/* Ethernet Module */ +typedef struct mcf5272_sim_enet_t +{ + + u8_t res1[0x40]; + + u32_t ecr; /* Ethernet control register */ + + u32_t eir; /* Interrupt event register */ + + u32_t eimr; /* Interrupt mask register */ + + u32_t ivsr; /* Interrupt vector status */ + /* register */ + + u32_t rdar; /* Receive descriptor active */ + /* register */ + + u32_t tdar; /* Transmit descriptor active */ + /* register */ + + u8_t res2[0x0880-0x0858]; + + u32_t mmfr; /* MII management frame register */ + + u32_t mscr; /* MII speed control register */ + + u8_t res3[0x08cc-0x0888]; + + u32_t frbr; /* FIFO receive bound register */ + + u32_t frsr; /* FIFO receive start register */ + + u8_t res4[0x08e4-0x08d4]; + + u32_t tfwr; /* Transmit FIFO watermark */ + + u8_t res5[0x08ec-0x08e8]; + + u32_t tfsr; /* Transmit FIFO start register */ + + u8_t res6[0x0944-0x08f0]; + + u32_t rcr; /* Receive control register */ + + u32_t mflr; /* Maximum frame length register */ + + u8_t res7[0x0984-0x094c]; + + u32_t tcr; /* Transmit control register */ + + u8_t res8[0x0c00-0x0988]; + + u32_t malr; /* Lower 32-bits of MAC address */ + + u32_t maur; /* Upper 16-bits of MAC address */ + + u32_t htur; /* Upper 32-bits of hash table */ + + u32_t htlr; /* Lower 32-bits of hash table */ + + u32_t erdsr; /* Pointer to receive descriptor */ + /* ring */ + + u32_t etdsr; /* Pointer to transmit descriptor */ + /* ring */ + + u32_t emrbr; /* Maximum receive buffer size */ + + u8_t res9[0x0c40-0x0c1c]; + + u8_t efifo[448]; /* FIFO RAM space */ + + u8_t res10[0x1000-0x0e00]; + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_enet_t; + +/* System Integration Module (SIM) This structure defines each */ +/* register's offset from the current value of the mbar register. */ +typedef struct mcf5272_sim_t +{ + + mcf5272_sim_cfg_t cfg; /* 0x0000: General configuration */ + /* registers. */ + + mcf5272_sim_int_t intc; /* 0x0020: Interrupt controller */ + /* registers. */ + + mcf5272_sim_cs_t cs[8]; /* 0x0040: Chip Select Module */ + + mcf5272_sim_gpio_t gpio; /* 0x0080: General purpose I/O */ + /* control registers */ + + u32_t qspi[8]; /* 0x00a0: Queued serial */ + /* peripheral interface module. */ + + u32_t pwm[8]; /* 0x00c0: Pulse Width Modulation */ + /* (PWM) Module */ + + u32_t dmac[8]; /* 0x00e0: DMA Controller */ + + mcf5272_sim_uart_t uart[2]; /* 0x0100: UART Modules */ + + u32_t sdramc[32]; /* 0x0180: SDRAM Controller */ + + mcf5272_sim_timer_t timer[4]; /* 0x0200: Timer Module */ + + mcf5272_sim_wdtmr_t wdtimer; /* 0x0280: Watchdog Timer Module */ + + u32_t plic[320]; /* 0x0300: Physical Layer */ + /* Interface Controller */ + + mcf5272_sim_enet_t enet; /* 0x0800: Ethernet Module */ + + u32_t usb[512]; /* 0x1000: Universal Serial Bus */ + +} __attribute__ ((aligned (4), packed)) mcf5272_sim_t; + +#endif /* MCF5272_SIM_H */ +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_arch.h @@ -0,0 +1,65 @@ +#ifndef CYGONCE_HAL_PROC_ARCH_H +#define CYGONCE_HAL_PROC_ARCH_H +//============================================================================= +// +// proc_arch.h +// +// Processor variant specific abstractions +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/mcf5272_sim.h> +//#include <cyg/hal/hal_memmap.h> + +// Declare the global pointer to the SIM registers. +// Everyone should use the MCF5272_SIM macro so it can be easily changed. +externC volatile mcf5272_sim_t * const mcf5272_sim_p; +#define MCF5272_SIM mcf5272_sim_p +//#define MCF5272_SIM ((volatile mcf5272_sim_t *) MCF5272_MBAR) + +/* ************************************************************************ */ +/* These routines write to the special purpose registers in the ColdFire */ +/* core. Since these registers are write-only in the supervisor model, no */ +/* corresponding read routines exist. */ + +externC void mcf5272_wr_mbar(CYG_WORD32); + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PROC_ARCH_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_intr.h @@ -0,0 +1,211 @@ +#ifndef CYGONCE_HAL_PROC_INTR_H +#define CYGONCE_HAL_PROC_INTR_H + +//========================================================================== +// +// proc_intr.h +// +// mcf5272 Processor variant interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// Include any platform specific interrupt definitions. +#include <cyg/hal/plf_intr.h> + +// Include for the SIM address (MCF5272_SIM). +#include <cyg/hal/proc_arch.h> + +//--------------------------------------------------------------------------- +// Interrupt controller management + +// This chip has a programmable interrupt vector base which is different +// from the vector base register (VBR). All interrupts from the interrupt +// controller are offsets from the programmable interrupt vector register +// (PIVR). + +#define HAL_PROG_INT_VEC_BASE 64 + +// Vector numbers defined by the interrupt controller. +// These are all relative to the interrupt vector base number. +#define CYGNUM_HAL_VECTOR_USR_SPUR_INT (0 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT1 (1 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT2 (2 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT3 (3 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT4 (4 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_TMR1 (5 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_TMR2 (6 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_TMR3 (7 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_TMR4 (8 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_UART1 (9 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_UART2 (10 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_PLIP (11 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_PLIA (12 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB0 (13 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB1 (14 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB2 (15 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB3 (16 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB4 (17 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB5 (18 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB6 (19 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_USB7 (20 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_DMA (21 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_ERX (22 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_ETX (23 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_ENTC (24 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_QSPI (25 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT5 (26 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_EXTINT6 (27 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_SWTO (28 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_RES1 (29 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_RES2 (30 + HAL_PROG_INT_VEC_BASE) +#define CYGNUM_HAL_VECTOR_RES3 (31 + HAL_PROG_INT_VEC_BASE) + +//--------------------------------------------------------------------------- +// Interrupt controller macros. + +// Declare a mirror copy of the interrupt control registers used to set +// interrupt priorities. In order to mask and unmask a specific interrupt, we +// must be able to set its priority to zero and then restore it to ist +// original priority. We use these locations to determine the level to +// restore the interrupt to in the unmask macro. + +externC cyg_uint32 hal_icr_pri_mirror[4]; + +// Block the interrupt associated with the given vector. To do this, we +// set the interrupt priority level to zero for the specified interrupt. To +// set the interrupt priority level, we simultaneously write a 1 to the +// pending interrupt field. The other interrupts are unaffected. Disable all +// interrupts while we access the hardware registers. + +#define HAL_INTERRUPT_MASK( _vector_ ) \ +CYG_MACRO_START \ + cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \ + cyg_uint32 _icr = _vec_offset / 8; \ + cyg_uint32 _icr_msk = 0xf0000000 >> ((_vec_offset % 8) * 4); \ + CYG_INTERRUPT_STATE _intr_state; \ + HAL_DISABLE_INTERRUPTS(_intr_state); \ + MCF5272_SIM->intc.icr[_icr] &= _icr_msk ^ 0x77777777; \ + HAL_RESTORE_INTERRUPTS(_intr_state); \ +CYG_MACRO_END + +// Unblock the interrupt associated with the given vector. Set the +// interrupt priority using the value from the icr mirror variable. Disable +// all interrupts while we access the hardware registers. + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ +CYG_MACRO_START \ + cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \ + cyg_uint32 _icr = _vec_offset / 8; \ + cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \ + cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \ + cyg_uint32 _icr_val; \ + CYG_INTERRUPT_STATE _intr_state; \ + HAL_DISABLE_INTERRUPTS(_intr_state); \ + _icr_val = MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \ + _icr_val |= hal_icr_pri_mirror[_icr] & _icr_msk; \ + _icr_val |= 0x08 << _icr_msk_offset; \ + MCF5272_SIM->intc.icr[_icr] = _icr_val; \ + HAL_RESTORE_INTERRUPTS(_intr_state); \ +CYG_MACRO_END + +// Acknowledge the interrupt by writing a 1 to the corresponding +// interrupt pending bit. Write 0 to all other interrupt pending bits. Leave +// all priority levels unchanged. Disable all interrupts while we access the +// hardware registers. + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ +CYG_MACRO_START \ + cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \ + cyg_uint32 _icr = _vec_offset / 8; \ + cyg_uint32 _icr_msk = 0x80000000 >> ((_vec_offset % 8) * 4); \ + CYG_INTERRUPT_STATE _intr_state; \ + HAL_DISABLE_INTERRUPTS(_intr_state); \ + MCF5272_SIM->intc.icr[_icr] &= _icr_msk | 0x77777777; \ + HAL_RESTORE_INTERRUPTS(_intr_state); \ +CYG_MACRO_END + +// Set the priority in the interrupt control register and the icr mirror. +// Do not copy the icr mirror into the icr because some interrupts may be +// masked. Disable all interrupts while we access the hardware registers. + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_ ) \ +CYG_MACRO_START \ + cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \ + cyg_uint32 _icr = _vec_offset / 8; \ + cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \ + cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \ + cyg_uint32 _icr_val = (0x08 | (_prilevel_ & 0x07)) << _icr_msk_offset; \ + CYG_INTERRUPT_STATE _intr_state; \ + HAL_DISABLE_INTERRUPTS(_intr_state); \ + cyg_uint32 _mir_val = hal_icr_pri_mirror[_icr] & 0x77777777 & ~_icr_msk; \ + hal_icr_pri_mirror[_icr] = _mir_val | _icr_val; \ + _icr_val |= MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \ + MCF5272_SIM->intc.icr[_icr] = _icr_val; \ + HAL_RESTORE_INTERRUPTS(_intr_state); \ +CYG_MACRO_END + +// Set/clear the interrupt transition register bit. Disable all +// interrupts while we access the hardware registers. + +// WARNING: It seems that manual currently has the polarity of this bit +// wrong. + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_ ) \ +CYG_MACRO_START \ + if (!(_leveltriggered_)) \ + { \ + cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \ + cyg_uint32 _itr_bit = 0x80000000 >> _vec_offset; \ + CYG_INTERRUPT_STATE _intr_state; \ + HAL_DISABLE_INTERRUPTS(_intr_state); \ + if (_up_) \ + { \ + MCF5272_SIM->intc.pitr |= _itr_bit; \ + } \ + else \ + { \ + MCF5272_SIM->intc.pitr &= ~_itr_bit; \ + } \ + HAL_RESTORE_INTERRUPTS(_intr_state); \ + } \ +CYG_MACRO_END + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PROC_INTR_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/include/proc_startup.h @@ -0,0 +1,49 @@ +#ifndef _PROC_STARTUP_H +#define _PROC_STARTUP_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> + +// Include the platform-specific startup header. + +#include <cyg/hal/plf_startup.h> + +// Processor-specific reset vector initialization routine + +externC void proc_reset(void); + +#endif // _PROC_STARTUP_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/memcpy.c @@ -0,0 +1,123 @@ +//========================================================================== +// +// memcpy.c +// +// memcpy() routine for coldfire +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +/* INCLUDES */ + +#include <cyg/infra/cyg_type.h> /* Common type definitions */ +#include <stddef.h> /* Compiler defns such as size_t, NULL etc. */ + +/* EXPORTED SYMBOLS */ + +externC void * +memcpy( void * s1, const void * s2, size_t n ) __attribute__((alias("_memcpy"))); + +/* FUNCTIONS */ + +void * +_memcpy( void * s1, const void * s2, size_t n ) +{ + char * dst = (char *) s1; + const char * src = (const char *) s2; + long longwords; + int_t rem_bytes; + int_t loops; + int_t loop_index; + + /* Don't worry about alignment on the coldfire. Most large */ + /* structures should be aligned anyway. */ + + longwords = (long)(n / 4); + rem_bytes = n % 4; + loops = (int_t)(longwords / 32); + loop_index = (int_t)(longwords % 32); + + switch (loop_index) + { + do + { + *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 31: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 30: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 29: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 28: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 27: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 26: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 25: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 24: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 23: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 22: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 21: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 20: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 19: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 18: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 17: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 16: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 15: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 14: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 13: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 12: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 11: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 10: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 9: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 8: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 7: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 6: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 5: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 4: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 3: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 2: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 1: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++; + case 0: ; /* Keep compiler from complaining. */ + } while (--loops >= 0); + } + + /* Clean up the remaining bytes. */ + + while (--rem_bytes >= 0) + { + *dst++ = *src++; + } + + return s1; + +} /* _memcpy() */ + +/* EOF memcpy.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/proc_arch.S @@ -0,0 +1,68 @@ +##============================================================================= +## +## proc_arch.S +## +## mcf5272 processor code +## +##============================================================================= +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= + +#include <pkgconf/hal.h> + +#------------------------------------------------------------------------------ +# function declaration macro + +#define FUNC_START(name) \ + .text; \ + .even; \ + .globl name; \ +name: + +/* ************************************************************************ */ +/* These routines write to the special purpose registers in the ColdFire */ +/* core. Since these registers are write-only in the supervisor model, no */ +/* corresponding read routines exist. */ + +FUNC_START(mcf5272_wr_mbar) + move.l 4(%sp),%d0 + movec %d0,%mbar + nop + rts + +##============================================================================= +##============================================================================= + +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/proc_misc.c @@ -0,0 +1,62 @@ +//========================================================================== +// +// proc_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/proc_arch.h> +#include <cyg/hal/hal_memmap.h> + +// Define the global pointer to the SIM registers. + +volatile mcf5272_sim_t * const mcf5272_sim_p = (mcf5272_sim_t *)MCF5272_MBAR; + +// Define a mirror copy of the interrupt control registers used to set +// interrupt priorities. In order to mask and unmask a specific interrupt, we +// must be able to set its priority to zero and then restore it to ist +// original priority. We use these locations to determine the level to +// restore the interrupt to in the unmask macro. + +cyg_uint32 hal_icr_pri_mirror[4]; + +//-------------------------------------------------------------------------- +// End of var_misc.c +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/mcf5272/proc/current/src/proc_startup.c @@ -0,0 +1,90 @@ +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> +#include <pkgconf/hal.h> +#include <cyg/hal/hal_startup.h> +#include <cyg/hal/hal_memmap.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> + +/***************************************************************************** +proc_reset -- Processor-specific reset vector initialization routine + + This routine must be called with interrupts disabled. + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void proc_reset(void) +{ + int i; + + // Set up the mapping of our internal registers. The LSB indicates that + // the registers are valid. + + mcf5272_wr_mbar((CYG_WORD32)(MCF5272_MBAR | 1)); + + // Initialize the vector base register in the interrupt controller. + + MCF5272_SIM->intc.ipvr = HAL_PROG_INT_VEC_BASE; + + // Initialize the interrupt control register and the icr priority + // mirror. Disable all interrupts by setting all priorities to zero. + + for (i=0; i < 4; i++) + { + MCF5272_SIM->intc.icr[i] = hal_icr_pri_mirror[i] = 0x88888888; + } + + // Enable/disable the data transfter acknowledge output pin. + + MCF5272_SIM->gpio.pbcnt = ((MCF5272_SIM->gpio.pbcnt & + ~(MCF5272_GPIO_PBCNT_TA_MSK)) | + ((HAL_MCF5272_ENABLE_DATA_TA) ? + (MCF5272_GPIO_PBCNT_TA_EN) : + (MCF5272_GPIO_PBCNT_TA_DE))); + + // Do any platform-specific reset initialization. + + plf_reset(); +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/cdl/hal_m68k_mcf52xx.cdl @@ -0,0 +1,70 @@ +# ==================================================================== +# +# hal_m68k_mcf52xx.cdl +# +# mcf52xx variant architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== + +cdl_package CYGPKG_HAL_M68K_MCF52xx { + display "68k/Coldfire version 2 core HAL" + parent CYGPKG_HAL_M68K + requires CYGPKG_HAL_M68K + hardware + include_dir cyg/hal + define_header hal_m68k_mcf52xx.h + + description "The 68k/Coldfire version 2 core HAL package provides + generic support for the version 2 Coldfire core. It is also + necessary to select a specific target platform HAL package." + + define_proc { + puts $::cdl_header "#include <pkgconf/hal_m68k.h>" + } + + compile var_startup.c var_misc.c var_arch.S + + make { + <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S + $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail +2 vectors.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm vectors.tmp + } + +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_arch.h @@ -0,0 +1,217 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// Architecture variant specific abstractions +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/proc_arch.h> + +// The ColdFire family of processors has a simplified exception stack +// frame that looks like the following: +// +// 3322222222221111 111111 +// 1098765432109876 5432109876543210 +// 8 +----------------+----------------+ +// | Program Counter | +// 4 +----------------+----------------+ +// |Fmt/FS/Vector/FS| SR | +// SP --> 0 +----------------+----------------+ +// +// The stack self-aligns to a 4-byte boundary at an exception, with +// the Fmt/FS/Vector/FS field indicating the size of the adjustment +// (SP += 0,1,2,3 bytes). + +// Define the Fmt/FS/Vector/FS word. +// The first four bits are the format word which tells the +// RTI instruction how to align the stack. +#define HAL_MCF52XX_RD_SF_FORMAT_MSK ((CYG_WORD16)0xF000) +// These bits are the vector number of the exception. +#define HAL_MCF52XX_RD_SF_VECTOR_MSK ((CYG_WORD16)0x03FC) +// These are bits 3-2, and 1-0 of the fault status used +// for bus and address errors. +#define HAL_MCF52XX_RD_SF_FS32_MSK ((CYG_WORD16)0x0C00) +#define HAL_MCF52XX_RD_SF_FS10_MSK ((CYG_WORD16)0x0003) + +// Macros to access fields in the format vector word. + +#define HAL_MCF52XX_RD_SF_FORMAT(_fmt_vec_word_) \ + ((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FORMAT_MSK) >> 12) + +#define HAL_MCF52XX_RD_SF_VECTOR(_fmt_vec_word_) \ + ((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_VECTOR_MSK) >> 2) + +#define HAL_MCF52XX_RD_SF_FS(_fmt_vec_word_) \ + (((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FS32_MSK) >> 8) \ + | (((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FS10_MSK)) + +/***************************************************************************** + Exception handler saved context. Some exceptions contain extra +information following this common exception handler context. +*****************************************************************************/ +typedef struct +{ + + // Data regs D0-D7 + + #define HAL_EXC_NUM_D_REGS 8 + CYG_WORD32 d[HAL_EXC_NUM_D_REGS]; + + // Address regs A0-A6 + + #define HAL_EXC_NUM_A_REGS 7 + CYG_ADDRESS a[HAL_EXC_NUM_A_REGS]; + + // Stack Pointer + + CYG_ADDRESS sp; + + // 16-bit format/vector word + + CYG_WORD16 fmt_vec_word; + + // Status Reg + + CYG_WORD16 sr; + + // Program Counter + + CYG_ADDRESS pc; + +} __attribute__ ((aligned, packed)) HAL_SavedRegisters_exception; + +#ifndef HAL_GENERIC_SAVED_CONTEXT +/***************************************************************************** +HAL_GENERIC_SAVED_CONTEXT -- Generic saved context structure + + This structure could contain a normal saved context or an exception +context. + +*****************************************************************************/ +#define HAL_GENERIC_SAVED_CONTEXT \ +typedef union \ +{ \ + HAL_SavedRegisters_normal normal; \ + HAL_SavedRegisters_exception exception; \ +} __attribute__ ((aligned, packed)) HAL_SavedRegisters; +#endif // HAL_GENERIC_SAVED_CONTEXT + +//----------------------------------------------------------------------------- +// Thread register state manipulation for GDB support. + +// Translate a stack pointer as saved by the thread context macros above into +// a pointer to a HAL_SavedRegisters structure. +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ + (_regs_) = (HAL_SavedRegisters *)(_sp_) + +// Copy a set of registers from a HAL_SavedRegisters structure into a +// GDB ordered array. + +/* there are 180 bytes of registers on a 68020 w/68881 */ +/* many of the fpa registers are 12 byte (96 bit) registers */ +/* +#define NUMREGBYTES 180 +enum regnames {D0,D1,D2,D3,D4,D5,D6,D7, + A0,A1,A2,A3,A4,A5,A6,A7, + PS,PC, + FP0,FP1,FP2,FP3,FP4,FP5,FP6,FP7, + FPCONTROL,FPSTATUS,FPIADDR + }; +*/ + +#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ + CYG_MACRO_START \ + CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ + int _i_; \ + \ + for( _i_ = 0; _i_ < HAL_NUM_D_REGS; _i_++ ) \ + *_regval_++ = (_regs_)->nml_ctxt.d[_i_]; \ + \ + for( _i_ = 0; _i_ < HAL_NUM_A_REGS; _i_++ ) \ + *_regval_++ = (_regs_)->nml_ctxt.a[_i_]; \ + \ + *_regval_++ = (_regs_)->nml_ctxt.sp; \ + *_regval_++ = (CYG_ADDRWORD) ((_regs_)->nml_ctxt.sr); \ + *_regval_++ = (_regs_)->nml_ctxt.pc; \ + /* Undefined registers */ \ + for ( _i_ = 0; _i_ < 8; _i_++ ) \ + { \ + *((CYG_WORD16*)_regval_)++ = _i_; \ + *((CYG_WORD16*)_regval_)++ = _i_; \ + *((CYG_WORD16*)_regval_)++ = _i_; \ + } \ + *_regval_++ = 0xBADC0DE0; \ + *_regval_++ = 0xBADC0DE1; \ + *_regval_++ = 0xBADC0DE2; \ + CYG_MACRO_END + +// Copy a GDB ordered array into a HAL_SavedRegisters structure. +#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ + CYG_MACRO_START \ + CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ + int _i_; \ + \ + for( _i_ = 0; _i_ < HAL_NUM_D_REGS; _i_++ ) \ + (_regs_)->nml_ctxt.d[_i_] = *_regval_++; \ + \ + for( _i_ = 0; _i_ < HAL_NUM_A_REGS; _i_++ ) \ + (_regs_)->nml_ctxt.a[_i_] = *_regval_++; \ + \ + (_regs_)->nml_ctxt.sp = *_regval_++; \ + (_regs_)->nml_ctxt.sr = (CYG_WORD16) (*_regval_++); \ + (_regs_)->nml_ctxt.pc = *_regval_++; \ + CYG_MACRO_END + +/* ************************************************************************ */ +/* These routines write to the special purpose registers in the ColdFire */ +/* core. Since these registers are write-only in the supervisor model, no */ +/* corresponding read routines exist. */ + +externC void mcf52xx_wr_vbr(CYG_WORD32); +externC void mcf52xx_wr_cacr(CYG_WORD32); +externC void mcf52xx_wr_acr0(CYG_WORD32); +externC void mcf52xx_wr_acr1(CYG_WORD32); +externC void mcf52xx_wr_rambar(CYG_WORD32); + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_ARCH_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_basetype.h @@ -0,0 +1,59 @@ +#ifndef CYGONCE_HAL_VAR_BASETYPE_H +#define CYGONCE_HAL_VAR_BASETYPE_H + +//============================================================================= +// +// var_basetype.h +// +// Standard types for this architecture variant. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +// Use defaults for this architecture. + +// TEMPORARY TO REMOVE WARNINGS! The 68k architecture compiler complains +// when the object file alignment is greater than 2. + +#ifndef CYGARC_ALIGNMENT +#define CYGARC_ALIGNMENT 2 +#endif +#ifndef CYGARC_P2ALIGNMENT +#define CYGARC_P2ALIGNMENT 1 +#endif + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_BASETYPE_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_cache.h @@ -0,0 +1,174 @@ +#ifndef CYGONCE_VAR_CACHE_H +#define CYGONCE_VAR_CACHE_H +//============================================================================= +// +// var_cache.h +// +// Variant HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// We currently just enable the instruction cache on startup. There is +// no data cache. + +//----------------------------------------------------------------------------- +// Cache dimensions - these vary between the 8xx sub-models + +// Data cache +#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +#define HAL_DCACHE_WAYS 1 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +#define HAL_ICACHE_WAYS 1 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +// Note: Any locked lines will not be invalidated. +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache +#define HAL_ICACHE_IS_ENABLED(_state_) + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_VAR_CACHE_H +// End of var_cache.h +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_gen_types.h @@ -0,0 +1,53 @@ +#ifndef _VAR_GEN_TYPES_H +#define _VAR_GEN_TYPES_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +/* + + ********************* + * * + * General Types * + * * + ********************* + + Define some simple variable sizes for the mcf52xx architecture. + +*/ + +// We use the defaults for the m68k architecture. + +#endif // _VAR_GEN_TYPES_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_intr.h @@ -0,0 +1,53 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// mcf52xx Variant interrupt and clock support +// +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> + +// Include any processor specific interrupt definitions. +#include <cyg/hal/proc_intr.h> + +//--------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_VAR_INTR_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/include/var_startup.h @@ -0,0 +1,49 @@ +#ifndef _VAR_STARTUP_H +#define _VAR_STARTUP_H +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> + +// Include the processor-specific startup header. + +#include <cyg/hal/proc_startup.h> + +// Variant-specific reset vector initialization routine + +externC void var_reset(void); + +#endif // _VAR_STARTUP_H +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/context.S @@ -0,0 +1,105 @@ +##============================================================================= +## +## context.S +## +## mcf52xx context switch code +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= + +#include <pkgconf/hal.h> + +#------------------------------------------------------------------------------ +# function declaration macro + +#define FUNC_START(name) \ + .text; \ + .even; \ + .globl name; \ +name: + +#------------------------------------------------------------------------------ +# hal_thread_switch_context +# Switch thread contexts +# : 0(%sp) : return address +# : 4(%sp) : to - address of sp of next thread to execute +# : 8(%sp) : from - address of sp save location of current thread +# +# d0, d1, a0, a1 are ours to abuse. +# +# externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); + +FUNC_START(hal_thread_switch_context) + + move.l 4(%sp),%a0 /* Read the to and from from */ + move.l 8(%sp),%a1 /* parameters from the stack. */ + + lea -(6+5)*4(%sp),%sp /* Save all of the registers */ + movem.l %d2-%d7/%a2-%a6,(%sp) /* that the C calling */ + /* convention expects us to */ + /* preserve. */ + + move.l %sp,(%a1) /* Store this threads current */ + /* stack pointer to *from. */ + + move.l (%a0),%sp /* Load the stack pointer for */ + /* the next thread from *to. */ + + movem.l (%sp),%d2-%d7/%a2-%a6 /* Load all of the preserved */ + lea (6+5)*4(%sp),%sp /* registers from the stack. */ + + rts /* Restore the PC. */ + +#------------------------------------------------------------------------------ +# hal_thread_load_context +# Load thread context +# : 4(%sp) : to - address of sp of next thread to execute +# +# d0, d1, a0, a1 are ours to abuse. + +FUNC_START(hal_thread_load_context) + + move.l 4(%sp),%a0 /* Read the to parameter from */ + move.l (%a0),%sp /* the stack and switch to that */ + /* stack pointer. */ + + movem.l (%sp),%d2-%d7/%a2-%a6 /* Load all of the preserved */ + lea (6+5)*4(%sp),%sp /* registers from the stack. */ + + rts /* Restore the PC. */ + +##============================================================================= +##============================================================================= +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/var_arch.S @@ -0,0 +1,87 @@ +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +/***************************************************************************** +var_arch.S -- mcf52xx variant code +*****************************************************************************/ + +#include <pkgconf/hal.h> + +/***************************************************************************** +FUNC_START -- Function declaration macro +*****************************************************************************/ +#define FUNC_START(name) \ + .text; \ + .even; \ + .globl name; \ +name: + +/* ************************************************************************ */ +/* These routines write to the special purpose registers in the ColdFire */ +/* core. Since these registers are write-only in the supervisor model, no */ +/* corresponding read routines exist. */ + +FUNC_START(mcf52xx_wr_vbr) + move.l 4(%sp),%d0 + andi.l #0xFFF00000,%d0 /* align to 1M boundary */ + movec %d0,%vbr + nop + rts + +FUNC_START(mcf52xx_wr_cacr) + move.l 4(%sp),%d0 + movec %d0,%cacr + nop + rts + +FUNC_START(mcf52xx_wr_acr0) + move.l 4(%sp),%d0 + movec %d0,%acr0 + nop + rts + +FUNC_START(mcf52xx_wr_acr1) + move.l 4(%sp),%d0 + movec %d0,%acr1 + nop + rts + +FUNC_START(mcf52xx_wr_rambar) + move.l 4(%sp),%d0 + .equ rambar,0xc04 /* Rc for movec */ + movec %d0,#rambar + nop + rts + +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/var_misc.c @@ -0,0 +1,69 @@ +//========================================================================== +// +// var_misc.c +// +// HAL implementation miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_arch.h> + +//-------------------------------------------------------------------------- +// VSR table + +// For the mcf52xx, we can point the VBR directly to the VSR table. +// However, the table must be on a 1 MB boundary. Locate the VSR table where +// the linker tells us to. + +volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT] + __attribute__ ((section (".ramvec"))); + +//-------------------------------------------------------------------------- +void hal_variant_init(void) +{ + + // Don't need to do anything yet. + +} + +//-------------------------------------------------------------------------- +// End of var_misc.c +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/var_startup.c @@ -0,0 +1,100 @@ +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== + +#include <cyg/infra/cyg_type.h> +#include <pkgconf/hal.h> +#include <cyg/hal/hal_startup.h> +#include <cyg/hal/hal_memmap.h> +#include <cyg/hal/hal_arch.h> + +/***************************************************************************** +var_init_cache_acr -- Initialize the cache and access control registers + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +static void var_init_cache_acr(void) +{ + + // Invalidate and disable the cache and ACRs. + + mcf52xx_wr_cacr((CYG_WORD32)0x01000000); + mcf52xx_wr_acr0((CYG_WORD32)0); + mcf52xx_wr_acr1((CYG_WORD32)0); + + // Call a routine to set up the cache and ACRs for this specific + // platform. + + plf_init_cache_acr(); + +} + +/***************************************************************************** +var_reset -- Variant-specific reset vector initialization routine + + This routine must be called with interrupts disabled. + +INPUT: + +OUTPUT: + +RETURN VALUE: + + None + +*****************************************************************************/ +void var_reset(void) +{ + + // Initialize the processor's vector base register. + + mcf52xx_wr_vbr((CYG_WORD32)__ramvec_start); + + // Initialize the cache and access control registers. + + var_init_cache_acr(); + + // Do any processor-specific reset initialization. + + proc_reset(); +} + +
new file mode 100644 --- /dev/null +++ b/packages/hal/m68k/mcf52xx/var/current/src/vectors.S @@ -0,0 +1,489 @@ +/***************************************************************************** +vectors.S -- mcf52xx exception vectors +*****************************************************************************/ +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif /* CYGPKG_KERNEL */ + +/****************************************************************************/ + + .file "vectors.S" + +/****************************************************************************/ + +/****************************************************************************/ + +/* The mcf52xx core allows us to move the VBR to our RAM vector table */ +/* at cyg_hal_vsr_table provided the table is at a 1MB boundary. */ + +/****************************************************************************/ +/* ROM vector table */ + +/* Create the ROM vector table. We use this table to initialize */ +/* cyg_hal_vsr_table which we point the VBR to. */ + + .macro hw_vsr name + .long hw_vsr_\name + .endm + + .section ".romvec","ax" + + .globl rom_vsr_table +rom_vsr_table: + + /* 0 - Initial SSP */ + hw_vsr stack + + /* 1 - Initial PC */ + hw_vsr reset + + /* 2-24 - Default exception handlers */ + .rept 24-2+1 + hw_vsr default + .endr + + /* 25-31 - Autovector interrupts 1-7 */ + .rept 31-25+1 + hw_vsr autovec + .endr + + /* 32-63 - Default exception handlers */ + .rept 63-32+1 + hw_vsr default + .endr + + /* 64-255 - User interrupt vectors */ + .rept 255-64+1 + hw_vsr interrupt + .endr + + .equ rom_vsr_table_size, . - rom_vsr_table + +/****************************************************************************/ +/* The default excetpion vector handler */ + +/* The default handler for all machine exceptions. We save the */ +/* machine state and call the default C VSR handler. This routine passes a */ +/* pointer to the saved state to the C VSR handler. The stack pointer in */ +/* the saved state points to the byte following the PC on the exception */ +/* stack (the sp before the exception). The format/vector word in the */ +/* exception stack contains the vector number. */ + +/* +void hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs); +*/ + + .text + .balign 4 +hw_vsr_default: + + lea.l -(16*4)(%sp),%sp /* Preserve the entire state. */ + movem.l %d0-%d7/%a0-%a6,(%sp) /* Allocate space for all */ + lea.l ((16+1+1)*4)(%sp),%a0 /* registers (including the */ + move.l %a0,(15*4)(%sp) /* stack pointer). Write all */ + /* registers to the stack */ + /* space. Write the original */ + /* stack pointer value to the */ + /* stack. The format/vector */ + /* word, sr, and pc are already */ + /* on the stack. */ + + move.w (16*4)(%sp),%d0 /* Calculate the vector */ + and.l #0x000003fc,%d0 /* number. The format/vector */ + lsr.l #2,%d0 /* word on the stack contains */ + /* the vector number. */ + + pea.l (%sp) /* Pass a pointer to the */ + /* saved state to the exception */ + /* handler. */ + + move.l %d0,-(%sp) /* Push the vector number */ + /* parameter. */ + + .extern hal_default_exception_handler /* Call the default */ + jbsr hal_default_exception_handler /* exception VSR. This */ + /* routine may (and */ + /* probably will) modify */ + /* the exception context. */ + + addq.l #2*4,%sp /* Remove the vector number */ + /* and the state pointer from */ + /* the stack. */ + + /* Restore the state. There */ + /* is a chance that a debugger */ + /* changed the state (including */ + /* the stack pointer, PC, */ + /* etc.). We must be very */ + /* careful to restore the new */ + /* state without first */ + /* overwriting the values on */ + /* the stack. We must copy the */ + /* format/vector word, SR, and */ + /* PC to the new stack, but we */ + /* must make sure that the new */ + /* stack is not in the middle */ + /* of our current stack */ + /* variables that we are using. */ + + movem.l (%sp),%d0-%d7/%a0-%a4 /* Restore all of the */ + /* registers that we do not */ + /* need in the following code. */ + /* We will copy all registers */ + /* that are not restored here */ + /* to the new stack before */ + /* restoring them. */ + + move.l (15*4)(%sp),%a6 /* Load the address of the */ + /* new SP. */ + + lea.l (18*4)(%sp),%a5 /* Get a pointer to the */ + /* location following the */ + /* exception context. */ + + cmp.l %a5,%a6 /* Compare the new stack */ + jcc 1f /*jcc=jhs*/ /* address to the end of the */ + /* exception context. This */ + /* will tell us the order that */ + /* we need to copy the */ + /* exception stack and the */ + /* remaining registers from the */ + /* exception context to the new */ + /* stack. The order is */ + /* important because the stack */ + /* frames might (and in many */ + /* cases do) overlap. */ + + /* The new SP is at a lower */ + /* address than the end of the */ + /* exception context. Copy */ + /* from the lowest address to */ + /* the highest address. */ + + lea.l -5*4(%a6),%a6 /* Copy A5, A6, FVW, SR, and */ + move.l -5*4(%a5),(%a6) /* PC from the old stack to the */ + move.l -4*4(%a5),1*4(%a6) /* new stack. Note that we do */ + move.l -2*4(%a5),3*4(%a6) /* not copy the SP location but */ + move.l -1*4(%a5),4*4(%a6) /* we leave a space for it on */ + /* the new stack. If we do not */ + /* leave space for the SP, */ + /* there is a possibility of */ + /* overwriting some of our */ + /* data. Note that we copy in */ + /* increasing order. */ + + move.l %a6,%sp /* A6 points to the top of */ + move.l (%sp)+,%a5 /* the new stack with our */ + move.l (%sp)+,%a6 /* registers on it. Restore */ + addq.l #1*4,%sp /* the remaining registers and */ + rte /* use the exception stack to */ + /* return. Note that we also */ + /* remove the unused space left */ + /* for the SP. */ + +1: + + move.l -(%a5),-(%a6) /* The new SP is at a higher */ + move.l -(%a5),-(%a6) /* or the same address as the */ + subq.l #4,%a5 /* end of the exception */ + move.l -(%a5),-(%a6) /* context. Copy from the */ + move.l -(%a5),-(%a6) /* highest address to the */ + /* lowest address. Note that */ + /* we do not copy the stack */ + /* pointer. When copying in */ + /* this direction, there is no */ + /* reason to leave space for */ + /* the stack pointer. */ + + move.l %a6,%sp /* A6 points to the top of */ + move.l (%sp)+,%a5 /* the new stack with our */ + move.l (%sp)+,%a6 /* registers on it. Restore */ + rte /* the remaining registers and */ + /* use the exception stack to */ + /* return. */ + +/****************************************************************************/ +/* User interrupt vector handler */ + +/* Control is transferred here from a user interrupt vector (#64-255). */ + +/* Before branching to common code, load a value to translate the */ +/* vector table offset to the ISR table offset. The ISR vector table */ +/* contains the autovectors (0-6) followed by the interrupt vectors */ +/* (7-198). */ + + .equ int_pres_regs_sz,((2+3)*4) + .macro int_pres_regs + lea.l -int_pres_regs_sz(%sp),%sp + movem.l %d0-%d2/%a0-%a1,(%sp) + .endm + .macro int_rest_regs + movem.l (%sp),%d0-%d2/%a0-%a1 + lea.l int_pres_regs_sz(%sp),%sp + .endm + + .text + .balign 4 +hw_vsr_interrupt: + + int_pres_regs /* Preserve all registers */ + /* that this ISR routine needs */ + /* to preserve. The C code */ + /* will preserve all other */ + /* registers. */ + + move.l #(-64+7)*4,%d0 /* Adding this value to the */ + /* vector table offset will */ + /* result in the corresponding */ + /* offset into the ISR table. */ + + /* Fall through to common code. */ + +hw_vsr_int_common: /* Common code. */ + + /* d0.l: Contains a value to translate the vector table offset to */ + /* the ISR table offset. */ + + move.w int_pres_regs_sz(%sp),%d1 /* Calculate the vector */ + and.l #0x000003fc,%d1 /* offset. The format/vector */ + /* word on the stack contains */ + /* the vector number. Mask off */ + /* all unused bits. The bit */ + /* position of the vector */ + /* number field makes it */ + /* automatically multiplied by */ + /* four. */ + + add.l %d1,%d0 /* Calculate the ISR table */ + /* offset. Add the vector */ + /* table offset to the */ + /* translation value. */ + + asr.l #2,%d1 /* Calculate the vector */ + /* number using the vector */ + /* table offset. */ + + /* d0.l: Contains the offset into the ISR table. */ + + /* d1.l: Contains the vector number. */ + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + + .extern cyg_scheduler_sched_lock /* Lock the scheduler if */ + addq.l #1,cyg_scheduler_sched_lock /* we are using the kernel. */ + +#endif /* CYGFUN_HAL_COMMON_KERNEL_SUPPORT */ + +/* We need to call the following routines. The isr address, data, and */ +/* intr are all from the ISR table. interrupt_end is a C routine and is */ +/* only called if we are using the kernel. regs points to the saved */ +/* registers on the stack. isr_ret is the return address from isr. vector */ +/* is the vector number. */ + +/* +static cyg_uint32 isr(CYG_ADDRWORD vector, + CYG_ADDRWORD data) + +externC void interrupt_end(cyg_uint32 isr_ret, + Cyg_Interrupt *intr, + HAL_SavedRegisters *regs) +*/ + + pea (%sp) /* Push the regs pointer. */ + + .extern cyg_hal_interrupt_objects /* Push the intr object */ + lea cyg_hal_interrupt_objects,%a0 /* pointer from the table. */ + move.l (%a0,%d0.l),-(%sp) + + .extern cyg_hal_interrupt_data /* Push the data value */ + lea cyg_hal_interrupt_data,%a0 /* from the table. */ + move.l (%a0,%d0.l),-(%sp) + + .extern cyg_hal_interrupt_handlers /* Get the address of the */ + lea cyg_hal_interrupt_handlers,%a0 /* ISR from the table. */ + move.l (%a0,%d0.l),%a0 + + move.l %d1,-(%sp) /* Push the vector number */ + /* parameter. */ + + jbsr (%a0) /* Call the ISR. */ + + addq.l #4*1,%sp /* Remove the vector */ + /* parameter from the stack. */ + + move.l %d0,(%sp) /* d0.l contains the return */ + /* value from the ISR. */ + /* Overwrite the data parameter */ + /* with the ISR return value to */ + /* pass as a parameter */ + /* (isr_ret) to interrupt_end. */ + /* The intr object and regs */ + /* parameters are still on the */ + /* stack. */ + +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + + /* We only need to call interrupt_end() when there is a kernel */ + /* present to do any tidying up. */ + + /* The interrupt_end routine will call the DSRs and do */ + /* rescheduling when it decrements the scheduler lock from 1 to */ + /* zero. In this case, we do not want to have interrupts masked */ + /* while the DSRs run. Restore the interrupt mask to the value */ + /* prior to this interrupt. Do not completely unmask all */ + /* interrupts because this interrupt may be a nested interrupt. We */ + /* do not want to lower the interrupt mask on the lower priority */ + /* interrupt. */ + + move.w (4*3)+int_pres_regs_sz+2(%sp),%d2 + move.w %d2,%sr + + /* If the interrupt mask was not previously zero, we want to make */ + /* sure that the DSRs to not run and no preemption occurs. Add the */ + /* value of the previous interrupt mask to the scheduler lock. If */ + /* the previous mask was zero, the scheduler lock will remain at */ + /* one and the interrupt end function will decrement it to zero. */ + /* Otherwise, we want to prevent the interrupt end function from */ + /* unlocking the scheduler. We do this because there is a chance */ + /* that someone had interrupts masked with the scheduler lock at */ + /* zero. If a higher priority interrupt occurs, we could be */ + /* running DSRs and doing preemption with the interrupts masked! */ + + and.l #0x0700,%d2 + lsr.l #8,%d2 + add.l %d2,cyg_scheduler_sched_lock + + .extern interrupt_end /* Call the interrupt_end C */ + jbsr interrupt_end /* routine. This routine might */ + /* preempt the currently */ + /* running thread. */ + + /* Now that interrupt end is complete, subtract the previous */ + /* interrupt level back out of the scheduler lock. */ + + sub.l %d2,cyg_scheduler_sched_lock + +#endif + + lea (4*3)(%sp),%sp /* Remove the isr_ret, intr, */ + /* and regs parameters from the */ + /* stack. */ + + int_rest_regs /* Restore the preserved */ + /* registers for the current */ + /* thread. */ + + rte /* Restore the SR and PC. */ + +/****************************************************************************/ +/* Autovector interrupt vector handler. */ + +/* Control is transferred here from an interrupt autovector (#25-31). */ + +/* Before branching to common code, load a value to translate the */ +/* vector table offset to the ISR table offset. The ISR vector table */ +/* contains the autovectors (0-6) followed by the interrupt vectors */ +/* (7-198). */ + + .text + .balign 4 +hw_vsr_autovec: + + int_pres_regs /* Preserve all registers */ + /* that this ISR routine needs */ + /* to preserve. The C code */ + /* will preserve all other */ + /* registers. */ + + move.l #(-25+0)*4,%d0 /* Adding this value to the */ + /* vector table offset will */ + /* result in the corresponding */ + /* offset into the ISR table. */ + + jra hw_vsr_int_common /* Branch into common code. */ + +/****************************************************************************/ +/* hw_vsr_reset -- Hardware Reset Vector */ + +/* We assume that most of the chip selects are configured by the boot */ +/* loader. */ + + .text + .balign 4 + .globl hw_vsr_reset +hw_vsr_reset: + + .globl __exception_reset /* Define the entry point for */ +__exception_reset: /* the linker. */ + + move.w #0x2700,%sr /* Make sure that all */ + /* interrupts are masked. */ + + lea hw_vsr_stack,%sp /* Load the reset and */ + /* interrupt stack pointer. */ + + lea 0,%fp /* Set up the initial frame */ + link %fp,#0 /* pointer. */ + + .extern hal_reset /* Call the C routine to */ + jbsr hal_reset /* complete the reset process. */ + +9: stop #0x2000 /* If we return, stop. */ + jra 9b + +/****************************************************************************/ +/* Interrupt and reset stack */ + +/* WARNING: Do not put this in any memory section that gets */ +/* initialized. Doing so may cause the C code to initialize its own stack. */ + + .section ".uninvar","aw",@nobits + + .balign 16 + .global hw_vsr_stack_bottom +hw_vsr_stack_bottom: + .skip 0x2000 + .balign 16 + .global hw_vsr_stack +hw_vsr_stack: + .skip 0x10 + +/****************************************************************************/ +
--- a/packages/hal/mips/mips32/current/ChangeLog +++ b/packages/hal/mips/mips32/current/ChangeLog @@ -1,3 +1,8 @@ +2002-05-24 Jesper Skov <jskov@redhat.com> + + * include/var_arch.h: Removed HAL_DIAG_IRQ_CHECK. It's not + implemented. + 2002-05-22 Jesper Skov <jskov@redhat.com> * include/var_arch.h: Added __ASSEMBLER__ protection.
--- a/packages/hal/mips/mips32/current/include/var_arch.h +++ b/packages/hal/mips/mips32/current/include/var_arch.h @@ -87,20 +87,6 @@ //-------------------------------------------------------------------------- -#ifndef __ASSEMBLER__ -#ifdef CYGSEM_HAL_USE_ROM_MONITOR_CygMon -externC int -hal_diag_irq_check(int vector); - -#define HAL_DIAG_IRQ_CHECK(_vector_, _ret_) \ -CYG_MACRO_START \ -_ret_ = hal_diag_irq_check((_vector_)); \ -CYG_MACRO_END -#endif -#endif /* __ASSEMBLER__ */ - -//-------------------------------------------------------------------------- - #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS /* System Control Coprocessor (CP0) exception processing registers */ /* These supplement the definitions in mips-regs.h */
--- a/packages/hal/mips/mips64/current/ChangeLog +++ b/packages/hal/mips/mips64/current/ChangeLog @@ -1,3 +1,8 @@ +2002-05-24 Jesper Skov <jskov@redhat.com> + + * include/var_arch.h: Removed HAL_DIAG_IRQ_CHECK. It's not + implemented. + 2002-05-22 Jesper Skov <jskov@redhat.com> * include/var_arch.h: Added __ASSEMBLER__ protection.
--- a/packages/hal/mips/mips64/current/include/var_arch.h +++ b/packages/hal/mips/mips64/current/include/var_arch.h @@ -102,21 +102,6 @@ : "r" (tmp), "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \ } - -//-------------------------------------------------------------------------- - -#ifndef __ASSEMBLER__ -#ifdef CYGSEM_HAL_USE_ROM_MONITOR_CygMon -externC int -hal_diag_irq_check(int vector); - -#define HAL_DIAG_IRQ_CHECK(_vector_, _ret_) \ -CYG_MACRO_START \ -_ret_ = hal_diag_irq_check((_vector_)); \ -CYG_MACRO_END -#endif -#endif /* __ASSEMBLER__ */ - //-------------------------------------------------------------------------- #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
--- a/packages/hal/v85x/ceb_v850/current/ChangeLog +++ b/packages/hal/v85x/ceb_v850/current/ChangeLog @@ -1,3 +1,8 @@ +2002-05-28 Jonathan Larmour <jlarmour@redhat.com> + + * include/hal_platform_setup.h: Correctly calculate wait states based + on external RAM/ROM timing. + 2002-04-24 Jesper Skov <jskov@redhat.com> * cdl/hal_v85x_ceb_v850.cdl: CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES
--- a/packages/hal/v85x/ceb_v850/current/include/hal_platform_setup.h +++ b/packages/hal/v85x/ceb_v850/current/include/hal_platform_setup.h @@ -74,20 +74,32 @@ // Internal RAM, internal ROM and I/O - no wait states, regardless // of the setting of DWC -#if CYGHWR_HAL_V85X_CPU_FREQ > 17000000 - // External ROM - 3 wait states + // External RAM is 70ns, External ROM is 120ns. Therefore... +#if CYGHWR_HAL_V85X_CPU_FREQ < 14285714 + // External RAM - 0 wait states + movea 0x3F00,r0,r1 +#elif CYGHWR_HAL_V85X_CPU_FREQ < 28571428 + // External RAM - 1 wait state + movea 0x7F00,r0,r1 +#elif CYGHWR_HAL_V85X_CPU_FREQ < 42857142 + // External RAM - 2 wait states + movea 0xBF00,r0,r1 +#else // External RAM - 3 wait states - movea 0xFFFF,r0,r1 -#elif CYGHWR_HAL_V85X_CPU_FREQ > 8000000 + movea 0xFF00,r0,r1 +#endif +#if CYGHWR_HAL_V85X_CPU_FREQ < 8333333 + // External ROM - 0 wait states + ori 0x00FC,r1,r1 +#elif CYGHWR_HAL_V85X_CPU_FREQ < 16666667 + // External ROM - 1 wait states + ori 0x00FD,r1,r1 +#elif CYGHWR_HAL_V85X_CPU_FREQ < 25000000 // External ROM - 2 wait states - // External RAM - 1 wait states - movea 0x7FFE,r0,r1 -#elif CYGHWR_HAL_V85X_CPU_FREQ > 4194304 - // External ROM - 1 wait states - // External RAM - 0 wait states - movea 0x3FFD,r0,r1 + ori 0x00FE,r1,r1 #else - + // External ROM - 3 wait states + ori 0x00FF,r1,r1 #endif st.h r1,lo(V850_REG_DWC)[r6]
--- a/packages/infra/current/ChangeLog +++ b/packages/infra/current/ChangeLog @@ -1,3 +1,11 @@ +2002-05-22 Jesper Skov <jskov@redhat.com> + + * cdl/infra.cdl: Added two options to control CFLAGS. + +2002-05-17 Martin Buck <martin.buck@ascom.ch> + + * include/cyg_type.h (CYGBLD_ATTRIB_PRINTF_FORMAT): Add. + 2002-05-23 Gary Thomas <gthomas@redhat.com> * src/diag.cxx (_vprintf): Mapping of '\n'=>'\r\n' must be done
--- a/packages/infra/current/cdl/infra.cdl +++ b/packages/infra/current/cdl/infra.cdl @@ -185,6 +185,36 @@ cdl_package CYGPKG_INFRA { puts $::cdl_header "/***** proc output end *****/" } + + # ======================================================================== + # Global compiler option controls + + cdl_option CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS { + display "Make all compiler warnings show as errors" + requires { is_substr(CYGBLD_GLOBAL_CFLAGS, " -Werror") } + default_value 0 + description " + Enabling this option will cause all compiler warnings to show + as errors and bring the library build to a halt. This is used + to ensure that the code base is warning free, and thus ensure + that newly introduced warnings stand out and get fixed before + they show up as weird run-time behavior." + } + + cdl_option CYGBLD_INFRA_CFLAGS_PIPE { + display "Make compiler and assembler communicate by pipe" + requires { is_substr(CYGBLD_GLOBAL_CFLAGS, " -pipe") } + default_value 0 + description " + Enabling this option will cause the compiler to feed the + assembly output the the assembler via a pipe instead of + via a temporary file. This normally reduces the build + time." + } + + # ======================================================================== + # Package compiler options + cdl_component CYGPKG_INFRA_OPTIONS { display "Infra build options" flavor none
--- a/packages/infra/current/include/cyg_type.h +++ b/packages/infra/current/include/cyg_type.h @@ -362,6 +362,10 @@ typedef cyg_haladdrword CYG_ADDRWORD; # define CYGBLD_ATTRIB_ALIGN(__align__) __attribute__((aligned(__align__))) # endif +// Teach compiler how to check format of printf-like functions +# define CYGBLD_ATTRIB_PRINTF_FORMAT(__format__, __args__) \ + __attribute__((format (printf, __format__, __args__))) + #else // non-GNU # define CYGBLD_ATTRIB_CONSTRUCTOR @@ -381,6 +385,8 @@ typedef cyg_haladdrword CYG_ADDRWORD; # define CYGBLD_ATTRIB_ALIGN(__align__) !!!-- Alignment alias not defined --!!! +# define CYGBLD_ATTRIB_PRINTF_FORMAT(__format__, __args__) + #endif // How to define weak aliases. Currently this is simply a mixture of the
--- a/packages/io/eth/current/ChangeLog +++ b/packages/io/eth/current/ChangeLog @@ -1,3 +1,7 @@ +2002-05-28 Jonathan Larmour <jlarmour@redhat.com> + + * src/lwip/lw.diff: Remove. Obsolete. + 2002-05-13 Jesper Skov <jskov@redhat.com> * cdl/eth_drivers.cdl: Moved the package's header files to
deleted file mode 100644 --- a/packages/io/eth/current/src/lwip/lw.diff +++ /dev/null @@ -1,1466 +0,0 @@ -diff -Nur lwip-0.5.3/proj/ecos/Makefile lwip.ecos/proj/ecos/Makefile ---- lwip-0.5.3/proj/ecos/Makefile Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/proj/ecos/Makefile Tue Apr 2 18:17:49 2002 -@@ -0,0 +1,76 @@ -+CCDEP=arm-elf-gcc -+CC=arm-elf-gcc -+AR=arm-elf-ar -+#CFLAGS=-g -Wall -DIPv4 -DLWIP_DEBUG -+#CFLAGS=-Wall -DIPv4 -+CFLAGS=-g -Wall -DIPv4 -+LDFLAGS=-nostdlib -L$(ECOSLIB) -Ttarget.ld -Wl,-static -Wl,--gc-sections -finit-priority -+LWIPARCH=ecos -+ARFLAGS=rs -+LWIPDIR=../../src -+ -+ECOSDIR=/home/jani/ecos/build/lwip/edb/install -+ECOSINC=$(ECOSDIR)/include -+ECOSLIB=$(ECOSDIR)/lib -+ -+CFLAGS:=$(CFLAGS) \ -+ -I$(LWIPDIR)/include -I$(LWIPDIR)/arch/$(LWIPARCH)/include -I$(LWIPDIR)/include/ipv4 \ -+ -Iapps -I$(ECOSINC) -I. -+ -+# COREFILES, CORE4FILES: The minimum set of files needed for lwIP. -+COREFILES=$(LWIPDIR)/core/mem.c $(LWIPDIR)/core/memp.c $(LWIPDIR)/core/netif.c \ -+ $(LWIPDIR)/core/pbuf.c $(LWIPDIR)/core/stats.c $(LWIPDIR)/core/sys.c \ -+ $(LWIPDIR)/core/tcp.c $(LWIPDIR)/core/tcp_input.c \ -+ $(LWIPDIR)/core/tcp_output.c $(LWIPDIR)/core/udp.c -+CORE4FILES=$(LWIPDIR)/core/ipv4/icmp.c $(LWIPDIR)/core/ipv4/ip.c \ -+ $(LWIPDIR)/core/inet.c $(LWIPDIR)/core/ipv4/ip_addr.c -+ -+ -+# APIFILES: The files which implement the sequential and socket APIs. -+APIFILES=$(LWIPDIR)/api/api_lib.c $(LWIPDIR)/api/api_msg.c $(LWIPDIR)/api/tcpip.c \ -+ $(LWIPDIR)/api/err.c $(LWIPDIR)/api/sockets.c -+ -+# NETIFFILES: Files implementing various generic network interface functions.' -+NETIFFILES= $(LWIPDIR)/netif/arp.c -+ -+# ARCHFILES: Architecture specific files. -+ARCHFILES=$(wildcard $(LWIPDIR)/arch/$(LWIPARCH)/*.c $(LWIPDIR)/arch/$(LWIPARCH)/netif/*.c) -+ -+ -+# APPFILES: Applications. -+APPFILES=apps/tcpecho.c apps/httpd.c apps/fs.c apps/udpecho.c apps/shell.c -+ -+# LWIPFILES: All the above. -+LWIPFILES=$(COREFILES) $(CORE4FILES) $(APIFILES) $(NETIFFILES) $(ARCHFILES) -+#LWIPFILESW=$(wildcard $(LWIPFILES)) -+#LWIPOBJS=$(notdir $(LWIPFILESW:.c=.o)) -+LWIPOBJS=$(notdir $(LWIPFILES:.c=.o)) -+ -+LWIPLIB=liblwip4.a -+APPLIB=liblwipapps.a -+APPOBJS=$(notdir $(APPFILES:.c=.o)) -+ -+%.o: -+ $(CC) $(CFLAGS) -c $(<:.o=.c) -+ -+all ipv4 compile: simhost -+.PHONY: all -+ -+clean: -+ rm -f *.o $(LWIPLIB) $(APPLIB) simhost *.s .depend* *.core core -+ -+depend dep: .depend -+ -+include .depend -+ -+$(APPLIB): $(APPOBJS) -+ $(AR) $(ARFLAGS) $(APPLIB) $? -+ -+$(LWIPLIB): $(LWIPOBJS) -+ $(AR) $(ARFLAGS) $(LWIPLIB) $? -+ -+.depend: simhost.c $(LWIPFILES) $(APPFILES) -+ $(CCDEP) $(CFLAGS) -MM $^ > .depend || rm -f .depend -+ -+simhost: .depend $(LWIPLIB) $(APPLIB) simhost.o $(APPFILES) $(ECOSLIB)/libtarget.a -+ $(CC) $(CFLAGS) $(LDFLAGS) -o simhost simhost.o $(APPLIB) $(LWIPLIB) -diff -Nur lwip-0.5.3/proj/ecos/README lwip.ecos/proj/ecos/README ---- lwip-0.5.3/proj/ecos/README Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/proj/ecos/README Tue Apr 2 19:12:52 2002 -@@ -0,0 +1,21 @@ -+Building the test prog with ecos+lwip -+ -+I suppose you have a working ecos build with your target.... -+ -+There: -+ -+#ecosconfig add net_drivers -+and select lwip and unselect standalone driver and debugging -+(after patching io/eth's cdl script with ioeth.diff first to see lwIP as an option) -+and build the ecos libs as usual -+ -+ -+Here: -+ -+copy the files in unixsim/apps over here.Don't overwrite makefsdata or else the -+httpd data won't be aligned and won't work on platforms which require >1 alignment (ARM) -+ -+modify ECOSDIR in the Makefile to point to your ecos project dir -+#make -+and you should have an ecos exec with lwIP linked to it. -+ -diff -Nur lwip-0.5.3/proj/ecos/apps/makefsdata lwip.ecos/proj/ecos/apps/makefsdata ---- lwip-0.5.3/proj/ecos/apps/makefsdata Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/proj/ecos/apps/makefsdata Tue Apr 2 16:05:10 2002 -@@ -0,0 +1,70 @@ -+#!/usr/bin/perl -+ -+open(OUTPUT, "> fsdata.c"); -+ -+chdir("fs"); -+open(FILES, "find . -type f -o -name CVS -a -prune -type f |"); -+ -+while($file = <FILES>) { -+ -+ chop($file); -+ -+ open(HEADER, "> /tmp/header") || die $!; -+ print(HEADER "HTTP/1.0 200 OK\r\n"); -+ if($file =~ /\.html$/) { -+ print(HEADER "Content-Type: text/html\r\n"); -+ } elsif($file =~ /\.gif$/) { -+ print(HEADER "Content-Type: image/gif\r\n"); -+ } elsif($file =~ /\.png$/) { -+ print(HEADER "Content-Type: image/png\r\n"); -+ } elsif($file =~ /\.jpg$/) { -+ print(HEADER "Content-Type: image/jpeg\r\n"); -+ } else { -+ print(HEADER "Content-Type: text/plain\r\n"); -+ } -+ print(HEADER "\r\n"); -+ close(HEADER); -+ -+ system("cat /tmp/header $file > /tmp/file"); -+ -+ open(FILE, "/tmp/file"); -+ unlink("/tmp/file"); -+ unlink("/tmp/header"); -+ -+ $file =~ s/\.//; -+ $fvar = $file; -+ $fvar =~ s-/-_-g; -+ $fvar =~ s-\.-_-g; -+ print(OUTPUT "static const char data".$fvar."[] __attribute__ ((aligned)) = {\n"); -+ $i = 0; -+ while(read(FILE, $data, 1)) { -+ if($i == 0) { -+ print(OUTPUT "\t"); -+ } -+ printf(OUTPUT "%#02x, ", unpack("C", $data)); -+ $i++; -+ if($i == 10) { -+ print(OUTPUT "\n"); -+ $i = 0; -+ } -+ } -+ print(OUTPUT "};\n\n"); -+ close(FILE); -+ push(@fvars, $fvar); -+ push(@files, $file); -+} -+ -+for($i = 0; $i < @fvars; $i++) { -+ $file = $files[$i]; -+ $fvar = $fvars[$i]; -+ -+ if($i == 0) { -+ $prevfile = "NULL"; -+ } else { -+ $prevfile = "file" . $fvars[$i - 1]; -+ } -+ print(OUTPUT "static const struct fsdata_file file".$fvar."[] = {{$prevfile, \"$file\", "); -+ print(OUTPUT "data$fvar, sizeof(data$fvar)}};\n\n"); -+} -+ -+print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); -diff -Nur lwip-0.5.3/proj/ecos/lwipopts.h lwip.ecos/proj/ecos/lwipopts.h ---- lwip-0.5.3/proj/ecos/lwipopts.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/proj/ecos/lwipopts.h Fri Mar 29 15:05:06 2002 -@@ -0,0 +1,174 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+#ifndef __LWIPOPTS_H__ -+#define __LWIPOPTS_H__ -+ -+/* ---------- Memory options ---------- */ -+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which -+ lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 -+ byte alignment -> define MEM_ALIGNMENT to 2. */ -+#define MEM_ALIGNMENT 4 -+ -+/* MEM_SIZE: the size of the heap memory. If the application will send -+a lot of data that needs to be copied, this should be set high. */ -+#define MEM_SIZE 1000 -+ -+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application -+ sends a lot of data out of ROM (or other static memory), this -+ should be set high. */ -+#define MEMP_NUM_PBUF 8 -+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One -+ per active UDP "connection". */ -+#define MEMP_NUM_UDP_PCB 4 -+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP -+ connections. */ -+#define MEMP_NUM_TCP_PCB 5 -+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP -+ connections. */ -+#define MEMP_NUM_TCP_PCB_LISTEN 8 -+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP -+ segments. */ -+#define MEMP_NUM_TCP_SEG 8 -+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active -+ timeouts. */ -+#define MEMP_NUM_SYS_TIMEOUT 3 -+ -+ -+/* The following four are used only with the sequential API and can be -+ set to 0 if the application only will use the raw API. */ -+/* MEMP_NUM_NETBUF: the number of struct netbufs. */ -+#define MEMP_NUM_NETBUF 2 -+/* MEMP_NUM_NETCONN: the number of struct netconns. */ -+#define MEMP_NUM_NETCONN 4 -+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for -+ communication between the TCP/IP stack and the sequential -+ programs. */ -+#define MEMP_NUM_API_MSG 8 -+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used -+ for sequential API communication and incoming packets. Used in -+ src/api/tcpip.c. */ -+#define MEMP_NUM_TCPIP_MSG 8 -+ -+/* These two control is reclaimer functions should be compiled -+ in. Should always be turned on (1). */ -+#define MEM_RECLAIM 1 -+#define MEMP_RECLAIM 1 -+ -+/* ---------- Pbuf options ---------- */ -+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -+#define PBUF_POOL_SIZE 6 -+ -+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ -+#define PBUF_POOL_BUFSIZE 128 -+ -+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a -+ link level header. */ -+#define PBUF_LINK_HLEN 16 -+ -+/* ---------- TCP options ---------- */ -+#define LWIP_TCP 1 -+#define TCP_TTL 255 -+ -+/* Controls if TCP should queue segments that arrive out of -+ order. Define to 0 if your device is low on memory. */ -+#define TCP_QUEUE_OOSEQ 1 -+ -+/* TCP Maximum segment size. */ -+#define TCP_MSS 128 -+ -+/* TCP sender buffer space (bytes). */ -+#define TCP_SND_BUF 256 -+ -+/* TCP sender buffer space (pbufs). This must be at least = 2 * -+ TCP_SND_BUF/TCP_MSS for things to work. */ -+#define TCP_SND_QUEUELEN 4 * TCP_SND_BUF/TCP_MSS -+ -+/* TCP receive window. */ -+#define TCP_WND 1024 -+ -+/* Maximum number of retransmissions of data segments. */ -+#define TCP_MAXRTX 12 -+ -+/* Maximum number of retransmissions of SYN segments. */ -+#define TCP_SYNMAXRTX 4 -+ -+/* ---------- ARP options ---------- */ -+#define ARP_TABLE_SIZE 10 -+ -+/* ---------- IP options ---------- */ -+/* Define IP_FORWARD to 1 if you wish to have the ability to forward -+ IP packets across network interfaces. If you are going to run lwIP -+ on a device with only one network interface, define this to 0. */ -+#define IP_FORWARD 1 -+ -+/* If defined to 1, IP options are allowed (but not parsed). If -+ defined to 0, all packets with IP options are dropped. */ -+#define IP_OPTIONS 1 -+ -+/* ---------- ICMP options ---------- */ -+#define ICMP_TTL 255 -+ -+ -+/* ---------- DHCP options ---------- */ -+/* Define LWIP_DHCP to 1 if you want DHCP configuration of -+ interfaces. DHCP is not implemented in lwIP 0.5.1, however, so -+ turning this on does currently not work. */ -+#define LWIP_DHCP 0 -+ -+/* 1 if you want to do an ARP check on the offered address -+ (recommended). */ -+#define DHCP_DOES_ARP_CHECK 1 -+ -+/* ---------- UDP options ---------- */ -+#define LWIP_UDP 1 -+#define UDP_TTL 255 -+ -+ -+/* ---------- Statistics options ---------- */ -+#define STATS -+ -+#ifdef STATS -+#define LINK_STATS -+#define IP_STATS -+#define ICMP_STATS -+#define UDP_STATS -+#define TCP_STATS -+#define MEM_STATS -+#define MEMP_STATS -+#define PBUF_STATS -+#define SYS_STATS -+#endif /* STATS */ -+ -+#endif /* __LWIPOPTS_H__ */ -diff -Nur lwip-0.5.3/proj/ecos/simhost.c lwip.ecos/proj/ecos/simhost.c ---- lwip-0.5.3/proj/ecos/simhost.c Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/proj/ecos/simhost.c Fri Mar 29 14:45:33 2002 -@@ -0,0 +1,141 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+ -+#include "lwip/debug.h" -+ -+#include <unistd.h> -+ -+#include "lwip/opt.h" -+ -+#include "lwip/mem.h" -+#include "lwip/memp.h" -+#include "lwip/sys.h" -+ -+#include "lwip/stats.h" -+ -+#include "netif/ecosif.h" -+//#include "netif/loopif.h" -+ -+#include "lwip/tcpip.h" -+ -+#include "lwip/ip_addr.h" -+ -+#include "arch/perf.h" -+ -+#include "httpd.h" -+#include "tcpecho.h" -+#include "udpecho.h" -+#include "shell.h" -+ -+/*-----------------------------------------------------------------------------------*/ -+static void -+tcp_timeout(void *data) -+{ -+#if TCP_DEBUG -+ tcp_debug_print_pcbs(); -+#endif /* TCP_DEBUG */ -+ sys_timeout(5000, tcp_timeout, NULL); -+} -+/*-----------------------------------------------------------------------------------*/ -+static void -+tcpip_init_done(void *arg) -+{ -+ sys_sem_t *sem; -+ sem = arg; -+ sys_sem_signal(*sem); -+} -+/*-----------------------------------------------------------------------------------*/ -+static void -+main_thread(void *arg) -+{ -+ struct ip_addr ipaddr, netmask, gw; -+ sys_sem_t sem; -+ netif_init(); -+ -+ sem = sys_sem_new(0); -+ tcpip_init(tcpip_init_done, &sem); -+ sys_sem_wait(sem); -+ sys_sem_free(sem); -+ printf("TCP/IP initialized.\n"); -+ -+ IP4_ADDR(&gw, 192,168,1,1); -+ IP4_ADDR(&ipaddr, 192,168,1,99); -+ IP4_ADDR(&netmask, 255,255,255,0); -+ -+ netif_set_default(netif_add(&ipaddr, &netmask, &gw, ecosif_init, tcpip_input)); -+ IP4_ADDR(&gw, 127,0,0,1); -+ IP4_ADDR(&ipaddr, 127,0,0,1); -+ IP4_ADDR(&netmask, 255,0,0,0); -+ -+// netif_add(&ipaddr, &netmask, &gw, loopif_init, tcpip_input); -+// udpecho_init(); -+// shell_init(); -+// tcpecho_init(); -+ httpd_init(); -+ printf("Applications started.\n"); -+ /* Block for ever. */ -+ sem = sys_sem_new(0); -+ sys_sem_wait(sem); -+} -+/*-----------------------------------------------------------------------------------*/ -+int -+main(int argc, char **argv) -+{ -+#ifdef STATS -+ stats_init(); -+#endif /* STATS */ -+ sys_init(); -+ mem_init(); -+ memp_init(); -+ pbuf_init(); -+ -+ -+ -+ printf("System initialized.\n"); -+ -+ sys_thread_new((void *)(main_thread), (void*)"simhost"); -+ while(1) -+ {cyg_thread_delay(1000);} -+ return 0; -+} -+/*-----------------------------------------------------------------------------------*/ -+ -+ -+ -+ -+ -+ -+ -+ -diff -Nur lwip-0.5.3/src/arch/ecos/README lwip.ecos/src/arch/ecos/README ---- lwip-0.5.3/src/arch/ecos/README Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/README Tue Apr 2 19:17:23 2002 -@@ -0,0 +1,47 @@ -+eCos port of lwIP -+====================== -+ -+Introduction -+------------- -+This is a beta version of the lwIP port to eCos.It was tested on a Cirrus Logic -+EDB72111 board with ARM and it responds to ping and runs the unixsim apps(http,tcpecho,shell,etc) -+The motivation behind it is that the current TCP stack in eCos is too large both -+as code size and as memory footprint for a board with 128K FLASH + 128K RAM. -+BTW this port is just working it still need optimization. -+ -+Description -+------------ -+ -+The port consists of 3 main parts -+ -+I) the eCos specific sys_arch implemetation -+- src/arch/ecos/sys_arch.c -+- sys/arch/ecos/include/.... -+This maps lwIP semaphores, mailboxes and threads to their eCos counterparts -+along with the required header files defining endianness and primitive data types -+ -+II) the interface to the hw network drivers -+- io/eth/lwip/eth_drv.c in the eCos repository -+This part consists of a hardware independent net driver which glues eCos -+low-level ethernet drivers to the lwIP stack (modeled after the two such drivers -+existing in eCos : the standalone for RedBoot and the other one for the BSD stack) -+This driver implements the 3 callbacks needed by hw specific drivers. -+It currently uses the polling model like the standalone driver and not interrupts. -+This makes the whole thing less intrusive -+ -+III) the eCos specific lwIP netif -+- src/arch/ecos/netif/ecosif.c -+This file implements the lwIP netif model with init/input/output functions.This -+calls into and is called from eth_drv.c described above -+ -+Usage -+------- -+ -+The way to build an eCos app with lwIP is to just link the lwIP libs to your app and then -+the whole thing to libtarget.a from eCos as usual.So this way lwIP is more like part of you app -+than part of eCos.For an example of Makefile see the one in proj/ecos heavily based on -+unixim/ecos from the lwip distribution. -+ -+The organisation should change.Ideally there would be an eCos package -+to simply add to your project and configure just like any other package. -+ -diff -Nur lwip-0.5.3/src/arch/ecos/include/arch/cc.h lwip.ecos/src/arch/ecos/include/arch/cc.h ---- lwip-0.5.3/src/arch/ecos/include/arch/cc.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/include/arch/cc.h Thu Mar 14 23:23:00 2002 -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+#ifndef __ARCH_CC_H__ -+#define __ARCH_CC_H__ -+ -+typedef unsigned char u8_t; -+typedef signed char s8_t; -+typedef unsigned short u16_t; -+typedef signed short s16_t; -+typedef unsigned long u32_t; -+typedef signed long s32_t; -+ -+ -+#define PACK_STRUCT_FIELD(x) x __attribute__((packed)) -+#define PACK_STRUCT_STRUCT __attribute__((packed)) -+#define PACK_STRUCT_BEGIN -+#define PACK_STRUCT_END -+ -+#endif /* __ARCH_CC_H__ */ -diff -Nur lwip-0.5.3/src/arch/ecos/include/arch/cpu.h lwip.ecos/src/arch/ecos/include/arch/cpu.h ---- lwip-0.5.3/src/arch/ecos/include/arch/cpu.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/include/arch/cpu.h Fri Mar 15 22:08:00 2002 -@@ -0,0 +1,44 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+#ifndef __ARCH_CPU_H__ -+#define __ARCH_CPU_H__ -+ -+#if (CYG_BYTEORDER == CYG_LSBFIRST) -+#define BYTE_ORDER LITTLE_ENDIAN -+#else -+#define BYTE_ORDER BIG_ENDIAN -+#endif -+ -+#endif /* __ARCH_CPU_H__ */ -diff -Nur lwip-0.5.3/src/arch/ecos/include/arch/init.h lwip.ecos/src/arch/ecos/include/arch/init.h ---- lwip-0.5.3/src/arch/ecos/include/arch/init.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/include/arch/init.h Wed Dec 12 00:00:00 2001 -@@ -0,0 +1,44 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+#ifndef __ARCH_INIT_H__ -+#define __ARCH_INIT_H__ -+ -+#define TCPIP_INIT_DONE(arg) sys_sem_signal(*(sys_sem_t *)arg) -+ -+#endif /* __ARCH_INIT_H__ */ -+ -+ -+ -+ -diff -Nur lwip-0.5.3/src/arch/ecos/include/arch/lib.h lwip.ecos/src/arch/ecos/include/arch/lib.h ---- lwip-0.5.3/src/arch/ecos/include/arch/lib.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/include/arch/lib.h Thu Mar 14 23:27:00 2002 -@@ -0,0 +1,38 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+#ifndef __ARCH_LIB_H__ -+#define __ARCH_LIB_H__ -+ -+#endif /* __ARCH_LIB_H__ */ -diff -Nur lwip-0.5.3/src/arch/ecos/include/arch/perf.h lwip.ecos/src/arch/ecos/include/arch/perf.h ---- lwip-0.5.3/src/arch/ecos/include/arch/perf.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/include/arch/perf.h Wed Dec 12 00:00:00 2001 -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+#ifndef __PERF_H__ -+#define __PERF_H__ -+ -+#define PERF_START /* null definition */ -+#define PERF_STOP(x) /* null definition */ -+ -+#endif /* __PERF_H__ */ -diff -Nur lwip-0.5.3/src/arch/ecos/include/arch/sys_arch.h lwip.ecos/src/arch/ecos/include/arch/sys_arch.h ---- lwip-0.5.3/src/arch/ecos/include/arch/sys_arch.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/include/arch/sys_arch.h Thu Mar 14 23:53:00 2002 -@@ -0,0 +1,13 @@ -+#ifndef __SYS_ECOS_H__ -+#define __SYS_ECOS_H__ -+ -+#include <cyg/kernel/kapi.h> -+ -+#define SYS_MBOX_NULL (sys_mbox_t)NULL -+#define SYS_SEM_NULL (sys_sem_t)NULL -+ -+typedef cyg_sem_t * sys_sem_t; -+typedef cyg_handle_t sys_mbox_t; -+typedef cyg_thread * sys_thread_t; -+#endif /* __SYS_ECOS_H__ */ -+ -diff -Nur lwip-0.5.3/src/arch/ecos/include/netif/ecosif.h lwip.ecos/src/arch/ecos/include/netif/ecosif.h ---- lwip-0.5.3/src/arch/ecos/include/netif/ecosif.h Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/include/netif/ecosif.h Tue Mar 19 23:38:00 2002 -@@ -0,0 +1,42 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+#ifndef __ECOSIF_H__ -+#define __ECOSIF_H__ -+ -+#include "lwip/netif.h" -+ -+void ecosif_init(struct netif *netif); -+ -+#endif /* __ECOSIF_H__ */ -diff -Nur lwip-0.5.3/src/arch/ecos/lib_arch.c lwip.ecos/src/arch/ecos/lib_arch.c ---- lwip-0.5.3/src/arch/ecos/lib_arch.c Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/lib_arch.c Wed Dec 12 00:00:00 2001 -@@ -0,0 +1,92 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+ -+/* These are generic implementations of various library functions used -+ * throughout the lwIP code. When porting, those should be optimized -+ * for the particular processor architecture, preferably coded in -+ * assembler. -+ */ -+ -+#include "lwip/arch.h" -+ -+u16_t -+htons(u16_t n) -+{ -+ return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); -+} -+/*-----------------------------------------------------------------------------------*/ -+u16_t -+ntohs(u16_t n) -+{ -+ return htons(n); -+} -+/*-----------------------------------------------------------------------------------*/ -+u32_t -+htonl(u32_t n) -+{ -+ return ((n & 0xff) << 24) | -+ ((n & 0xff00) << 8) | -+ ((n & 0xff0000) >> 8) | -+ ((n & 0xff000000) >> 24); -+} -+/*-----------------------------------------------------------------------------------*/ -+u32_t -+ntohl(u32_t n) -+{ -+ return htonl(n); -+} -+/*-----------------------------------------------------------------------------------*/ -+void -+bcopy(const void *src, void *dst, unsigned int size) -+{ -+ char *csrc, *cdst; -+ unsigned int i; -+ -+ csrc = (char *)src; -+ cdst = dst; -+ -+ for(i = 0; i < size; ++i) { -+ cdst[i] = csrc[i]; -+ } -+} -+/*-----------------------------------------------------------------------------------*/ -+void -+bzero(void *s, int n) -+{ -+ for(--n ;n >= 0; --n) { -+ ((char *)s)[n] = 0; -+ } -+} -+/*-----------------------------------------------------------------------------------*/ -diff -Nur lwip-0.5.3/src/arch/ecos/netif/ecosif.c lwip.ecos/src/arch/ecos/netif/ecosif.c ---- lwip-0.5.3/src/arch/ecos/netif/ecosif.c Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/netif/ecosif.c Tue Apr 2 16:13:46 2002 -@@ -0,0 +1,327 @@ -+/* -+ * Copyright (c) 2001, Swedish Institute of Computer Science. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the Institute nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * This file is part of the lwIP TCP/IP stack. -+ * -+ * Author: Adam Dunkels <adam@sics.se> -+ * -+ * $Id: lw.diff,v 1.2 2002/05/23 23:06:02 jlarmour Exp $ -+ */ -+ -+#include "lwip/debug.h" -+ -+#include "lwip/opt.h" -+#include "lwip/def.h" -+#include "lwip/ip.h" -+#include "lwip/mem.h" -+#include "lwip/pbuf.h" -+#include "lwip/sys.h" -+ -+#include "netif/arp.h" -+ -+ -+#define IFNAME0 'c' -+#define IFNAME1 'y' -+ -+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; -+ -+struct ecosif { -+ struct eth_addr *ethaddr; -+ /* Add whatever per-interface state that is needed here. */ -+}; -+ -+static struct netif *this_netif; -+ -+/* Forward declarations. */ -+static void ecosif_input(struct netif *netif, char*buf, int len); -+static err_t ecosif_output(struct netif *netif, struct pbuf *p, -+ struct ip_addr *ipaddr); -+ -+/* Entry points in the eCos hw independent driver */ -+extern void eth_drv_write(char *, char *, int); -+extern void init_hw_drivers(unsigned char *hw_addr,void (*pig)(char *,int)); -+ -+/* -+ * This is called from eCos when data is read from the driver -+ */ -+void lwip_input(char *buf, int len) -+{ -+ ecosif_input((struct netif*)this_netif,buf,len); -+} -+ -+ -+extern void input_thread(void *arg); -+ -+static void -+low_level_init(struct netif *netif) -+{ -+ struct ecosif *ecosif; -+ -+ ecosif = netif->state; -+ -+ /* Init eCos low level driver which sets MAC address */ -+ init_hw_drivers((unsigned char *)ecosif->ethaddr->addr,lwip_input); -+ printf("MAC address : %X:%X:%X:%X:%X:%X\n", -+ (unsigned char)(ecosif->ethaddr->addr[0]), -+ (unsigned char)(ecosif->ethaddr->addr[1]), -+ (unsigned char)(ecosif->ethaddr->addr[2]), -+ (unsigned char)(ecosif->ethaddr->addr[3]), -+ (unsigned char)(ecosif->ethaddr->addr[4]), -+ (unsigned char)(ecosif->ethaddr->addr[5])); -+ sys_thread_new(input_thread,(void*)"poll_thread"); -+} -+/* -+ * low_level_output(): -+ * -+ * Should do the actual transmission of the packet. The packet is -+ * contained in the pbuf that is passed to the function. This pbuf -+ * might be chained.We pass the data down to the eCos hw independent -+ * ethernet driver -+ */ -+ -+static err_t -+low_level_output(struct ecosif *ecosif, struct pbuf *p) -+{ -+ struct pbuf *q; -+ char buf[1500]; -+ char *bufptr; -+ -+ /* initiate transfer(); */ -+ bufptr = &buf[0]; -+ -+ for(q = p; q != NULL; q = q->next) { -+ /* Send the data from the pbuf to the interface, one pbuf at a -+ time. The size of the data in each pbuf is kept in the ->len -+ variable. */ -+ /* send data from(q->payload, q->len); */ -+ bcopy(q->payload, bufptr, q->len); -+ bufptr += q->len; -+ } -+ -+ /* signal that packet should be sent(); */ -+ eth_drv_write(NULL, buf, p->tot_len); -+ return ERR_OK; -+} -+/*-----------------------------------------------------------------------------------*/ -+/* -+ * ecosif_output(): -+ * -+ * This function is called by the TCP/IP stack when an IP packet -+ * should be sent. It calls the function called low_level_output() to -+ * do the actuall transmission of the packet. -+ * -+ */ -+/*-----------------------------------------------------------------------------------*/ -+static err_t -+ecosif_output(struct netif *netif, struct pbuf *p, -+ struct ip_addr *ipaddr) -+{ -+ struct ecosif *ecosif; -+ struct pbuf *q; -+ struct eth_hdr *ethhdr; -+ struct eth_addr *dest, mcastaddr; -+ struct ip_addr *queryaddr; -+ err_t err; -+ u8_t i; -+ -+ ecosif = netif->state; -+ -+ /* Make room for Ethernet header. */ -+ if(pbuf_header(p, sizeof(struct eth_hdr)) != 0) { -+ /* The pbuf_header() call shouldn't fail, but we allocate an extra -+ pbuf just in case. */ -+ q = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr), PBUF_RAM); -+ if(q == NULL) { -+ return ERR_MEM; -+ } -+ pbuf_chain(q, p); -+ p = q; -+ } -+ -+ /* Construct Ethernet header. Start with looking up deciding which -+ MAC address to use as a destination address. Broadcasts and -+ multicasts are special, all other addresses are looked up in the -+ ARP table. */ -+ queryaddr = ipaddr; -+ if(ip_addr_isany(ipaddr) || -+ ip_addr_isbroadcast(ipaddr, &(netif->netmask))) { -+ dest = (struct eth_addr *)ðbroadcast; -+ } else if(ip_addr_ismulticast(ipaddr)) { -+ /* Hash IP multicast address to MAC address. */ -+ mcastaddr.addr[0] = 0x01; -+ mcastaddr.addr[1] = 0x0; -+ mcastaddr.addr[2] = 0x5e; -+ mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; -+ mcastaddr.addr[4] = ip4_addr3(ipaddr); -+ mcastaddr.addr[5] = ip4_addr4(ipaddr); -+ dest = &mcastaddr; -+ } else { -+ if(ip_addr_maskcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) { -+ /* Use destination IP address if the destination is on the same -+ subnet as we are. */ -+ queryaddr = ipaddr; -+ } else { -+ /* Otherwise we use the default router as the address to send -+ the Ethernet frame to. */ -+ queryaddr = &(netif->gw); -+ } -+ dest = arp_lookup(queryaddr); -+ } -+ -+ -+ /* If the arp_lookup() didn't find an address, we send out an ARP -+ query for the IP address. */ -+ if(dest == NULL) { -+ q = arp_query(netif, ecosif->ethaddr, queryaddr); -+ if(q != NULL) { -+ printf("Sending ARP after query\n"); -+ err = low_level_output(ecosif, q); -+ pbuf_free(q); -+ return err; -+ } -+ return ERR_MEM; -+ } -+ ethhdr = p->payload; -+ -+ for(i = 0; i < 6; i++) { -+ ethhdr->dest.addr[i] = dest->addr[i]; -+ ethhdr->src.addr[i] = ecosif->ethaddr->addr[i]; -+ } -+ -+ ethhdr->type = htons(ETHTYPE_IP); -+ -+ return low_level_output(ecosif, p); -+ -+} -+ -+ -+ -+/* -+ * ecosif_input(): -+ * This function is called when the eCos hw independent driver -+ * has some data to pass up to lwIP.It does it through lwip_input. -+ */ -+ -+static void -+ecosif_input(struct netif *netif, char * bufptr, int len) -+{ -+ struct ecosif *ecosif; -+ struct eth_hdr *ethhdr; -+ struct pbuf *p, *q; -+ -+ ecosif = netif->state; -+ /* We allocate a pbuf chain of pbufs from the pool. */ -+ p = pbuf_alloc(PBUF_LINK, len, PBUF_POOL); -+ -+ if(p != NULL) { -+ /* We iterate over the pbuf chain until we have read the entire -+ packet into the pbuf. */ -+ for(q = p; q != NULL; q = q->next) { -+ /* Read enough bytes to fill this pbuf in the chain. The -+ avaliable data in the pbuf is given by the q->len -+ variable. */ -+ /* read data into(q->payload, q->len); */ -+ bcopy(bufptr, q->payload, q->len); -+ bufptr += q->len; -+ } -+ /* acknowledge that packet has been read(); */ -+ } else { -+ /* drop packet(); */ -+ } -+ -+ if(p == NULL) { -+ DEBUGF(ECOSIF_DEBUG, ("ecosif_input: low_level_input returned NULL\n")); -+ return; -+ } -+ ethhdr = p->payload; -+ -+ switch(htons(ethhdr->type)) { -+ case ETHTYPE_IP: -+ DEBUGF(ECOSIF_DEBUG, ("ecosif_input: IP packet\n")); -+ arp_ip_input(netif, p); -+ pbuf_header(p, -14); -+#if LWIP_DEBUG -+ if(ip_lookup(p->payload, netif)) { -+#endif -+ netif->input(p, netif); -+#if LWIP_DEBUG -+ } else { -+ printf("ecosif_input: lookup failed!\n"); -+ } -+#endif -+ break; -+ case ETHTYPE_ARP: -+ DEBUGF(ECOSIF_DEBUG, ("ecosif_input: ARP packet\n")); -+ p = arp_arp_input(netif, ecosif->ethaddr, p); -+ if(p != NULL) { -+ DEBUGF(ECOSIF_DEBUG, ("ecosif_input: Sending ARP reply\n")); -+ low_level_output(ecosif, p); -+ pbuf_free(p); -+ } -+ break; -+ default: -+ pbuf_free(p); -+ break; -+ } -+} -+/*-----------------------------------------------------------------------------------*/ -+static void -+arp_timer(void *arg) -+{ -+ arp_tmr(); -+ sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler)arp_timer, NULL); -+} -+/*-----------------------------------------------------------------------------------*/ -+/* -+ * ecosif_init(): -+ * -+ * Should be called at the beginning of the program to set up the -+ * network interface. It calls the function low_level_init() to do the -+ * actual setup of the hardware. -+ * -+ */ -+/*-----------------------------------------------------------------------------------*/ -+void -+ecosif_init(struct netif *netif) -+{ -+ struct ecosif *ecosif; -+ -+ this_netif = netif; -+ ecosif = mem_malloc(sizeof(struct ecosif)); -+ netif->state = ecosif; -+ netif->name[0] = IFNAME0; -+ netif->name[1] = IFNAME1; -+ netif->output = ecosif_output; -+ -+ ecosif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); -+ low_level_init(netif); -+ arp_init(); -+ -+ sys_timeout(ARP_TMR_INTERVAL, (sys_timeout_handler)arp_timer, NULL); -+} -+/*-----------------------------------------------------------------------------------*/ -diff -Nur lwip-0.5.3/src/arch/ecos/sys_arch.c lwip.ecos/src/arch/ecos/sys_arch.c ---- lwip-0.5.3/src/arch/ecos/sys_arch.c Thu Jan 1 02:00:00 1970 -+++ lwip.ecos/src/arch/ecos/sys_arch.c Tue Apr 2 19:05:58 2002 -@@ -0,0 +1,181 @@ -+/* -+ * This file implements the eCos specific sys_arch functions used by lwIP -+ */ -+ -+#include <cyg/kernel/kapi.h> -+ -+#include "lwip/sys.h" -+#include "lwip/def.h" -+#include "lwip/debug.h" -+ -+//FIXME use CYG_HWR_whatever for RTC -+ -+/* lwIp timeouts are milliseconds, eCos time unit is clock tick */ -+//1s = 1000ms = 100ticks (eCos default is 100 tick per second for most(all?) platforms) -+#define tick_to_msec(tick) ((u16_t)(tick*10+1)) -+#define msec_to_tick(msec) ((cyg_tick_count_t)(msec+9)/10) -+ -+/* We use a common var mempool for allocating semaphores, mboxes and threads... */ -+#define VARMEMPOOLSIZE 0x4000 /* tunable */ -+static char memvar[VARMEMPOOLSIZE]; -+static cyg_mempool_var var_mempool; -+static cyg_handle_t var_mempool_h; -+ -+/* ...and a fix mempool for allocating thread stacks */ -+ -+#define LWIP_THREAD_STACK_SIZE 0x2000 /* tunable */ -+#define MAX_THREADS 4 /* tunable */ -+ -+static char memfix[LWIP_THREAD_STACK_SIZE * MAX_THREADS]; -+static cyg_mempool_fix fix_mempool; -+static cyg_handle_t fix_mempool_h; -+ -+/* List of threads: associate eCos thread info with lwIP timeout info */ -+struct lwip_thread { -+ struct lwip_thread * next; -+ struct sys_timeouts to; -+ cyg_handle_t th; -+ cyg_thread t; -+} *threads; -+ -+/*FIXME: the timeout struct used for non-lwIP threads -eCos -+ * there might be threads which are not created through -+ * sys_thread_new but access lwIP stuff (i.e. net interrupt) -+ * This must go away. -+ * */ -+struct sys_timeouts global_timeout; -+ -+/* Set up memory pools and threads*/ -+void sys_init(void) -+{ -+ cyg_mempool_var_create(memvar, sizeof(memvar), &var_mempool_h, &var_mempool); -+ -+ cyg_mempool_fix_create(memfix, sizeof(memfix), -+ LWIP_THREAD_STACK_SIZE, &fix_mempool_h, &fix_mempool); -+ threads = NULL; -+ global_timeout.next = NULL; -+} -+ -+/* Message boxes */ -+ -+sys_mbox_t sys_mbox_new(void) -+{ -+ cyg_mbox * mbox; -+ cyg_handle_t m; -+ mbox = (cyg_mbox *)cyg_mempool_var_alloc(var_mempool_h, sizeof(cyg_mbox)); -+ cyg_mbox_create(&m, mbox); -+ return m; -+} -+ -+void sys_mbox_free(sys_mbox_t mbox) -+{ -+ cyg_mbox_delete(mbox); -+} -+ -+//FIXME returns false maybe retry? -+void sys_mbox_post(sys_mbox_t mbox, void *data) -+{ -+#if 0 -+ if (cyg_mbox_put(mbox, data)==false) -+ printf("AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAaaa\n"); -+#endif -+ cyg_mbox_put(mbox,data); -+} -+ -+u16_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **data, u16_t timeout) -+{ -+ void *d; -+ cyg_tick_count_t end_time, start_time,lool; -+ static int pig = 0; -+ if (timeout) { -+ start_time = cyg_current_time(); -+ lool = start_time + msec_to_tick(timeout); -+ d = cyg_mbox_timed_get(mbox, lool); -+ end_time = cyg_current_time(); -+ -+ if (d == NULL) -+ return 0; -+ } else { -+ d = cyg_mbox_get(mbox); -+ } -+ *data = d; -+ return tick_to_msec(end_time - start_time); -+} -+ -+/* Semaphores */ -+ -+sys_sem_t sys_sem_new(u8_t count) -+{ -+ sys_sem_t sem; -+ -+ sem = (cyg_sem_t *)cyg_mempool_var_alloc(var_mempool_h, sizeof(cyg_sem_t)); -+ cyg_semaphore_init(sem, count); -+ return sem; -+} -+ -+u16_t sys_arch_sem_wait(sys_sem_t sem, u16_t timeout) -+{ -+ cyg_bool_t r; -+ cyg_tick_count_t end_time, start_time; -+ -+ if (timeout) { -+ start_time = cyg_current_time(); -+ r = cyg_semaphore_timed_wait(sem, start_time + msec_to_tick(timeout)); -+ end_time = cyg_current_time(); -+ -+ if (r == false) -+ return 0; -+ } else { -+ cyg_semaphore_wait(sem); -+ } -+ -+ return tick_to_msec(end_time - start_time); -+} -+ -+void sys_sem_signal(sys_sem_t sem) -+{ -+ cyg_semaphore_post(sem); -+} -+ -+void sys_sem_free(sys_sem_t sem) -+{ -+ cyg_semaphore_destroy(sem); -+} -+ -+/* Thread creation */ -+ -+void sys_thread_new(void (*function) (void *arg), void *arg) -+{ -+ struct lwip_thread * nt; -+ void * stack; -+ -+ nt = (struct lwip_thread *)cyg_mempool_var_alloc(var_mempool_h, sizeof(struct lwip_thread)); -+ -+ nt->next = threads; -+ nt->to.next = NULL; -+ -+ threads = nt; -+ -+ stack = cyg_mempool_fix_alloc(fix_mempool_h); -+ -+ cyg_thread_create(12, (cyg_thread_entry_t *)function, (cyg_addrword_t)arg, -+ (char *)arg , stack, LWIP_THREAD_STACK_SIZE, &(nt->th), &(nt->t) ); -+ -+ cyg_thread_resume(nt->th); -+} -+ -+/* Find current thread's timeout info */ -+ -+struct sys_timeouts *sys_arch_timeouts(void) -+{ -+ cyg_handle_t ct; -+ struct lwip_thread *t; -+ -+ ct = cyg_thread_self(); -+ for(t = threads; t; t = t->next) -+ if (t->th == ct) -+ return &(t->to); -+ -+ printf("tmobad@@@@@\n"); -+ return &global_timeout; -+}
--- a/packages/io/fileio/current/ChangeLog +++ b/packages/io/fileio/current/ChangeLog @@ -1,3 +1,13 @@ +2002-05-29 Jesper Skov <jskov@redhat.com> + + * tests/fileio1.c: Removed strcat definition. Rely on string.h to + provide it. + +2002-05-28 Jonathan Larmour <jlarmour@redhat.com> + + * include/limits.h (NAME_MAX): Increase default to 64. + * cdl/fileio.cdl: Set CYGBLD_ISO_NAME_MAX_HEADER. + 2002-04-11 Nick Garnett <nickg@redhat.com> * doc/fileio.sgml: Added a section on writing a new
--- a/packages/io/fileio/current/cdl/fileio.cdl +++ b/packages/io/fileio/current/cdl/fileio.cdl @@ -66,6 +66,7 @@ cdl_package CYGPKG_IO_FILEIO { requires { CYGBLD_ISO_DIRENT_HEADER == "<cyg/fileio/dirent.h>" } requires { CYGBLD_ISO_OPEN_MAX_HEADER == "<cyg/fileio/limits.h>" } + requires { CYGBLD_ISO_NAME_MAX_HEADER == "<cyg/fileio/limits.h>" } compile fd.cxx file.cxx io.cxx dir.cxx compile -library=libextras.a misc.cxx
--- a/packages/io/fileio/current/include/limits.h +++ b/packages/io/fileio/current/include/limits.h @@ -57,7 +57,10 @@ #include <pkgconf/io_fileio.h> -#define OPEN_MAX CYGNUM_FILEIO_NFILE +#ifndef __STRICT_ANSI__ +# define NAME_MAX 64 +# define OPEN_MAX CYGNUM_FILEIO_NFILE +#endif /*--------------------------------------------------------------------------*/ #endif /* ifndef CYGONCE_IO_FILEIO_LIMITS_H */
--- a/packages/io/fileio/current/tests/fileio1.c +++ b/packages/io/fileio/current/tests/fileio1.c @@ -92,16 +92,6 @@ diag_printf("<INFO>: " #_fn "() returned //========================================================================== -static char *strcat( char *s1, const char *s2 ) -{ - char *s = s1; - while( *s1 ) s1++; - while( (*s1++ = *s2++) != 0); - return s; -} - -//========================================================================== - static void listdir( char *name, int statp ) { int err;
--- a/packages/kernel/current/ChangeLog +++ b/packages/kernel/current/ChangeLog @@ -1,3 +1,7 @@ +2002-05-24 Jesper Skov <jskov@redhat.com> + + * cdl/kernel.cdl: Fix typo. + 2002-05-23 Jonathan Larmour <jlarmour@redhat.com> * include/kapi.h: Expose new cyg_thread_add_destructor and
--- a/packages/kernel/current/cdl/kernel.cdl +++ b/packages/kernel/current/cdl/kernel.cdl @@ -328,7 +328,7 @@ cdl_package CYGPKG_KERNEL { no_define calculated { "tests/bin_sem0 tests/bin_sem1 tests/bin_sem2 tests/clock0 tests/clock1 tests/clockcnv tests/clocktruth tests/cnt_sem0 tests/cnt_sem1 tests/except1 tests/flag0 tests/flag1 tests/intr0 tests/kill tests/mbox1 tests/mqueue1 tests/mutex0 tests/mutex1 tests/mutex2 tests/mutex3 tests/release tests/sched1 tests/sync2 tests/sync3 tests/thread0 tests/thread1 tests/thread2" - . ((CYGFUN_KERNEL_API_C) ? "tests/kclock0 tests/kclock1 tests/kexcept1 tests/kflag0 tests/kflag1 tests/kintr0 tests/klock tests/kmbox1 tests/kmutex0 tests/kmutex1 tests/kmutex3 tests/kmutex4 tests/ksched1 tests/ksem0 tests/ksem1 tests/kthread0 tests/kthread1 tests/stress_threads tests/thread_gdb tests/timeslice tests/tm_basic" : "") + . ((CYGFUN_KERNEL_API_C) ? " tests/kclock0 tests/kclock1 tests/kexcept1 tests/kflag0 tests/kflag1 tests/kintr0 tests/klock tests/kmbox1 tests/kmutex0 tests/kmutex1 tests/kmutex3 tests/kmutex4 tests/ksched1 tests/ksem0 tests/ksem1 tests/kthread0 tests/kthread1 tests/stress_threads tests/thread_gdb tests/timeslice tests/tm_basic" : "") . ((!CYGPKG_INFRA_DEBUG && !CYGPKG_KERNEL_INSTRUMENT && CYGFUN_KERNEL_API_C) ? " tests/dhrystone" : "") . ((CYGPKG_KERNEL_SMP_SUPPORT && CYGFUN_KERNEL_API_C) ? " tests/smp" : "") . ((!CYGINT_HAL_TESTS_NO_CACHES && CYGFUN_KERNEL_API_C) ? " tests/kcache1 tests/kcache2" : "")
--- a/packages/language/c/libc/stdio/current/ChangeLog +++ b/packages/language/c/libc/stdio/current/ChangeLog @@ -1,3 +1,10 @@ +2002-05-17 Martin Buck <martin.buck@ascom.ch> + + * include/stdio.h (fnprintf): Added printf-format-checking using + CYGBLD_ATTRIB_PRINTF_FORMAT, since gcc does it automatically only for + ISO C90 functions. + (snprintf) Likewise. + 2002-04-24 Yoshinori Sato <qzb04471@nifty.ne.jp> * include/streambuf.inl (Cyg_StdioStreamBuffer constructor):
--- a/packages/language/c/libc/stdio/current/include/stdio.h +++ b/packages/language/c/libc/stdio/current/include/stdio.h @@ -271,11 +271,11 @@ perror( const char * /* prefix_str */ ); externC int fnprintf( FILE * /* stream */, size_t /* length */, - const char * /* format */, ... ); + const char * /* format */, ... ) CYGBLD_ATTRIB_PRINTF_FORMAT(3, 4); externC int snprintf( char * /* str */, size_t /* length */, const char * /* format */, - ... ); + ... ) CYGBLD_ATTRIB_PRINTF_FORMAT(3, 4); externC int vfnprintf( FILE * /* stream */, size_t /* length */,
--- a/packages/net/common/current/ChangeLog +++ b/packages/net/common/current/ChangeLog @@ -1,3 +1,19 @@ +2002-05-28 Jonathan Larmour <jlarmour@redhat.com> + + * src/dhcp_prot.c (do_dhcp): xmit2 need not be static. + +2002-05-27 Gary Thomas <gthomas@redhat.com> + + * src/dhcp_prot.c (do_dhcp): Suppress my_ip and server_ip fields + in all messages where they should not be set. Also be more careful + about size of messages as they are copied. + +2002-05-24 Gary Thomas <gthomas@redhat.com> + + * src/dhcp_prot.c (do_dhcp): Suppress my_ip and server_ip fields + when returning DHCP request (acceptance phase) because some DHCP + servers insist (and the RFC says it must be this way). + 2002-05-21 Jesper Skov <jskov@redhat.com> * include/net/netdb.h: Include netinet/in.h for the in_addr use in
--- a/packages/net/common/current/src/dhcp_prot.c +++ b/packages/net/common/current/src/dhcp_prot.c @@ -546,6 +546,7 @@ do_dhcp(const char *intf, struct bootp * struct bootp rx_local; struct bootp *received = &rx_local; struct bootp *xmit = res; + struct bootp xmit2; // First, get a socket on the interface in question. But Zeroth, if // needs be, bring it to the half-up broadcast only state if needs be. @@ -783,7 +784,13 @@ do_dhcp(const char *intf, struct bootp * diag_printf( "---------DHCPSTATE_REQUESTING sending:\n" ); show_bootp( intf, xmit ); #endif - if(sendto(s, xmit, dhcp_size_for_send(xmit), 0, + // Send back a [modified] copy. Note that some fields are explicitly + // cleared, as per the RFC. We need the copy because these fields are + // still useful to us (and currently stored in the 'result' structure) + bcopy(xmit, &xmit2, dhcp_size_for_send(xmit)); + xmit2.bp_yiaddr.s_addr = 0; + xmit2.bp_siaddr.s_addr = 0; + if(sendto(s, &xmit2, dhcp_size_for_send(xmit), 0, (struct sockaddr *)&broadcast_addr, sizeof(broadcast_addr)) < 0) { *pstate = DHCPSTATE_FAILED; break; @@ -913,7 +920,13 @@ do_dhcp(const char *intf, struct bootp * show_bootp( intf, xmit ); #endif - if(sendto(s, xmit, dhcp_size_for_send(xmit), 0, + // Send back a [modified] copy. Note that some fields are explicitly + // cleared, as per the RFC. We need the copy because these fields are + // still useful to us (and currently stored in the 'result' structure) + bcopy(xmit, &xmit2, dhcp_size_for_send(xmit)); + xmit2.bp_yiaddr.s_addr = 0; + xmit2.bp_siaddr.s_addr = 0; + if(sendto(s, &xmit2, dhcp_size_for_send(xmit), 0, // UNICAST address of the server: (struct sockaddr *)&server_addr, sizeof(server_addr)) < 0) { @@ -1011,7 +1024,13 @@ do_dhcp(const char *intf, struct bootp * diag_printf( "---------DHCPSTATE_REBINDING sending:\n" ); show_bootp( intf, xmit ); #endif - if(sendto(s, xmit, dhcp_size_for_send(xmit), 0, + // Send back a [modified] copy. Note that some fields are explicitly + // cleared, as per the RFC. We need the copy because these fields are + // still useful to us (and currently stored in the 'result' structure) + bcopy(xmit, &xmit2, dhcp_size_for_send(xmit)); + xmit2.bp_yiaddr.s_addr = 0; + xmit2.bp_siaddr.s_addr = 0; + if(sendto(s, &xmit2, dhcp_size_for_send(xmit), 0, (struct sockaddr *)&broadcast_addr, sizeof(broadcast_addr)) < 0) { *pstate = DHCPSTATE_FAILED; break; @@ -1152,7 +1171,13 @@ do_dhcp(const char *intf, struct bootp * server_addr.sin_port ); show_bootp( intf, xmit ); #endif - if(sendto(s, xmit, dhcp_size_for_send(xmit), 0, + // Send back a [modified] copy. Note that some fields are explicitly + // cleared, as per the RFC. We need the copy because these fields are + // still useful to us (and currently stored in the 'result' structure) + bcopy(xmit, &xmit2, dhcp_size_for_send(xmit)); + xmit2.bp_yiaddr.s_addr = 0; + xmit2.bp_siaddr.s_addr = 0; + if(sendto(s, &xmit2, dhcp_size_for_send(xmit), 0, // UNICAST address of the server: (struct sockaddr *)&server_addr, sizeof(server_addr)) < 0) {
--- a/packages/net/ns/dns/current/ChangeLog +++ b/packages/net/ns/dns/current/ChangeLog @@ -1,3 +1,7 @@ +2002-05-24 Jonathan Larmour <jlarmour@redhat.com> + + * src/dns.c (free_hent): Actually free hent itself! + 2002-05-23 Jonathan Larmour <jlarmour@redhat.com> * cdl/dns.cdl (CYGPKG_NS_DNS_BUILD): Require thread destructors in
--- a/packages/net/ns/dns/current/src/dns.c +++ b/packages/net/ns/dns/current/src/dns.c @@ -115,6 +115,7 @@ free_hent(struct hostent * hent) } free(hent->h_addr_list); } + free(hent); } /* Allocate hent structure with room for one in_addr. Returns NULL on
--- a/packages/redboot/current/ChangeLog +++ b/packages/redboot/current/ChangeLog @@ -1,3 +1,42 @@ +2002-05-29 Jesper Skov <jskov@redhat.com> + + * doc/redboot_cmds.sgml: Changed format of fis commands. + + * doc/redboot_installing.sgml: Updated installation instructions + for all targets up to PowerPC. + +2002-05-28 Gary Thomas <gthomas@redhat.com> + + * src/load.c (load_elf_image): Improve loading of ELF files with + multiple physical segments. + +2002-05-27 Jesper Skov <jskov@redhat.com> + + * doc/redboot_rebuilding.sgml: Added some guimenu tags. + + * doc/redboot_installing.sgml: Updating more board instructions. + More updates. Changing most programlisting keywords to screen. + Converted remaining rebuild instructions. More mode descriptions + updated. iPAQ converted as well. + +2002-05-24 Gary Thomas <gthomas@redhat.com> + + * src/load.c (load_elf_image): Improve loading where ELF image + actually overlaps headers [old COFF style files]. + +2002-05-24 Jesper Skov <jskov@redhat.com> + + * doc/redboot_installing.sgml: Updated another 3 boards' + instructions. + + * doc/redboot.sgml: Changes due to comments from Jifl. + * doc/redboot_rebuilding.sgml: Same. + + * doc/redboot.sgml: Fix wording. + + * doc/redboot_installing.sgml: Reordered the platform sections + according to CPU architecture/variant and board manufacturer. + 2002-05-23 Jonathan Larmour <jlarmour@redhat.com> * src/net/dns.c (store_hent): New function. DNS package now requires
--- a/packages/redboot/current/doc/redboot.sgml +++ b/packages/redboot/current/doc/redboot.sgml @@ -208,16 +208,8 @@ value for the start-up script; it must a <para>RedBoot can normally be configured to run in a number of startup modes (or just "modes" for short), determining its location of -residence and its location of execution: +residence and execution: <variablelist> - <varlistentry><term>RAM mode</term> - <listitem><para>In this mode, RedBoot both resides and executes from - RAM memory. This is used for updating a primary ROM - mode image in situ and sometimes as part of the RedBoot installation - on the board when there's already an existing (non-RedBoot) boot - monitor available.</para></listitem> - </varlistentry> - <varlistentry><term>ROM mode</term> <listitem><para>In this mode, RedBoot both resides and executes from ROM memory (flash or EPROM). This mode is used when there are limited @@ -235,6 +227,22 @@ residence and its location of execution: only on slower boards) and it is able to update the flash region where the image resides.</para></listitem> </varlistentry> + + <varlistentry><term>RAM mode</term> + <listitem><para>In this mode, RedBoot both resides and executes from + RAM memory. This is used for updating a primary ROM + mode image in situ and sometimes as part of the RedBoot installation + on the board when there's already an existing (non-RedBoot) boot + monitor available.</para> + + <para> You can only use ROM and ROMRAM mode images for booting a + board - a RAM mode image cannot run unless loaded by another ROM + monitor. There is no need for this startup mode if a RedBoot ROMRAM + mode image is the primary boot monitor. When this startup mode is + programmed into flash (as a convenience as it's fast to load from + flash) it will generally be named as "RedBoot[RAM]" in the FIS + directory. </para></listitem> + </varlistentry> </variablelist> The chosen mode has influence on flash and RAM resource usage (see @@ -270,6 +278,14 @@ resources used by RedBoot, such as timer used by RedBoot are listed in the platform specific parts of this manual.</para> +<para>Both flash and RAM resources used by RedBoot depend to some +degree on the features enabled in the RedBoot configuration. It is +possible to reduce in particular the RAM resources used by RedBoot by +removing features that are not needed. Flash resources can also be +reduced, but due to the granularity of the flash (the block sizes), +reductions in feature size do not always result in flash resource +savings.</para> + <sect2> <title>Flash Resources</title> @@ -295,6 +311,14 @@ RedBoot config 0x0007F000 0x0007F000 FIS directory 0x00070000 0x00070000 0x0000F000 0x00000000 </screen> </para> + +<para>To save flash resources, use a ROMRAM mode RedBoot, or if using +a ROM mode RedBoot, avoid reserving space for the RedBoot[RAM] image +(this is done by changing the RedBoot configuration) and download the +RAM mode RedBoot whenever it is needed. If the RedBoot image takes up +a fraction of an extra flash block, it may be possible to reduce the +image size enough to free this block by removing some features.</para> + </sect2> <sect2> @@ -336,6 +360,13 @@ 06061000: 86 F5 EB D8 3D 11 51 F2 96 F4 06061010: E6 55 DD DB F3 75 5D 15 E0 F3 FC D9 C8 73 1D DA |.U...u]......s..| </screen> </para> + +<para>To reduce RedBoot's RAM resource usage, use a ROM mode +RedBoot. The RedBoot features that use most RAM are the net stack, the +flash support and the gunzip support. These, and other features, can +be disabled to reduce the RAM footprint, but obviously at the cost of +lost functionality.</para> + </sect2> </sect1>
--- a/packages/redboot/current/doc/redboot_cmds.sgml +++ b/packages/redboot/current/doc/redboot_cmds.sgml @@ -1590,204 +1590,525 @@ RAM: 0x00000000-0x00400000 </indexterm><indexterm><primary>fis commands</primary></indexterm>If the platform has flash memory, RedBoot can use this for image storage. Executable images, as well as data, can be stored in flash in a simple file store. The <command> -fis</command> command is used to manipulate and maintain flash images. +fis</command> command (fis is short for Flash Image System) is used to +manipulate and maintain flash images. </para> -<para>The available <command>fis</command> commands are: </para> -<variablelist> -<varlistentry><term>fis init [-f]</term> -<listitem> -<para>This command is used to initialize the flash Image System (FIS). It -should only be executed once, when RedBoot is first installed on the hardware. -Subsequent executions will cause loss of data in the flash (previously saved -images will no longer be accessible). </para> -<para>If the <computeroutput>-f</computeroutput> option is specified, all -blocks of flash memory will be erased as part of this process.</para> -</listitem> -</varlistentry> -</variablelist> -<para><screen> + +<!-- ******** fis init ************************************************ --> + + <refentry id="fis-init-command"> + <refnamediv> + <refname>fis init</refname> + <refpurpose>Initialize Flash Image System (FIS)</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis init</command> + <arg><replaceable>-f</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry>-f</entry> + <entry></entry> + <entry>All blocks of flash memory (except for the boot + blocks) will be erased as part of the initialization + procedure.</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> + + <para>This command is used to initialize the Flash Image System + (FIS). It should normally only be executed once, when RedBoot + is first installed on the hardware. If the reserved images or + their sizes in the FIS change, due to a different configuration + of RedBoot being used, it may be necessary to issue the command + again though. + + <note><para>Subsequent executions will cause loss of + previously stored information in the FIS.</para></note> + </para> + </refsect1> + <refsect1> + <title>Examples</title> + <para> +Initialize the FIS directory. +<screen> +RedBoot> <userinput>fis init</userinput> +About to initialize [format] flash image system - continue (y/n)? <userinput>y</userinput> +*** Initialize FLASH Image System + Warning: device contents not erased, some blocks may not be usable +... Erase from 0x00070000-0x00080000: . +... Program from 0x0606f000-0x0607f000 at 0x00070000: . +</screen> +</para> + + <para> +Initialize the FIS directory and all of flash memory, except for first +blocks of the flash where the boot monitor resides. +<screen> RedBoot> <userinput>fis init -f</userinput> -About to initialize [format] flash image system - continue (y/n)? n -</screen></para> -<variablelist> -<varlistentry><term>fis [-c] [-d] list</term> -<listitem> +About to initialize [format] flash image system - continue (y/n)? <userinput>y</userinput> +*** Initialize FLASH Image System +... Erase from 0x00020000-0x00070000: ..... +... Erase from 0x00080000-0x00080000: +... Erase from 0x00070000-0x00080000: . +... Program from 0x0606f000-0x0607f000 at 0x00070000: . +</screen> +</para> +</refsect1> +</refentry> + +<!-- ******** fis list ************************************************ --> + <refentry id="fis-list-command"> + <refnamediv> + <refname>fis list</refname> + <refpurpose>List Flash Image System directory</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis list</command> + <arg><replaceable>-f</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry>-c</entry> + <entry></entry> + <entry>Show image checksum instead of memory address + (column <computeroutput>Mem addr</computeroutput> is + replaced by + <computeroutput>Checksum</computeroutput>).</entry> + <entry></entry> + </row> + <row> + <entry>-d</entry> + <entry></entry> + <entry>Show image data length instead of amount of flash + occupied by image (column + <computeroutput>Length</computeroutput> is replaced by + <computeroutput>Datalen</computeroutput>).</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> <para>This command lists the images currently available in the FIS. Certain -images used by RedBoot have fixed names. Other images can be manipulated by -the user. </para> -<para>If the <emphasis>-c</emphasis> option is specified, the image checksum -is displayed instead of the <computeroutput>Mem Addr</computeroutput> field. - </para> -<para>If the <emphasis>-d</emphasis> option is specified, the image -<computeroutput>datalength</computeroutput> is displayed instead of the -length [amount of flash used]. The <computeroutput>datalength</computeroutput> -is the length of data within the allocated flash image actually being -used for data. - </para> -</listitem> -</varlistentry> -</variablelist> -<para><screen> +images used by RedBoot have fixed names and have reserved slots in the +FIS (these can be seen after using the <command>fis init</command> +command). Other images can be manipulated by the user.</para> +<note><para>The images are listed in the order they appear in the FIS +directory, not by name or creation time.</para></note> + </refsect1> + + <refsect1> + <title>Examples</title> + <para> +List the FIS directory. +<screen> RedBoot> <userinput>fis list</userinput> -Name flash addr Mem addr Length Entry point -RedBoot 0xA0000000 0xA0000000 0x020000 0x80000000 -RedBoot config 0xA0FC0000 0xA0FC0000 0x020000 0x00000000 -FIS directory 0xA0FE0000 0xA0FE0000 0x020000 0x00000000 +Name FLASH addr Mem addr Length Entry point +RedBoot 0x00000000 0x00000000 0x00020000 0x00000000 +RedBoot config 0x0007F000 0x0007F000 0x00001000 0x00000000 +FIS directory 0x00070000 0x00070000 0x0000F000 0x00000000 +</screen> +</para> + + <para> +List the FIS directory, with image checksums substituted for +memory addresses. +<screen> RedBoot> <userinput>fis list -c</userinput> -Name flash addr Checksum Length Entry point -RedBoot 0xA0000000 0x34C94A57 0x020000 0x80000000 -RedBoot config 0xA0FC0000 0x00000000 0x020000 0x00000000 -FIS directory 0xA0FE0000 0x00000000 0x020000 0x00000000 -</screen></para> -<variablelist> -<varlistentry><term>fis free</term> -<listitem> -<para>This command shows which areas of the flash memory are currently not -in use. In use means that the block contains non-erased contents. Since it -is possible to force an image to be loaded at a particular flash location, -this command can be used to check whether that location is in use by any other -image. </para> -<note><title>NOTE</title> -<para>There is currently no cross-checking between actual flash contents and -the image directory, which mans that there could be a segment of flash which -is not erased that does not correspond to a named image, or vice-versa. +Name FLASH addr Checksum Length Entry point +RedBoot 0x00000000 0x00000000 0x00020000 0x00000000 +RedBoot config 0x0007F000 0x00000000 0x00001000 0x00000000 +FIS directory 0x00070000 0x00000000 0x0000F000 0x00000000 +</screen> +</para> + + <para> +List the FIS directory with image data lengths substituted for flash +block reservation lengths. +<screen> +RedBoot> <userinput>fis list</userinput> +Name FLASH addr Mem addr Datalen Entry point +RedBoot 0x00000000 0x00000000 0x00000000 0x00000000 +RedBoot config 0x0007F000 0x0007F000 0x00000000 0x00000000 +FIS directory 0x00070000 0x00070000 0x00000000 0x00000000 +</screen> </para> -</note> -</listitem> -</varlistentry> -</variablelist> -<para><screen> +</refsect1> +</refentry> + +<!-- ******** fis free ************************************************ --> + + <refentry id="fis-free-command"> + <refnamediv> + <refname>fis free</refname> + <refpurpose>Free flash image</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis free</command> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Description</title> + + +<para>This command shows which areas of the flash memory are currently +not in use. When a block contains non-erased contents it is considered +in use. Since it is possible to force an image to be loaded at a +particular flash location, this command can be used to check whether +that location is in use by any other image.</para> + +<note><para>There is currently no cross-checking between actual flash +contents and the FIS directory, which mans that there could be a +segment of flash which is not erased that does not correspond to a +named image, or vice-versa.</para></note> + </refsect1> + + <refsect1> + <title>Examples</title> + <para> +Show free flash areas. +<screen> RedBoot> <userinput>fis free</userinput> 0xA0040000 .. 0xA07C0000 0xA0840000 .. 0xA0FC0000 </screen></para> -<variablelist> -<varlistentry><term>fis create -b <mem_base> -l <length> [-f <flash_addr>] -[-e <entry_point>] [-r <ram_addr>] [-s <data_length>] [-n] <name> -</term> -<listitem> +</refsect1> +</refentry> + +<!-- ******** fis create ************************************************ --> + + <refentry id="fis-create-command"> + <refnamediv> + <refname>fis create</refname> + <refpurpose>Create flash image</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis create</command> + <arg choice="req">-b <replaceable> data address</replaceable></arg> + <arg choice="req">-l <replaceable> length</replaceable></arg> + <arg>-f <replaceable> flash address</replaceable></arg> + <arg>-e <replaceable> entry</replaceable></arg> + <arg>-r <replaceable> relocation address</replaceable></arg> + <arg>-s <replaceable> data length</replaceable></arg> + <arg>-n </arg> + <arg><replaceable>name</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry>-b</entry> + <entry>Number</entry> + <entry>Address of data to be written to the flash.</entry> + <entry>Address of last loaded file. If not set in a load + operation, it must be specified.</entry> + </row> + <row> + <entry>-l</entry> + <entry>Number</entry> + <entry>Length of flash area to occopy. If specified, and + the named image already exists, the length must match + the value in the FIS directory.</entry> + <entry>Length of area reserved in FIS directory if the + image already exists, or the length of the last loaded + file. If neither are set, it must be specified.</entry> + </row> + <row> + <entry>-f</entry> + <entry>Number</entry> + <entry>Address of flash area to occopy.</entry> + <entry>The address of an area reserved in the FIS + directory for extant images. Otherwise the first free block + which is large enough will be used.</entry> + </row> + <row> + <entry>-e</entry> + <entry>Number</entry> + <entry>Entry address for an executable image, used by + the <command>fis load</command> command.</entry> + <entry>The entry address of last loaded file.</entry> + </row> + <row> + <entry>-r</entry> + <entry>Number</entry> + <entry>Address where the image should be relocated to by + the <command>fis load</command> command. This is only + relevant for images that will be loaded with the + <command>fis load</command> command.</entry> + <entry>The load address of the last loaded file.</entry> + </row> + <row> + <entry>-s</entry> + <entry>Number</entry> + <entry>Actual length of data written to image. This is + used to control the range over which the checksum is + made.</entry> + <entry>It defaults to the length of the last loaded + file.</entry> + </row> + <row> + <entry>-n</entry> + <entry></entry> + <entry>When set, no image data will be written to the + flash. Only the FIS directory will be updated.</entry> + <entry></entry> + </row> + <row> + <entry><replaceable>name</replaceable></entry> + <entry>String</entry> + <entry>Name of flash image.</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> <para>This command creates an image in the FIS directory. The data for the image must exist in RAM memory before the copy. Typically, you would use the -RedBoot <command>load</command> command to load an image into +RedBoot <command>load</command> command to load file into RAM and then the <command>fis create</command> command to write -it to flash. </para> -</listitem> -</varlistentry> -</variablelist> -<bridgehead>Arguments</bridgehead> -<informaltable frame="none"><tgroup cols="2"> -<?PubTbl tgroup dispwid="7.00in"> -<colspec colname="col1" colwidth="0.75in"><colspec colname="col2" colwidth="2*"> -<tbody><row> -<entry colname="col1" colsep="0" rowsep="0">name</entry> -<entry colname="col2" colsep="0" rowsep="0">The name of the file, as shown -in the FIS directory.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-b</entry> -<entry colname="col2" colsep="0" rowsep="0">The location in RAM used to obtain -the image. This is a required option.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-l</entry> -<entry colname="col2" colsep="0" rowsep="0">The length of the image. If the -image already exists, then the length is inferred from when the image was -previously created. If specified, and the image exists, it must match the -original value.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-f</entry> -<entry colname="col2" colsep="0" rowsep="0">The location in flash for the -image, which will be inferred for extant images if not specified. If this -is not provided, the first free block which is large enough will be used. -See <command>fis free</command>.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-e</entry> -<entry colname="col2" colsep="0" rowsep="0">The execution entry address. This -is used if the starting address for an image is not known, or needs to be -overridden.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-r</entry> -<entry colname="col2" colsep="0" rowsep="0">The location in RAM when the image -is loaded via<command> fis load</command>. This only needs to -be specified for images which will eventually loaded via <command> -fis load</command>. Fixed images, such as RedBoot itself, will not -need this.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0"> -s</entry> -<entry colname="col2" colsep="0" rowsep="0">The length of the actual data -to be written to flash. If not present then the image length (-1) value is -assumed. If the value given by -s is less than -1, the remainder of the image -in flash will be left in an erased state. Note that by using this option it -is possible to create a completely empty flash image, for example to reserve -space for use by applications other than RedBoot.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-n</entry> -<entry colname="col2" colsep="0" rowsep="0">If -n is specified, then only -the FIS directory is updated, and no data is copied from RAM to flash. This -feature can be used to recreate the FIS entry if it has been destroyed.</entry> -</row></tbody></tgroup></informaltable> -<para><screen> +it to a flash image.</para> +</refsect1> + + <refsect1> + <title>Examples</title> + <para>Trying to create an extant image, will require the action + to be verified. +<screen> RedBoot> <userinput>fis create RedBoot -f 0xa0000000 -b 0x8c400000 -l 0x20000</userinput> -An image named ‘RedBoot’ exists - continue (y/n)? n +An image named ‘RedBoot’ exists - continue (y/n)? <userinput>n</userinput> +</screen> +</para> + +<para>Create a new test image, let the command find a suitable place. +<screen> RedBoot> <userinput>fis create junk -b 0x8c400000 -l 0x20000</userinput> ... Erase from 0xa0040000-0xa0060000: . ... Program from 0x8c400000-0x8c420000 at 0xa0040000: . ... Erase from 0xa0fe0000-0xa1000000: . ... Program from 0x8c7d0000-0x8c7f0000 at 0xa0fe0000: . -</screen>If -you are loading an existing file, then the fis create command will provide -some values automatically, such as the flash address and flash length.</para> -<variablelist> -<varlistentry><term>fis load [-b <memory load address>] [-c] [-d] name -</term> -<listitem> +</screen> +</para> + +<para>Update the RedBoot[RAM] image. +<screen> +RedBoot> <userinput>load redboot_RAM.img</userinput> +Entry point: 0x060213c0, address range: 0x06020000-0x06036cc0 +RedBoot> <userinput>fis create RedBoot[RAM]</userinput> +No memory address set. +An image named 'RedBoot[RAM]' exists - continue (y/n)? <userinput>y</userinput> +* CAUTION * about to program 'RedBoot[RAM]' + at 0x00020000..0x00036cbf from 0x06020000 - continue (y/n)? <userinput>y</userinput> +... Erase from 0x00020000-0x00040000: .. +... Program from 0x06020000-0x06036cc0 at 0x00020000: .. +... Erase from 0x00070000-0x00080000: . +... Program from 0x0606f000-0x0607f000 at 0x00070000: . +</screen> +</para> +</refsect1> +</refentry> + +<!-- ******** fis load ************************************************ --> + + <refentry id="fis-load-command"> + <refnamediv> + <refname>fis load</refname> + <refpurpose>Load flash image</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis load</command> + <arg>-b <replaceable> load address</replaceable></arg> + <arg>-c </arg> + <arg>-d </arg> + <arg><replaceable>name</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry>-b</entry> + <entry>Number</entry> + <entry>Address the image should be loaded to. Executable + images normally load at the location to which the file + was linked. This option allows the image to be loaded to + a specific memory location, possibly overriding any + assumed location.</entry> + <entry>If not specified, the address associated with the + image in the FIS directory will be used.</entry> + </row> + <row> + <entry>-c</entry> + <entry></entry> + <entry>Compute and print the checksum of the image data + after it has been loaded into memory.</entry> + </row> + <row> + <entry>-d</entry> + <entry></entry> + <entry>Decompress gzipped image while copying it from + flash to RAM.</entry> + </row> + <row> + <entry><replaceable>name</replaceable></entry> + <entry>String</entry> + <entry>The name of the file, as shown in the FIS + directory.</entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> <para>This command is used to transfer an image from flash memory to RAM. </para> -<para>Once loaded, it may be executed using the go command. If -b is specified, -then the image is copied from flash to the specified address in RAM. If -b -is not specified, the image is copied from flash to the load address given -when the image was created. </para> -</listitem> -</varlistentry> -</variablelist> -<bridgehead>Arguments</bridgehead> -<para> -<informaltable frame="none"><tgroup cols="2"> -<?PubTbl tgroup dispwid="7.00in"> -<colspec colname="col1" colwidth="0.75in"><colspec colname="col2" colwidth="2*"> -<tbody><row> -<entry colname="col1" colsep="0" rowsep="0">name</entry> -<entry colname="col2" colsep="0" rowsep="0">The name of the file, as shown -in the FIS directory</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-b</entry> -<entry colname="col2" colsep="0" rowsep="0">Specify the location in memory -to which the file should be loaded. Executable images normally load at the -location to which the file was linked. This option allows the file to be loaded -to a specific memory location, possibly overriding any assumed location.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-c</entry> -<entry colname="col2" colsep="0" rowsep="0">Compute and print the checksum -of the image data after it has been loaded into memory.</entry> -</row><row> -<entry colname="col1" colsep="0" rowsep="0">-d</entry> -<entry colname="col2" colsep="0" rowsep="0">Decompress gzipped image while -copying it from flash to RAM.</entry> -</row></tbody></tgroup></informaltable> -</para> -<para><screen> +<para>Once the image has been loaded, it may be executed using the +<command>go</command> command.</para> +</refsect1> + + <refsect1> + <title>Examples</title> +<para>Load and run RedBoot[RAM] image. +<screen> RedBoot> <userinput>fis load RedBoot[RAM]</userinput> RedBoot> <userinput>go</userinput> </screen> </para> -<variablelist> -<varlistentry><term>fis delete name</term> -<listitem> +</refsect1> +</refentry> + +<!-- ******** fis delete ************************************************ --> + + <refentry id="fis-delete-command"> + <refnamediv> + <refname>fis delete</refname> + <refpurpose>Delete flash image</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis delete</command> + <arg choice="req"><replaceable>name</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry><replaceable>name</replaceable></entry> + <entry>Number</entry> + <entry>Name of image that should be deleted.</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> <para>This command removes an image from the FIS. The flash memory will be erased as part of the execution of this command, as well as removal of the name from the FIS directory.</para> -</listitem> -</varlistentry> -</variablelist> -<para><screen> + +<note><para>Certain images are reserved by RedBoot and cannot be deleted. +RedBoot will issue a warning if this is attempted.</para></note> +</refsect1> + <refsect1> + <title>Examples</title> +<para> +<screen> RedBoot> <userinput>fis list</userinput> Name flash addr Mem addr Length Entry point RedBoot 0xA0000000 0xA0000000 0x020000 0x80000000 @@ -1795,73 +2116,294 @@ RedBoot config 0xA0FC0000 0xA0FC0000 FIS directory 0xA0FE0000 0xA0FE0000 0x020000 0x00000000 junk 0xA0040000 0x8C400000 0x020000 0x80000000 RedBoot> <userinput>fis delete junk</userinput> -Delete image ‘junk’ - continue (y/n)? y +Delete image ‘junk’ - continue (y/n)? <userinput>y</userinput> ... Erase from 0xa0040000-0xa0060000: . ... Erase from 0xa0fe0000-0xa1000000: . ... Program from 0x8c7d0000-0x8c7f0000 at 0xa0fe0000: . </screen> - </para> -<note><title>NOTE</title> -<para>Certain images are reserved by RedBoot and cannot be deleted. -RedBoot will issue a warning if this is attempted. </para> -</note> -<variablelist> -<varlistentry><term>fis lock -f <flash_addr> -l <length></term> -<listitem> +</refsect1> +</refentry> + +<!-- ******** fis lock ************************************************ --> + + <refentry id="fis-lock-command"> + <refnamediv> + <refname>fis lock</refname> + <refpurpose>Lock flash area</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis lock</command> + <arg choice="req">-f <replaceable>flash_address</replaceable></arg> + <arg choice="req">-l <replaceable>length</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry><replaceable>flash_address</replaceable></entry> + <entry>Number</entry> + <entry>Address of area to be locked.</entry> + <entry></entry> + </row> + <row> + <entry><replaceable>length</replaceable></entry> + <entry>Number</entry> + <entry>Length of area to be locked.</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> <para>This command is used to write-protect (lock) a portion of flash memory, to prevent accidental overwriting of images. In order to make make any modifications -to the flash, a matching unlock command must be issued. This command is optional -and will only be provided on hardware which can support write-protection of -the flash space. </para> -<note><title>NOTE</title> +to the flash, a matching <command>fis unlock</command> command must be +issued. This command is optional and will only be provided on hardware +which can support write-protection of the flash space.</para> +<note> <para>Depending on the system, attempting to write to write-protected flash may generate errors or warnings, or be benignly quiet. </para> </note> -</listitem> -</varlistentry> -</variablelist> -<para><screen> +</refsect1> + + <refsect1> + <title>Examples</title> +<para>Lock an area of the flash +<screen> RedBoot> <userinput>fis lock -f 0xa0040000 -l 0x20000</userinput> ... Lock from 0xa0040000-0xa0060000: . </screen> - </para> -<variablelist> -<varlistentry><term>fis unlock -f <flash_addr> -l <length></term> -<listitem> +</para> +</refsect1> +</refentry> + +<!-- ******** fis unlock ************************************************ --> + + <refentry id="fis-unlock-command"> + <refnamediv> + <refname>fis unlock</refname> + <refpurpose>Unlock flash area</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis unlock</command> + <arg choice="req">-f <replaceable>flash_address</replaceable></arg> + <arg choice="req">-l <replaceable>length</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry><replaceable>flash_address</replaceable></entry> + <entry>Number</entry> + <entry>Address of area to be unlocked.</entry> + <entry></entry> + </row> + <row> + <entry><replaceable>length</replaceable></entry> + <entry>Number</entry> + <entry>Length of area to be unlocked.</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> <para>This command is used to unlock a portion of flash memory forcibly, allowing it to be updated. It must be issued for regions which have been locked before the FIS can reuse those portions of flash.</para> -</listitem> -</varlistentry> -</variablelist> -<para><screen> +<note> +<para>Some flash devices power up in locked state and always need to +be manually unlocked before they can be written to.</para></note> +</refsect1> + + <refsect1> + <title>Examples</title> +<para>Unlock an area of the flash +<screen> RedBoot> <userinput>fis unlock -f 0xa0040000 -l 0x20000</userinput> ... Unlock from 0xa0040000-0xa0060000: . </screen> - </para> -<variablelist> -<varlistentry><term>fis erase -f <flash_addr> -l <length></term> -<listitem> +</para> +</refsect1> +</refentry> + +<!-- ******** fis erase ************************************************ --> + + <refentry id="fis-erase-command"> + <refnamediv> + <refname>fis erase</refname> + <refpurpose>Erase flash area</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis erase</command> + <arg choice="req">-f <replaceable>flash_address</replaceable></arg> + <arg choice="req">-l <replaceable>length</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry><replaceable>flash_address</replaceable></entry> + <entry>Number</entry> + <entry>Address of area to be erased.</entry> + <entry></entry> + </row> + <row> + <entry><replaceable>length</replaceable></entry> + <entry>Number</entry> + <entry>Length of area to be erased.</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> <para>This command is used to erase a portion of flash memory forcibly. There is no cross-checking to ensure that the area being erased does not correspond -to a loaded image.</para> -</listitem> -</varlistentry> -</variablelist> -<para><screen> +to an existing image.</para> +</refsect1> + + <refsect1> + <title>Examples</title> +<para>Erase an area of the flash +<screen> RedBoot> <userinput>fis erase -f 0xa0040000 -l 0x20000</userinput> ... Erase from 0xa0040000-0xa0060000: . </screen> </para> -<variablelist> -<varlistentry><term>fis write -b <location> -l <length> -f <flash -addr></term> -<listitem> -<para>Writes data from RAM at <location> to flash.</para> -</listitem> -</varlistentry> -</variablelist> +</refsect1> +</refentry> + +<!-- ******** fis write ************************************************ --> + + <refentry id="fis-write-command"> + <refnamediv> + <refname>fis write</refname> + <refpurpose>Write flash area</refpurpose> + </refnamediv> + <refsynopsisdiv> + <cmdsynopsis> + <command>fis write</command> + <arg choice="req">-b <replaceable>mem_address</replaceable></arg> + <arg choice="req">-l <replaceable>length</replaceable></arg> + <arg choice="req">-f <replaceable>flash_address</replaceable></arg> + </cmdsynopsis> + </refsynopsisdiv> + <refsect1> + <title>Arguments</title> + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <colspec colname="c1"> + <colspec colname="c2"> + <colspec colname="c3"> + <colspec colname="c4"> + <thead> + <row> + <entry>Name</entry> + <entry>Type</entry> + <entry>Description</entry> + <entry>Default</entry> + </row> + </thead> + <tbody> + <row> + <entry><replaceable>mem_address</replaceable></entry> + <entry>Number</entry> + <entry>Address of data to be written to flash.</entry> + <entry></entry> + </row> + <row> + <entry><replaceable>length</replaceable></entry> + <entry>Number</entry> + <entry>Length of data to be writtem.</entry> + <entry></entry> + </row> + <row> + <entry><replaceable>flash_address</replaceable></entry> + <entry>Number</entry> + <entry>Address of flash to write to.</entry> + <entry></entry> + </row> + </tbody> + </tgroup> + </informaltable> + </refsect1> + <refsect1> + <title>Description</title> +<para>This command is used to write data from memory to flash. There +is no cross-checking to ensure that the area being written to does not +correspond to an existing image.</para> +</refsect1> + + <refsect1> + <title>Examples</title> +<para>Write an area of data to the flash +<screen> +RedBoot> <userinput>fis write -b 0x0606f000 -l 0x1000 -f 0x00020000</userinput> +* CAUTION * about to program FLASH + at 0x00020000..0x0002ffff from 0x0606f000 - continue (y/n)? <userinput>y</userinput> +... Erase from 0x00020000-0x00030000: . +... Program from 0x0606f000-0x0607f000 at 0x00020000: . +</screen> +</para> +</refsect1> +</refentry> + </sect1> <sect1 id="Persistent-State-Flash"> <title>Persistent State Flash-based Configuration and Control</title>
--- a/packages/redboot/current/doc/redboot_installing.sgml +++ b/packages/redboot/current/doc/redboot_installing.sgml @@ -1,9 +1,2615 @@ +<!-- FIXME: + Need to make index terms consistent +--> + + <chapter id="Installation-and-Testing"> <title>Installation and Testing</title> <indexterm><primary>installing and testing RedBoot</primary></indexterm><indexterm> <primary>RedBoot</primary><secondary>installing and testing</secondary></indexterm> + +<!-- *************************** AM3x ********************** --> + +<?Pub _newpage> +<sect1 id="asb2305"> +<title>AM3x/MN103E010 Matsushita MN103E010 (AM33/2.0) ASB2305 Board</title> +<sect2> +<title>Overview</title> +<para> +<indexterm> +<primary>Matsushita MN103E010 (AM33/2.0) ASB2305 Board</primary> +<secondary>installing and testing</secondary> +</indexterm> +<indexterm> +<primary>installing and testing</primary> +<secondary>Matsushita MN103E010 (AM33/2.0) ASB2305 Board</secondary> +</indexterm> +RedBoot supports the debug serial port and the built in ethernet port for communication and +downloads. The default serial port settings are 115200,8,N,1 with RTS/CTS flow control. RedBoot can +run from either flash, and can support flash management for either the boot PROM or the system +flash regions.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>PROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the boot PROM and able to + access the system flash.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>FLASH</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the system flash and able to + access the boot PROM.</entry> + <entry>redboot_FLASH.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM and able to access the + boot PROM.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> +</sect2> + +<sect2> +<title>Initial Installation</title> +<para>Unless a pre-programmed system flash module is available to be plugged into a new board, +RedBoot must be installed with the aid of a JTAG interface unit. To achieve this, the RAM mode +RedBoot must be loaded directly into RAM by JTAG and started, and then <emphasis>that</emphasis> +must be used to store the ROM mode RedBoot into the boot PROM.</para> +<para>These instructions assume that you have binary images of the RAM-based and boot PROM-based +RedBoot images available.</para> +<sect3> +<title>Preparing to program the board</title> +<para>If the board is to be programmed, whether via JTAG or RedBoot, some hardware settings need to +be changed:</para> +<itemizedlist> +<listitem> +<para>Jumper across ST18 on the board to allow write access to the boot PROM.</para> +</listitem> +<listitem> +<para>Set DIP switch S1-3 to OFF to allow RedBoot to write to the system flash.</para> +</listitem> +<listitem> +<para>Set the switch S5 (on the front of the board) to boot from whichever flash is +<emphasis>not</emphasis> being programmed. Note that the RedBoot image cannot access the flash from +which it is currently executing (it can only access the other flash).</para> +</listitem> +</itemizedlist> +<para> +The RedBoot binary image files should also be copied to the TFTP pickup area on the host providing +TFTP services if that is how RedBoot should pick up the images it is going to program into the +flash. Alternatively, the images can be passed by YMODEM over the serial link. +</para> +</sect3> +<sect3> +<title>Preparing to use the JTAG debugger</title> +<para>The JTAG debugger will also need setting up:</para> +<orderedlist> +<listitem><para>Install the JTAG debugger software (WICE103E) on a PC running Windows (WinNT is +probably the best choice for this) in “C:/PanaX”.</para> +</listitem> +<listitem><para>Install the Matsushita provided “project” into the +“C:/Panax/wice103e/prj” directory.</para> +</listitem> +<listitem><para>Install the RedBoot image files into the “C:/Panax/wice103e/prj” +directory under the names redboot.ram and redboot.prom.</para> +</listitem> +<listitem><para>Make sure the PC's BIOS has the parallel port set to full bidirectional +mode.</para> +</listitem> +<listitem><para>Connect the JTAG debugger to the PC's parallel port.</para> +</listitem> +<listitem><para>Connect the JTAG debugger to the board.</para> +</listitem> +<listitem><para>Set the switch on the front of the board to boot from “boot +PROM”.</para> +</listitem> +<listitem><para>Power up the JTAG debugger and then power up the board.</para> +</listitem> +<listitem><para>Connect the board's Debug Serial port to a computer by a null modem cable.</para> +</listitem> +<listitem><para>Start minicom or some other serial communication software and set for 115200 baud, +1-N-8 with hardware (RTS/CTS) flow control.</para> +</listitem> +</orderedlist> +</sect3> +<sect3> +<title>Loading the RAM-based RedBoot via JTAG</title> +<para>To perform the first half of the operation, the following steps should be followed:</para> +<orderedlist> +<listitem><para>Start the JTAG debugger software.</para> +</listitem> +<listitem> +<para>Run the following commands at the JTAG debugger's prompt to set up the MMU registers on the +CPU.</para> +<screen> +<userinput>ed 0xc0002000, 0x12000580</userinput> + +<userinput>ed 0xd8c00100, 0x8000fe01</userinput> +<userinput>ed 0xd8c00200, 0x21111000</userinput> +<userinput>ed 0xd8c00204, 0x00100200</userinput> +<userinput>ed 0xd8c00208, 0x00000004</userinput> + +<userinput>ed 0xd8c00110, 0x8400fe01</userinput> +<userinput>ed 0xd8c00210, 0x21111000</userinput> +<userinput>ed 0xd8c00214, 0x00100200</userinput> +<userinput>ed 0xd8c00218, 0x00000004</userinput> + +<userinput>ed 0xd8c00120, 0x8600ff81</userinput> +<userinput>ed 0xd8c00220, 0x21111000</userinput> +<userinput>ed 0xd8c00224, 0x00100200</userinput> +<userinput>ed 0xd8c00228, 0x00000004</userinput> + +<userinput>ed 0xd8c00130, 0x8680ff81</userinput> +<userinput>ed 0xd8c00230, 0x21111000</userinput> +<userinput>ed 0xd8c00234, 0x00100200</userinput> +<userinput>ed 0xd8c00238, 0x00000004</userinput> + +<userinput>ed 0xd8c00140, 0x9800f801</userinput> +<userinput>ed 0xd8c00240, 0x00140000</userinput> +<userinput>ed 0xd8c00244, 0x11011100</userinput> +<userinput>ed 0xd8c00248, 0x01000001</userinput> + +<userinput>ed 0xda000000, 0x55561645</userinput> +<userinput>ed 0xda000004, 0x000003c0</userinput> +<userinput>ed 0xda000008, 0x9000fe01</userinput> +<userinput>ed 0xda00000c, 0x9200fe01</userinput> +<userinput>ed 0xda000000, 0xa89b0654</userinput> +</screen> +</listitem> +<listitem> +<para>Run the following commands at the JTAG debugger's prompt to tell it what regions of the CPU's +address space it can access:</para> +<screen> +<userinput>ex 0x80000000,0x81ffffff,/mexram</userinput> +<userinput>ex 0x84000000,0x85ffffff,/mexram</userinput> +<userinput>ex 0x86000000,0x867fffff,/mexram</userinput> +<userinput>ex 0x86800000,0x87ffffff,/mexram</userinput> +<userinput>ex 0x8c000000,0x8cffffff,/mexram</userinput> +<userinput>ex 0x90000000,0x93ffffff,/mexram</userinput> +</screen> +</listitem> +<listitem><para>Instruct the debugger to load the RAM RedBoot image into RAM:</para> +<screen> +<userinput>_pc=90000000</userinput> +<userinput>u_pc</userinput> +<userinput>rd redboot.ram,90000000</userinput> +</screen> +</listitem> +<listitem><para>Load the boot PROM RedBoot into RAM:</para> +<screen> +<userinput>rd redboot.prom,91020000</userinput> +</screen> +</listitem> +<listitem><para>Start RedBoot in RAM:</para> +<screen> +<userinput>g</userinput> +</screen> +<para>Note that RedBoot may take some time to start up, as it will attempt to query a BOOTP or DHCP +server to try and automatically get an IP address for the board. Note, however, that it should send +a plus over the serial port immediately, and the 7-segment LEDs should display “rh +8”.</para> +</listitem> +</orderedlist> +</sect3> +<sect3> +<title>Loading the boot PROM-based RedBoot via the RAM mode RedBoot</title> +<para>Once the RAM mode RedBoot is up and running, it can be communicated with by way of the serial +port. Commands can now be entered directly to RedBoot for flashing the boot PROM.</para> +<orderedlist> +<listitem><para>Instruct RedBoot to initialise the boot PROM:</para> +<screen> +RedBoot> <userinput>fi init</userinput> +</screen> +</listitem> +<listitem><para>Write the previously loaded redboot.prom image into the boot PROM:</para> +<screen> +RedBoot> <userinput>fi write -f 0x80000000 -b 0x91020000 -l 0x00020000</userinput> +</screen> +</listitem> +<listitem><para>Check that RedBoot has written the image:</para> +<screen> +RedBoot> <userinput>dump -b 0x91020000</userinput> +RedBoot> <userinput>dump -b 0x80000000</userinput> +</screen> +<para>Barring the difference in address, the two dumps should be the same.</para> +</listitem> +<listitem><para>Close the JTAG software and power-cycle the board. The RedBoot banners should be +displayed again over the serial port, followed by the RedBoot prompt. The boot PROM-based RedBoot +will now be running.</para> +</listitem> +<listitem><para>Power off the board and unjumper ST18 to write-protect the contents of the boot +PROM. Then power the board back up.</para> +</listitem> +<listitem><para>Run the following command to initialise the system flash:</para> +<screen> +RedBoot> <userinput>fi init</userinput> +</screen> +<para>Then program the system flash based RedBoot into the system flash:</para> +<screen> +RedBoot> <userinput>load -r -b %{FREEMEMLO} redboot_FLASH.bin</userinput> +RedBoot> <userinput>fi write -f 0x84000000 -b %{FREEMEMLO} -l 0x00020000</userinput> +</screen> +<note> +<title>NOTE</title> +<para>RedBoot arranges the flashes on booting such that they always appear at the same addresses, +no matter which one was booted from.</para> +</note> +</listitem> +<listitem> +<para>A similar sequence of commands can be used to program the boot PROM when RedBoot has been +booted from an image stored in the system flash. +</para> +<screen> +RedBoot> <userinput>load -r -b %{FREEMEMLO} /tftpboot/redboot_ROM.bin</userinput> +RedBoot> <userinput>fi write -f 0x80000000 -b %{FREEMEMLO} -l 0x00020000</userinput> +</screen> +<para>See <xref linkend="Persistent-State-Flash"> for details on configuring the RedBoot in +general, and also <xref linkend="Flash-Image-System"> for more details on programming the system +flash.</para> +</listitem> +</orderedlist> +</sect3> +</sect2> +<sect2> +<title>Additional Commands</title> +<para>The <command>exec</command> command which allows the loading and execution of +Linux kernels, is supported for this architecture (see <xref linkend="executing-programs">). The +<command>exec</command> parameters used for ASB2305 board are:</para> +<variablelist> +<varlistentry><term> +-w <replaceable><time></replaceable></term> +<listitem><para>Wait time in seconds before starting kernel</para></listitem></varlistentry> +<varlistentry><term> +-c <replaceable>"params"</replaceable></term> +<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> +<varlistentry><term><replaceable><addr></replaceable></term> +<listitem><para>Kernel entry point, defaulting to the entry point of the last image +loaded</para></listitem></varlistentry> +</variablelist> +<para>The parameter string is stored in the on-chip memory at location 0x8C001000, and is prefixed +by “cmdline:” if it was supplied.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>RedBoot sets up the following memory map on the ASB2305 board.</para> +<note> +<title>NOTE</title> +<para>The regions mapped between 0x80000000-0x9FFFFFFF are cached by the CPU. However, all those +regions can be accessed uncached by adding 0x20000000 to the address.</para> +</note> +<programlisting> +Physical Address Range Description +----------------------- ----------- +0x80000000 - 0x9FFFFFFF Cached Region +0x80000000 - 0x81FFFFFF Boot PROM +0x84000000 - 0x85FFFFFF System Flash +0x86000000 - 0x86007FFF 64Kbit Sys Config EEPROM +0x86F90000 - 0x86F90003 4x 7-segment LEDs +0x86FA0000 - 0x86FA0003 Software DIP Switches +0x86FB0000 - 0x86FB001F PC16550 Debug Serial Port +0x8C000000 - 0x8FFFFFFF On-Chip Memory (repeated 16Kb SRAM) +0x90000000 - 0x93FFFFFF SDRAM +0x98000000 - 0x9BFFFFFF Paged PCI Memory Space (64Mb) +0x9C000000 - 0x9DFFFFFF PCI Local SRAM (32Mb) +0x9E000000 - 0x9E03FFFF PCI I/O Space +0x9E040000 - 0x9E0400FF AM33-PCI Bridge Registers +0x9FFFFFF4 - 0x9FFFFFF7 PCI Memory Page Register +0x9FFFFFF8 - 0x9FFFFFFF PCI Config Registers +0xA0000000 - 0xBFFFFFFF Uncached Mirror Region +0xC0000000 - 0xDFFFFFFF CPU Control Registers +</programlisting> +<para>The ASB2305 HAL makes use of the on-chip memory in the following way:</para> +<programlisting> +0x8C000000 - 0x8C0000FF hal_vsr_table +0x8C000100 - 0x8C0001FF hal_virtual_vector_table +0x8C001000 - Linux command line (RedBoot exec command) + - 0x8C003FFF Emergency DoubleFault Exception Stack +</programlisting> +<para>Currently the CPU's interrupt table lies at the beginning of the RedBoot image, which must +therefore be aligned to a 0xFF000000 mask.</para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=asb2305 +export ARCH_DIR=mn10300 +export PLATFORM_DIR=asb2305 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<!-- *************************** ARM ******************* --> + +<?Pub _newpage> +<sect1 id="e7t"> +<title>ARM/ARM7 ARM Evaluator7T</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>ARM Evaluator7T</primary><secondary>installing and +testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>ARM Evaluator7T</secondary></indexterm>RedBoot supports +both serial ports for communication and downloads. The default serial port +settings are 38400,8,N,1.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from flash address 0x20000, with + ARM Boot Monitor in flash boot sector.</entry> + <entry>redboot_ROMA.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation</title> +<para>RedBoot is installed using the on-board boot environment. See the user +manual for full details.</para> +</sect2> +<sect2> +<title>Quick download instructions</title> +<para>Here are quick start instructions for downloading the prebuilt Redboot +image:</para> +<itemizedlist> +<listitem><para>Boot the board and press ENTER:</para> +<screen> + + ARM Evaluator7T Boot Monitor PreRelease 1.00 + Press ENTER within 2 seconds to stop autoboot + Boot: </screen> +</listitem> +<listitem><para>Erase the part of the flash where RedBoot will get programmed: +</para> +<screen> Boot: <userinput>flasherase 01820000 10000</userinput></screen> +</listitem> +<listitem><para>Prepare to download the UU-encoded version of the RedBoot +image:</para> +<screen> Boot: <userinput>download 10000</userinput> + Ready to download. Use 'transmit' option on terminal emulator to download file. +</screen> +</listitem> +<listitem><para>Either use ASCII transmit option in the terminal emulator, +or on Linux, simply cat the file to the serial port:<screen> $ <userinput> +cat redboot.UU > /dev/ttyS0</userinput></screen>When complete, you should +see:<screen> Loaded file redboot.bin at address 000100000, size = 41960 + Boot:</screen></para> +</listitem> +<listitem><para>Program the flash:<screen> Boot: <userinput>flashwrite 01820000 10000 10000 +</userinput></screen></para> +</listitem> +<listitem><para>And verify that the module is available:<screen> Boot: <userinput> +rommodules</userinput> + Header Base Limit + 018057c8 01800000 018059e7 BootStrapLoader v1.0 Apr 27 2000 10:33:58 + 01828f24 01820000 0182a3e8 RedBoot Apr 5 2001</screen></para> +</listitem> +<listitem><para>Reboot the board and you should see the RedBoot banner.</para> +</listitem> +</itemizedlist> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>RedBoot sets up the following memory map on the E7T board. <note><title> +NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note> <programlisting>Physical Address Range C B Description +----------------------- - - ----------- +0x00000000 - 0x0007ffff Y N SDRAM +0x03ff0000 - 0x03ffffff N N Microcontroller registers +0x01820000 - 0x0187ffff N N System flash (mirrored)</programlisting></para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=e7t +export ARCH_DIR=arm +export PLATFORM_DIR=e7t +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="integrator"> +<title>ARM/ARM7+ARM9 ARM Integrator</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>ARM Integrator</primary><secondary>installing and +testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>ARM Integrator</secondary></indexterm>RedBoot supports +both serial ports for communication and downloads. The default serial port +settings are 38400,8,N,1.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> + <row> + <entry>ROMRAM</entry> + <entry>[ROMRAM]</entry> + <entry>RedBoot running from RAM, but contained in the + board's flash boot sector.</entry> + <entry>redboot_ROMRAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> + +<sect2> +<title>Initial Installation</title> +<para>RedBoot is installed using the on-board bootPROM environment. See the user +manual for full details.</para> +</sect2> +<sect2> +<title>Quick download instructions</title> +<para>Here are quick start instructions for downloading the prebuilt Redboot +image:</para> +<itemizedlist> +<listitem><para>Set DIP switch S1[1] to the ON position and reset or +power the board up. You will see the bootPROM startup message on +serial port A (J14):</para> +<screen> +Initialising... + + +ARM bootPROM [Version 1.3] Rebuilt on Jun 26 2001 at 22:04:10 +Running on a Integrator Evaluation Board +Board Revision V1.0, ARM966E-S Processor +Memory Size is 16MBytes, Flash Size is 32MBytes +Copyright (c) ARM Limited 1999 - 2001. All rights reserved. +Board designed by ARM Limited +Hardware support provided at http://www.arm.com/ +For help on the available commands type ? or h +boot Monitor > +</screen> +</listitem> +<listitem> +<para>Issue the FLASH ROM load command: +</para> +<screen> +boot Monitor > <userinput>L</userinput> +Load Motorola S-Records into flash + +Deleting Image 0 + +The S-Record loader only accepts input on the serial port. +Type Ctrl/C to exit loader. +</screen> +</listitem> +<listitem><para>Either use the ASCII transmit option in the terminal emulator, +or on Linux, simply cat the file to the serial port: +</para> +<screen> +$ <userinput>cat redboot.srec > /dev/ttyS0</userinput> +</screen> +<para> +When complete, type Ctrl-C and you should see something similar to: +</para> +<screen> +................................ +................................ +.................... +Downloaded 5,394 records in 81 seconds. + +Overwritten block/s + 0 + +boot Monitor > +</screen> +</listitem> +<listitem><para>Set DIP switch S1[1] to the OFF position and reboot +the board and you should see the RedBoot banner.</para> +</listitem> +</itemizedlist> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>RedBoot sets up the following memory map on the Integrator board. <note><title> +NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note> +<programlisting> + +ARM7TDMI +-------- + +Physical Address Range C B Description +----------------------- - - ----------- +0x00000000 - 0x0007ffff N N SSRAM +0x00080000 - 0x0fffffff N N SDRAM (depends on part fitted) +0x10000000 - 0x1fffffff N N System control and peripheral registers +0x20000000 - 0x23ffffff N N Boot ROM (contains boot Monitor) +0x24000000 - 0x27ffffff N N FLASH ROM (contains RedBoot) +0x28000000 - 0x2bffffff N N SSRAM echo area +0x40000000 - 0x5fffffff N N PCI Memory access windows +0x60000000 - 0x60ffffff N N PCI IO access window +0x61000000 - 0x61ffffff N N PCI config space window +0x62000000 - 0x6200ffff N N PCI bridge register window +0x80000000 - 0x8fffffff N N SDRAM echo area (used for PCI accesses) + + +ARM966E +------- + +Physical Address Range C B Description +----------------------- - - ----------- +0x00000000 - 0x000fffff N N SSRAM +0x00100000 - 0x0fffffff N N SDRAM (depends on part fitted) +0x10000000 - 0x1fffffff N N System control and peripheral registers +0x20000000 - 0x23ffffff N N Boot ROM (contains boot Monitor) +0x24000000 - 0x27ffffff N N FLASH ROM (contains RedBoot) +0x28000000 - 0x2bffffff N N SSRAM echo area +0x40000000 - 0x5fffffff N N PCI Memory access windows +0x60000000 - 0x60ffffff N N PCI IO access window +0x61000000 - 0x61ffffff N N PCI config space window +0x62000000 - 0x6200ffff N N PCI bridge register window +0x80000000 - 0x8fffffff N N SDRAM echo area (used for PCI accesses) + +</programlisting> +</para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=integrator +export ARCH_DIR=arm +export PLATFORM_DIR=integrator +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="pid"> +<title>ARM/ARM7+ARM9 ARM PID Board and EPI Dev7+Dev9</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>ARM ARM7 PID, Dev7 and Dev9</primary><secondary> +installing and testing</secondary></indexterm><indexterm><primary>installing +and testing</primary><secondary>ARM ARM7 PID, Dev7 and Dev9</secondary></indexterm>RedBoot +uses either of the serial ports. The default serial port settings are 38400,8,N,1. +Management of onboard flash is also supported.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> +</sect2> + +<sect2> +<title>Initial Installation Method </title> +<para>Device programmer is used to program socketed flash parts with ROM version +of RedBoot. </para> +<para>Alternatively, to install RedBoot on a target that already has eCos +GDB stubs, download the RAM mode image of RedBoot and run it. Initialize the +flash image directory: <command>fis init</command> Then +download the ROM version of RedBoot and program it into flash: <screen> +RedBoot> <userinput>load -b %{FREEMEMLO} -m ymodem</userinput> +RedBoot> <userinput>fi cr RedBoot</userinput> +</screen></para> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>RedBoot sets up the following memory map on the PID board. <programlisting> +Physical Address Range Description +----------------------- ----------- +0x00000000 - 0x0007ffff DRAM +0x04000000 - 0x04080000 flash +0x08000000 - 0x09ffffff ASB Expansion +0x0a000000 - 0x0bffffff APB Reference Peripheral +0x0c000000 - 0x0fffffff NISA Serial, Parallel and PC Card ports </programlisting></para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=pid +export ARCH_DIR=arm +export PLATFORM_DIR=pid +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2></sect1> + +<?Pub _newpage> +<sect1 id="at91"> +<title>ARM/ARM7 Atmel AT91 Evaluation Board (EB40)</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Atmel AT91/EB40</primary> +<secondary>installing and testing</secondary></indexterm><indexterm><primary> +installing and testing</primary><secondary>Atmel AT91/EB40 +</secondary></indexterm>RedBoot supports both serial ports. +The default serial port settings are 38400,8,N,1. RedBoot +also supports minimal flash management on the EB40. +However, since the flash device (AT29LV1024) is so small (only the upper 64K is +available for general use), only 'fconfig' is +supported, along with the simple flash write command, 'fis +write'.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> + <row> + <entry>ROMRAM</entry> + <entry>[ROMRAM]</entry> + <entry>RedBoot running from RAM, but contained in the + board's flash boot sector.</entry> + <entry>redboot_ROMRAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> +</sect2> + +<sect2> +<title>Initial Installation Method </title> +<para> +This development board comes with ARM's debug tool, Angel, installed in flash. +At this time, Angel will not be replaced. Rather, RedBoot will be placed in +the alternate half of flash. Switch SW1 is used which monitor to boot. Selecting +SW1 to "lower mem" will choose Angel. Select SW1 to "Upper mem" for RedBoot once +it has been installed. +</para> +<para> +Set SW1 to "lower mem" and connect serial port A to a host computer. Using GDB +from the host and Angel on the board, download the RAM mode image of RedBoot +to the board. Once this is started, the Angel session must be interrupted (on +Linux this can be done using ^Z). Follow this by connecting to the board using +minicom at 38400-8N1. At this point, RedBoot will be running on the board in +RAM. Now, download the ROMRAM mode image and program it to flash. Be sure and +first set SW1 to "upper mem". +<screen> +<userinput>arm-elf-gdb redboot_RAM.elf</userinput> +(gdb) <userinput>tar rdi s=/dev/ttyS0</userinput> +Angel Debug Monitor (serial) 1.04 (Advanced RISC Machines SDT 2.5) for +AT91EB40 (2.00) +Angel Debug Monitor rebuilt on Apr 07 2000 at 12:40:31 +Serial Rate: 9600 +Connected to ARM RDI target. +(gdb) <userinput>set $ps=0xd3</userinput> +(gdb) <userinput>load</userinput> +Loading section .rom_vectors, size 0x40 lma 0x2020000 +Loading section .text, size 0x7fd8 lma 0x2020040 +Loading section .rodata, size 0x15a0 lma 0x2028018 +Loading section .data, size 0x2e4 lma 0x20295b8 +Start address 0x2020040 , load size 39068 +Transfer rate: 6250 bits/sec, 500 bytes/write. +(gdb) <userinput>cont</userinput> +Continuing. +</screen> +At this point, suspend the GDB session (use Ctrl-Z) and start a +terminal emulator: +<screen> +RedBoot> <userinput>version</userinput> + +RedBoot(tm) bootstrap and debug environment [RAM] +Non-certified release, version UNKNOWN - built 14:09:27, Jul 20 2001 + +Platform: Atmel AT91/EB40 (ARM7TDMI) +Copyright (C) 2000, 2001, Red Hat, Inc. + +RAM: 0x02000000-0x02080000, 0x020116d8-0x0207fd00 available +FLASH: 0x01010000 - 0x01020000, 256 blocks of 0x00000100 bytes each. + +RedBoot> <userinput>load -m ymodem -b %{FREEMEMLO}</userinput> +</screen> +Use minicom to send the file redboot_ROMRAM.srec via YModem. +<screen> +RedBoot> <userinput>fi wr -f 0x01010000 -b %{FREEMEMLO} -l 0xe000</userinput> +</screen> +Set switch SW1 to "upper mem", press the "reset" pushbutton and RedBoot +should come up on the board. +</para> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>This processor has no MMU, so the only memory map is for physical addresses. +<programlisting> +Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x00000fff On-chip SRAM +0x01000000 - 0x0101ffff Flash +0x02000000 - 0x0207ffff RAM +0xffe00000 - 0xffffffff I/O registers + +The flash based RedBoot image occupies virtual addresses 0x01010000 - 0x0101dfff +</programlisting></para> + +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=eb40 +export ARCH_DIR=arm +export PLATFORM_DIR=at91 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + + +<?Pub _newpage> +<sect1 id="edb7xxx"> +<title>ARM/ARM7 Cirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312) </title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Cirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312)</primary> +<secondary>installing and testing</secondary></indexterm><indexterm><primary> +installing and testing</primary><secondary>Cirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312) +</secondary></indexterm>RedBoot supports both serial ports on the board and +the ethernet port. The default serial port settings are 38400,8,N,1. RedBoot +also supports flash management on the EDB7xxx for the NOR flash +only.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> + <row> + <entry>ROMRAM</entry> + <entry>[ROMRAM]</entry> + <entry>RedBoot running from RAM, but contained in the + board's flash boot sector (EDB7312 only).</entry> + <entry>redboot_ROMRAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation Method </title> +<para>A Windows or Linux utility is used to program flash using serial port +#1 via on-chip programming firmware. See board documentation for details on +in situ flash programming. </para> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>The MMU page tables and LCD display buffer, if enabled, are located +at the end of DRAM. <note><title>NOTE +</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note><programlisting> +Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x01ffffff NOR Flash (EDB7211, EDB7212) +0x00000000 - 0x00ffffff NOR Flash (EDB7312) +0x10000000 - 0x11ffffff NAND Flash +0x20000000 - 0x2fffffff Expansion 2 +0x30000000 - 0x3fffffff Expansion 3 +0x40000000 - 0x4fffffff PCMCIA 0 +0x50000000 - 0x5fffffff PCMCIA 1 +0x60000000 - 0x600007ff On-chip SRAM +0x80000000 - 0x8fffffff I/O registers +0xc0000000 - 0xc1ffffff DRAM (EDB7211, EDB7212) +0xc0000000 - 0xc0ffffff DRAM (EDB7312) + +Virtual Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x01ffffff Y Y DRAM +0x00000000 - 0x00fcffff Y Y DRAM (EDB7312) +0x20000000 - 0x2fffffff N N Expansion 2 +0x30000000 - 0x3fffffff N N Expansion 3 +0x40000000 - 0x4fffffff N N PCMCIA 0 +0x50000000 - 0x5fffffff N N PCMCIA 1 +0x60000000 - 0x600007ff Y Y On-chip SRAM +0x80000000 - 0x8fffffff N N I/O registers +0xc0000000 - 0xc001ffff N Y LCD buffer (if configured) +0xe0000000 - 0xe1ffffff Y Y NOR Flash (EDB7211, EDB7212) +0xe0000000 - 0xe0ffffff Y Y NOR Flash (EDB7312) +0xf0000000 - 0xf1ffffff Y Y NAND Flash + +The flash based RedBoot image occupies virtual addresses 0xe0000000 - 0xe003ffff. +</programlisting></para> +</sect2> +<sect2> +<title>Platform Resource Usage</title> +<para>The EP7xxx timer #2 is used as a polled timer to provide timeout support +for network and XModem file transfers.</para> +</sect2><sect2> + +<title>Rebuilding RedBoot</title> + + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=edb7211 +export TARGET=edb7212 +export TARGET=edb7312 +export ARCH_DIR=arm +export PLATFORM_DIR=edb7xxx +</programlisting> + +Use one of the TARGET settings only. +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="aaed2000"> +<title>ARM/ARM9 Agilent AAED2000</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Agilent AAED2000 ARM9 (aaed)</primary> +<secondary>installing and testing</secondary></indexterm><indexterm><primary> +installing and testing</primary><secondary>Agilent AAED2000 ARM9 (aaed) +</secondary></indexterm>RedBoot supports the serial and ethernet ports +on the board. The default serial port settings are 38400,8,N,1. +RedBoot also supports flash management on the AAED2000.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROMRAM</entry> + <entry>[ROMRAM]</entry> + <entry>RedBoot running from RAM, but contained in the + board's flash boot sector.</entry> + <entry>redboot_primary_ROMRAM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_primary_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> +</sect2> + +<sect2> +<title>Initial Installation Method </title> +<para>It is possible to install RedBoot in one of two ways. Either as +the primary bootmonitor on the board (installed to blocks 0-1 of the +flash) or as the secondary bootmonitor on the board (installed to +blocks 1-2 of the flash).</para> + +<para>Presently, only the former method is supported.</para> +<!-- Nuke the above line if uncommenting this block +<para>When installed as the secondary bootmonitor, the ARM bootmonitor +remains in flash and auto-executes RedBoot (but only when RedBoot is +smaller than 128KB - which means it cannot include the LCD driver). +It is of crucial importance that no RedBoot configured to be +primary bootmonitor is executed on a board where RedBoot is actually +supposed to be the secondary bootmonitor since it may cause corruption +of the flash. Installing RedBoot as the primary booter is +adviced.</para> +--> + +<sect3><title>RedBoot as Primary Bootmonitor</title> + +<para>RedBoot is installed in flash using the on-board ARM Boot +Monitor.</para> +<para>Boot the board while pressing SPACE. This should bring up the +Boot Monitor: +<screen>ARM bootPROM [Version 1.3] Rebuilt on Jul 16 2001 at 16:21:36 +Running on a P920 board Evaluation Board +Board Revision V1.0, ARM920T processor Processor +Memory Size is 32MBytes, Flash Size is 32MBytes +Copyright (c) ARM Limited 1999 - 2001. All rights reserved. +Board designed by ARM Limited +Hardware support provided at http://www.arm.com/ +For help on the available commands type ? or h +boot Monitor > +</screen> + +Download the RAM mode image of RedBoot configured as a primary +bootmonitor using the ARM bootmonitor's SREC-download command: + +<screen>boot Monitor > <userinput>m</userinput> +Load Motorola S-Record image into memory and execute it +The S-Record loader only accepts input on the serial port. +Record addresses must be between 0x00008000 and 0x01E0F510. +Type Ctrl/C to exit loader. +</screen> + +Use the terminal emulator's ASCII upload command, or (on Linux) simply +cat the file to the serial port: + +<screen>$ <userinput>cat redboot_primary_RAM/redboot.srec >/dev/ttyS1</userinput> +</screen> + +You should see RedBoot start up: + +<screen>FLASH configuration checksum error or invalid key +Ethernet eth0: MAC address 00:30:d3:03:04:99 +IP: 192.168.42.111, Default server: 192.168.42.3 + +RedBoot(tm) bootstrap and debug environment [RAM] +Non-certified release, version UNKNOWN - built 13:15:40, Nov 9 2001 + +Platform: AAED2000 system (ARM9) [Primary] +Copyright (C) 2000, 2001, Red Hat, Inc. + +RAM: 0x00000000-0x01f80000, 0x0006f208-0x01f51000 available +FLASH: 0x60000000 - 0x62000000, 256 blocks of 0x00020000 bytes each. +RedBoot></screen> + +As can be seen from the output above, the network has been configured +to give the board an IP address and information about the default +server. If things are not set up on your network, you can still +continue, but use the Y-modem download method when loading the RedBoot +ROMRAM mode image. + +Now initialize RedBoot's FIS: + +<screen>RedBoot> <userinput>fis init</userinput> +About to initialize [format] FLASH image system - continue (y/n)? <userinput>y</userinput> +*** Initialize FLASH Image System + Warning: device contents not erased, some blocks may not be usable +... Erase from 0x61fe0000-0x62000000: . +... Program from 0x01f5f000-0x01f5f300 at 0x61fe0000: . +</screen> + +Download the ROMRAM mode image of RedBoot via ethernet: + +<screen>RedBoot> <userinput>load -b %{FREEMEMLO} redboot_primary_ROMRAM/redboot.srec</userinput> +</screen> + +or using serial Y-modem protocol: + +<screen>RedBoot> <userinput>load -mode ymodem -b %{FREEMEMLO}</userinput> +</screen> + +(Use the terminal emulator's Y-modem upload command to send the file +<filename>redboot_primary_ROMRAM/redboot.srec</filename>.) + +When the image has been downloaded, program it into flash: + +<screen>Address offset = 0x00ff8000 +Entry point: 0x00008040, address range: 0x00008000-0x0002da80 +RedBoot> <userinput>fi cr RedBoot</userinput> +An image named 'RedBoot' exists - continue (y/n)? <userinput>y</userinput> +* CAUTION * about to program 'RedBoot' + at 0x60000000..0x6003ffff from 0x00100000 - continue (y/n)? <userinput>y</userinput> +... Erase from 0x60000000-0x60040000: .. +... Program from 0x00100000-0x00140000 at 0x60000000: .. +... Erase from 0x61fe0000-0x62000000: . +... Program from 0x01f5f000-0x01f7f000 at 0x61fe0000: . +</screen> + +Now reset the board. You should see the RedBoot banner.</para> + +</sect3> + +<!-- +<sect3><title>RedBoot as Secondary Bootmonitor</title> + +<para>RedBoot is installed in flash using the on-board ARM Boot +Monitor.</para> +<para>Boot the board while pressing SPACE. This should bring up the +Boot Monitor: +<screen>ARM bootPROM [Version 1.3] Rebuilt on Jul 16 2001 at 16:21:36 +Running on a P920 board Evaluation Board +Board Revision V1.0, ARM920T processor Processor +Memory Size is 32MBytes, Flash Size is 32MBytes +Copyright (c) ARM Limited 1999 - 2001. All rights reserved. +Board designed by ARM Limited +Hardware support provided at http://www.arm.com/ +For help on the available commands type ? or h +boot Monitor > +</screen> + +Download the RAM mode image of RedBoot configured as a secondary +bootmonitor using the ARM bootmonitor's SREC-download command: + +<screen>boot Monitor > <userinput>m</userinput> +Load Motorola S-Record image into memory and execute it +The S-Record loader only accepts input on the serial port. +Record addresses must be between 0x00008000 and 0x01E0F510. +Type Ctrl/C to exit loader. +</screen> + +Use the terminal emulator's ASCII upload command, or (on Linux) simply +cat the file to the serial port: + +<screen>$ <userinput>cat redboot_secondary_RAM.srec >/dev/ttyS1</userinput> +</screen> + +You should see RedBoot start up: + +<screen>FLASH configuration checksum error or invalid key +Ethernet eth0: MAC address 00:30:d3:03:04:99 +IP: 192.168.42.111, Default server: 192.168.42.3 + +RedBoot(tm) bootstrap and debug environment [RAM] +Non-certified release, version UNKNOWN - built 12:31:13, Nov 9 2001 + +Platform: AAED2000 system (ARM9) [Secondary] +Copyright (C) 2000, 2001, Red Hat, Inc. + +RAM: 0x00000000-0x01f80000, 0x00063568-0x01f51000 available +FLASH: 0x60000000 - 0x62000000, 256 blocks of 0x00020000 bytes each. +</screen> + +As can be seen from the output above, the network has been configured +to give the board an IP address and information about the default +server. If things are not set up on your network, you can still +continue, but use the Y-modem download method when loading the RedBoot +ROMRAM mode image. + +Next step is to erase all of the flash, except where the ARM booter resides: + +<screen>RedBoot> <userinput>fi erase -f 0x60020000 -l 0x01fe0000</userinput> +... Erase from 0x60020000-0x62000000: .......................................... +................................................................................ +................................................................................ +..................................................... +</screen> + +Then initialize RedBoot's FIS: + +<screen>RedBoot> <userinput>fi init</userinput> +About to initialize [format] FLASH image system - continue (y/n)? <userinput>y</userinput> +*** Initialize FLASH Image System + Warning: device contents not erased, some blocks may not be usable +... Erase from 0x61fc0000-0x61fe0000: . +... Program from 0x01fdf000-0x01fff000 at 0x61fc0000: . +</screen> + +Download the ROMRAM mode RedBoot image via ethernet: + +<screen>RedBoot> <userinput>load -raw -b %{FREEMEMLO} redboot_secondary_ROMRAM.arm.bin</userinput> +</screen> + +or using serial Y-modem protocol: + +<screen>RedBoot> <userinput>load -raw -mode ymodem -b %{FREEMEMLO}</userinput> +</screen> + +(Use the terminal emulator's Y-modem upload command to send the file +<filename>redboot_secondary_ROMRAM.arm.bin</filename>.) + +When the image has been downloaded, program it into flash: + +<screen>RedBoot> <userinput>fi cr RedBoot</userinput> +An image named 'RedBoot' exists - continue (y/n)? <userinput>y</userinput> +* CAUTION * about to program 'RedBoot' + at 0x60020000..0x6005ffff from 0x00100000 - continue (y/n)? <userinput>y</userinput> +... Erase from 0x60020000-0x60060000: .. +... Program from 0x00100000-0x00140000 at 0x60020000: .. +... Erase from 0x61fc0000-0x61fe0000: . +... Program from 0x01f5f000-0x01f7f000 at 0x61fc0000: . +</screen> + +Now reset the board. You might see the ARM Monitor complain: + +<screen>Failed to boot from flash. +The ARM Boot Monitor SIB can not be found. +Press any key to continue. +</screen> + +This is due to due to the flash having been erased. Press a key, and +execute the "validate flash contents" command: + +<screen>boot Monitor > <userinput>v</userinput> + +There are 254 128KByte blocks of Application Flash: + +No images found! +================ + +System Information Blocks +========================= +Address Owner Size Idx Rev +~~~~~~~ ~~~~~ ~~~~ ~~~ ~~~ +0x05FE0000 ARM Boot Monitor 312 0 0 + + +Blocks of unknown type +====================== +Block Size Footer Type +~~~~~ ~~~~ ~~~~~~~~~~~ + 252 1 0x52420000 +boot Monitor > +</screen> + +This causes the last block of the flash to be initialized with the ARM +Boot Monitor ID, necessary for the Monitor to work properly. When +resetting the board now, it should automatically start RedBoot. If you +ever need to get into the ARM Boot Monitor again, reset the board +while pressing the SPACE key. + +</para></sect3> +--> + +</sect2> + +<sect2> +<title>Special RedBoot Commands </title> +<para>The <command>exec</command> command which allows the loading +and execution of Linux kernels, +is supported for this board (see <xref linkend="executing-programs">). The <command> +exec</command> parameters used for the AAED2000 are:</para> +<variablelist><varlistentry> +<term>-b <replaceable><addr></replaceable></term> +<listitem><para>Location Linux kernel was loaded to</para></listitem></varlistentry> +<varlistentry><term> +-l <replaceable><len></replaceable></term> +<listitem><para>Length of kernel</para></listitem></varlistentry> +<varlistentry><term> +-c <replaceable>"params"</replaceable></term> +<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> +<varlistentry><term>-r <replaceable><addr></replaceable></term> +<listitem><para>'initrd' ramdisk location</para></listitem></varlistentry> +<varlistentry><term>-s <replaceable><len></replaceable></term> +<listitem><para>Length of initrd ramdisk</para></listitem></varlistentry> +</variablelist> + +<para>The parameters for kernel image base and size are automatically +set after a load operation. So one way of starting the kernel would +be: + +<screen>RedBoot> <userinput>load -r -b 0x100000 zImage</userinput> +Raw file loaded 0x00100000-0x001a3d6c +RedBoot> exec -c "console=ttyAC0,38400" +Using base address 0x00100000 and length 0x000a3d6c +Uncompressing Linux..... +</screen> + +An image could also be put in flash and started directly: + +<screen>RedBoot> <userinput>exec -b 0x60040000 -l 0xc0000 -c "console=ttyAC0,38400"</userinput> +Uncompressing Linux..... +</screen> + +</para> + +</sect2> +<sect2> +<title>Memory Maps </title> +<para>The MMU page tables are located at 0x4000. <note><title>NOTE +</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note><programlisting>Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x01ffffff Flash +0x10000000 - 0x100fffff Ethernet +0x30000000 - 0x300fffff Board registers +0x40000000 - 0x4fffffff PCMCIA Slot (0) +0x50000000 - 0x5fffffff Compact Flash Slot (1) +0x80000000 - 0x800037ff I/O registers +0xb0060000 - 0xb00fffff On-chip SRAM +0xf0000000 - 0xfd3fffff SDRAM + +Virtual Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x01f7ffff Y Y SDRAM +0x01f80000 - 0x01ffffff Y Y SDRAM (used for LCD frame buffer) +0x10000000 - 0x100fffff N N Ethernet +0x30000000 - 0x300fffff N N Board registers +0x40000000 - 0x4fffffff N N PCMCIA Slot (0) +0x50000000 - 0x5fffffff N N Compact Flash Slot (1) +0x60000000 - 0x61ffffff N N Flash +0x80000000 - 0x800037ff N N I/O registers +0xf0000000 - 0xffffffff N N SDRAM (uncached) + +</programlisting></para> + +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=aaed +export ARCH_DIR=arm +export PLATFORM_DIR=arm9/aaed2000 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + + + +<?Pub _newpage> +<sect1 id="ebsa285"> +<title>ARM/StrongARM(SA110) Intel EBSA 285</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Intel StrongArm EBSA 285</primary><secondary>installing +and testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Intel StrongArm EBSA 285</secondary></indexterm>RedBoot +uses the single EBSA-285 serial port. The default serial port settings are +38400,8,N,1. If the EBSA-285 is used as a host on a PCI backplane, ethernet +is supported using an Intel PRO/100+ ethernet adapter. Management of +onboard flash is also supported.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation Method </title> +<para>A linux application is used to program the flash over the PCI bus. Sources +and build instructions for this utility are located in the RedBoot sources +in: <filename class="directory">packages/hal/arm/ebsa285/current/support/linux/safl_util</filename> +</para> +</sect2> +<sect2> +<title>Communication Channels </title> +<para>Serial, Intel PRO 10/100+ 82559 PCI ethernet card.</para> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>Physical and virtual mapping are mapped one to one on the EBSA-285 using +a first level page table located at address 0x4000. No second level tables +are used. <note><title>NOTE </title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note><programlisting>Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x01ffffff Y Y SDRAM +0x40000000 - 0x400fffff N N 21285 Registers +0x41000000 - 0x413fffff Y N flash +0x42000000 - 0x420fffff N N 21285 CSR Space +0x50000000 - 0x50ffffff Y Y Cache Clean +0x78000000 - 0x78ffffff N N Outbound Write Flush +0x79000000 - 0x7c0fffff N N PCI IACK/Config/IO +0x80000000 - 0xffffffff N Y PCI Memory </programlisting></para> +</sect2> +<sect2> +<title>Platform Resource Usage </title> +<para>Timer3 is used as a polled timer to provide timeout support for networking +and XModem file transfers.</para> +</sect2> +<!-- +<sect2> +<title>Building eCos Test Cases to run with old RedBoots</title> +<para>If using older versions of RedBoot, the default configuration for +EBSA-285 will send diagnostic output to the serial line only, not over an ethernet +connection. To allow eCos programs to use RedBoot to channel diagnostic output to +GDB whether connected by net or serial, enable the configuration option <programlisting> +CYGSEM_HAL_VIRTUAL_VECTOR_DIAG +"Do diagnostic IO via virtual vector table"</programlisting> located here +in the common HAL configuration tree: <programlisting>"eCos HAL" + "ROM monitor support" + "Enable use of virtual vector calling interface" + "Do diagnostic IO via virtual vector table"</programlisting>Other +than that, no special configuration is required to use RedBoot. </para> +<para>If you have been using built-in stubs to acquire support for thread-aware +debugging, you can still do that, but you must only use the serial device +for GDB connection and you must not enable the option mentioned above. However, +it is no longer necessary to do that to get thread-awareness; RedBoot is thread +aware.</para> +</sect2> +--> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=ebsa285 +export ARCH_DIR=arm +export PLATFORM_DIR=ebsa285 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="brutus"> +<title>ARM/StrongARM(SA1100) Intel Brutus</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Intel-SA1100 (Brutus)</primary><secondary>installing +and testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Intel SA1100 (Brutus)</secondary></indexterm>RedBoot +supports both board serial ports on the Brutus board. The default serial port +settings are 38400,8,N,1. flash management is not currently supported. </para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation Method </title> +<para>Device programmer is used to program socketed flash parts.</para> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>The first level page table is located at physical address 0xc0004000. +No second level tables are used. + +<note><title>NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> + +</note><programlisting>Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x000fffff Boot ROM +0x08000000 - 0x083fffff Application flash +0x10000000 - 0x100fffff SRAM +0x18000000 - 0x180fffff Chip Select 3 +0x20000000 - 0x3fffffff PCMCIA +0x80000000 - 0xbfffffff SA-1100 Internal Registers +0xc0000000 - 0xc7ffffff DRAM Bank 0 +0xc8000000 - 0xcfffffff DRAM Bank 1 +0xd0000000 - 0xd7ffffff DRAM Bank 2 +0xd8000000 - 0xdfffffff DRAM Bank 3 +0xe0000000 - 0xe7ffffff Cache Clean + + +Virtual Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x003fffff Y Y DRAM Bank 0 +0x00400000 - 0x007fffff Y Y DRAM Bank 1 +0x00800000 - 0x00bfffff Y Y DRAM Bank 2 +0x00c00000 - 0x00ffffff Y Y DRAM Bank 3 +0x08000000 - 0x083fffff Y Y Application flash +0x10000000 - 0x100fffff Y N SRAM +0x20000000 - 0x3fffffff N N PCMCIA +0x40000000 - 0x400fffff Y Y Boot ROM +0x80000000 - 0xbfffffff N N SA-1100 Internal Registers +0xe0000000 - 0xe7ffffff Y Y Cache Clean</programlisting></para> +</sect2> +<sect2> +<title>Platform Resource Usage </title> +<para> +The SA11x0 OS timer is used as a polled timer to provide timeout +support for XModem file transfers.</para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=brutus +export ARCH_DIR=arm +export PLATFORM_DIR=sa11x0/brutus +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="sa1100mm"> +<title>ARM/StrongARM(SA1100) Intel SA1100 Multimedia Board </title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Intel SA1100 Multimedia Board</primary><secondary> +installing and testing</secondary></indexterm><indexterm><primary>installing +and testing</primary><secondary>Intel SA1100 Multimedia Board</secondary> +</indexterm>RedBoot supports both board serial ports. The default serial port +settings are 38400,8,N,1. flash management is also supported.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> +</sect2> + +<sect2> +<title>Initial Installation Method </title> +<para>A device programmer is used to program socketed flash parts.</para> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps </title> +<para>The first level page table is located at physical address 0xc0004000. +No second level tables are used.<note><title>NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note><programlisting>Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x000fffff Boot flash +0x08000000 - 0x083fffff Application flash +0x10000000 - 0x107fffff SA-1101 Board Registers +0x18000000 - 0x180fffff Ct8020 DSP +0x18400000 - 0x184fffff XBusReg +0x18800000 - 0x188fffff SysRegA +0x18c00000 - 0x18cfffff SysRegB +0x19000000 - 0x193fffff Spare CPLD A +0x19400000 - 0x197fffff Spare CPLD B +0x20000000 - 0x3fffffff PCMCIA +0x80000000 - 0xbfffffff SA1100 Internal Registers +0xc0000000 - 0xc07fffff DRAM Bank 0 +0xe0000000 - 0xe7ffffff Cache Clean +Virtual Address Range C B Description + + +----------------------- - - ---------------------------------- +0x00000000 - 0x007fffff Y Y DRAM Bank 0 +0x08000000 - 0x083fffff Y Y Application flash +0x10000000 - 0x100fffff N N SA-1101 Registers +0x18000000 - 0x180fffff N N Ct8020 DSP +0x18400000 - 0x184fffff N N XBusReg +0x18800000 - 0x188fffff N N SysRegA +0x18c00000 - 0x18cfffff N N SysRegB +0x19000000 - 0x193fffff N N Spare CPLD A +0x19400000 - 0x197fffff N N Spare CPLD B +0x20000000 - 0x3fffffff N N PCMCIA +0x50000000 - 0x500fffff Y Y Boot flash +0x80000000 - 0xbfffffff N N SA1100 Internal Registers +0xc0000000 - 0xc07fffff N Y DRAM Bank 0 +0xe0000000 - 0xe7ffffff Y Y Cache Clean</programlisting></para> +</sect2> +<sect2> +<title>Platform Resource Usage </title> +<para> The SA11x0 OS timer is used as a polled timer to provide timeout support +for XModem file transfers.</para> +</sect2><sect2> + +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=sa1100mm +export ARCH_DIR=arm +export PLATFORM_DIR=sa11x0/sa1100mm +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + + + +<?Pub _newpage> +<sect1 id="assabet"> +<title>ARM/StrongARM(SA1110) Intel SA1110 (Assabet) </title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Intel SA1110 (Assabet)</primary><secondary>installing +and testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Intel SA1110 (Assabet)</secondary></indexterm>RedBoot +supports the board serial port and the compact flash ethernet port. The default +serial port settings are 38400,8,N,1. RedBoot also supports flash management +on the Assabet. </para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> +</sect2> +<sect2> +<title>Initial Installation Method</title> +<para>A Windows or Linux utility is used to program flash over parallel port +driven JTAG interface. See board documentation for details on in situ flash +programming. </para> +<para>The flash parts are also socketed and may be programmed in a suitable +device programmer.</para> +</sect2> +<sect2> +<title>Special RedBoot Commands</title> +<para>None.</para> +</sect2> +<sect2> +<title>Memory Maps</title> +<para>The first level page table is located at physical address 0xc0004000. +No second level tables are used.<note><title>NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note><programlisting>Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x07ffffff flash +0x08000000 - 0x0fffffff SA-1111 Board flash +0x10000000 - 0x17ffffff Board Registers +0x18000000 - 0x1fffffff Ethernet +0x20000000 - 0x2fffffff SA-1111 Board PCMCIA +0x30000000 - 0x3fffffff Compact Flash +0x40000000 - 0x47ffffff SA-1111 Board +0x48000000 - 0x4bffffff GFX +0x80000000 - 0xbfffffff SA-1110 Internal Registers +0xc0000000 - 0xc7ffffff DRAM Bank 0 +0xc8000000 - 0xcfffffff DRAM Bank 1 +0xd0000000 - 0xd7ffffff DRAM Bank 2 +0xd8000000 - 0xdfffffff DRAM Bank 3 +0xe0000000 - 0xe7ffffff Cache Clean + + +Virtual Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x01ffffff Y Y DRAM Bank 0 +0x08000000 - 0x0fffffff Y Y SA-1111 Board flash +0x10000000 - 0x17ffffff N N Board Registers +0x18000000 - 0x1fffffff N N Ethernet +0x20000000 - 0x2fffffff N N SA-1111 Board PCMCIA +0x30000000 - 0x3fffffff N N Compact Flash +0x40000000 - 0x47ffffff N N SA-1111 Board +0x48000000 - 0x4bffffff N N GFX +0x50000000 - 0x57ffffff Y Y flash +0x80000000 - 0xbfffffff N N SA-1110 Internal Registers +0xc0000000 - 0xc1ffffff N Y DRAM Bank 0 +0xe0000000 - 0xe7ffffff Y Y Cache Clean +</programlisting></para> +</sect2> +<sect2> +<title>Platform Resource Usage </title> +<para>The SA11x0 OS timer is used as a polled timer to provide timeout support +for network and XModem file transfers.</para> +</sect2><sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=assabet +export ARCH_DIR=arm +export PLATFORM_DIR=sa11x0/assabet +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="nano"> +<title>ARM/StrongARM(SA11X0) Bright Star Engineering commEngine and nanoEngine</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>commEngine</primary><secondary>installing and testing +</secondary></indexterm><indexterm><primary>nanoEngine</primary><secondary> +installing and testing</secondary></indexterm><indexterm><primary>installing +and testing</primary><secondary>commEngine</secondary></indexterm><indexterm> +<primary>installing and testing</primary><secondary>nanoEngine</secondary> +</indexterm>RedBoot supports a serial port and the built in ethernet port +for communication and downloads. The default serial port settings are 38400,8,N,1. +RedBoot runs from and supports flash management for the system flash +region.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>POST</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the first free flash block + at 0x40000.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation</title> +<para>Unlike other targets, the nanoEngine comes equipped with boot firmware +which you cannot modify. See chapter 5, "nanoEngine Firmware" of the <citetitle> +nanoEngine Hardware Reference Manual</citetitle> (we refer to "July 17, 2000 +Rev 0.6") from Bright Star Engineering. </para> +<para>Because of this, eCos, and therefore Redboot, only supports a +special configuration of the ROM mode, starting at offset 0x40000 in +the flash.</para> +<para>Briefly, the POST-configuration RedBoot image lives in flash following the +BSE firmware. The BSE firmware is configured, using its standard <command> +bootcmd</command> command, to run RedBoot at startup. +</para> +</sect2> +<sect2> +<title>Download Instructions</title> +<para>You can perform the initial load of the POST-configuration RedBoot image into +flash using the BSE firmware's <command>load</command> command. +This will load a binary file, using TFTP, and program it into flash in one +operation. Because no memory management is used in the BSE firmware, flash +is mapped from address zero upwards, so the address for the RedBoot POST image +is 0x40000. You must use the binary version of RedBoot for this, +<filename>redboot-post.bin</filename>.</para> + +<para>This assumes you have set up the other BSE firmware config +parameters such that it can communicate over your network to your TFTP +server. +<screen>><userinput>load redboot-post.bin 40000</userinput> +loading ... erasing blk at 00040000 +erasing blk at 00050000 +94168 bytes loaded cksum 00008579 +done +> +> <userinput>set bootcmd "go 40000"</userinput> +> <userinput>get</userinput> +myip = 10.16.19.198 +netmask = 255.255.255.0 +eth = 0 +gateway = 10.16.19.66 +serverip = 10.16.19.66 +bootcmd = go 40000 +></screen> + +<note><title>NOTE</title> +<para>the BSE firmware runs its serial IO at 9600 Baud; RedBoot runs instead +at 38400 Baud. You must select the right baud rate in your terminal program +to be able to set up the BSE firmware.</para> +</note> + +After a reset, the BSE firmware will print + +<screen>Boot: BSE 2000 Sep 12 2000 14:00:30 +autoboot: "go 40000" [hit ESC to abort]</screen> + +and then RedBoot starts, switching to 38400 Baud.</para> + +<para>Once you have installed a bootable RedBoot in the system in this +manner, we advise re-installing using the generic method described in +<xref linkend="updating-redboot"> in order that the Flash Image System +contains an appropriate description of the flash entries.</para> +</sect2> +<sect2> +<title>Cohabiting with POST in Flash</title> +<para>The configuration file named <filename>redboot_POST.ecm</filename> +configures RedBoot to build for execution at address 0x50040000 (or, during +bootup, 0x00040000). This is to allow power-on self-test (POST) code or immutable +firmware to live in the lower addresses of the flash and to run before RedBoot +gets control. The assumption is that RedBoot will be entered at its base address +in physical memory, that is 0x00040000.</para> + +<para>Alternatively, for testing, you can call it in an already running system +by using <userinput>go 0x50040040</userinput> at another RedBoot prompt, or +a branch to that address. The address is where the reset vector +points. It is reported by RedBoot's <command>load</command> command +and listed +by the <command>fis list</command> command, amongst other +places.</para> + +<para>Using the POST configuration enables a normal config option which causes +linking and initialization against memory layout files called "...post..." +rather than "...rom..." or "...ram..." in the <filename class="directory">include/pkgconf +</filename> directory. Specifically:<literallayout><filename>include/pkgconf/mlt_arm_sa11x0_nano_post.h</filename> +<filename>include/pkgconf/mlt_arm_sa11x0_nano_post.ldi</filename> +<filename>include/pkgconf/mlt_arm_sa11x0_nano_post.mlt</filename></literallayout> + +It is these you should edit if you wish to move the execution address +from 0x50040000 in the POST configuration. Startup mode naturally +remains ROM in this configuration.</para> + +<para>Because the nanoEngine contains immutable boot firmware at the start +of flash, RedBoot for this target is configured to reserve that area in the +Flash Image System, and to create by default an entry for the POST +mode RedBoot. +<screen> +RedBoot> <userinput>fis list</userinput> +Name FLASH addr Mem addr Length Entry point +(reserved) 0x50000000 0x50000000 0x00040000 0x00000000 +RedBoot[post] 0x50040000 0x00100000 0x00020000 0x50040040 +RedBoot config 0x503E0000 0x503E0000 0x00010000 0x00000000 +FIS directory 0x503F0000 0x503F0000 0x00010000 0x00000000 +RedBoot> +</screen> +The entry "(reserved)" ensures that the FIS cannot attempt +to overwrite the BSE firmware, thus ensuring that the board remains bootable +and recoverable even after installing a broken RedBoot image.</para> +</sect2> +<sect2> +<title>Special RedBoot Commands</title> +<para>The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers +installed, but these have no associated serial EEPROM in which to record their +Ethernet Station Address (ESA, or MAC address). The BSE firmware records an +ESA for the device it uses, but this information is not available to RedBoot; +we cannot share it.</para> +<para>To keep the ESAs for the two ethernet interfaces, two new items of RedBoot +configuration data are introduced. You can list them with the RedBoot command <command> +fconfig -l</command> thus: +<screen> +RedBoot> <userinput>fconfig -l</userinput> +Run script at boot: false +Use BOOTP for network configuration: false +Local IP address: 10.16.19.91 +Default server IP address: 10.16.19.66 +Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99 +Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A +GDB connection port: 9000 +Network debug at boot time: false +RedBoot></screen> + +You should set them before running RedBoot or eCos applications with +the board connected to a network. The <command>fconfig </command> +command can be used as for any configuration data item; the entire ESA +is entered in one line.</para> +</sect2> +<sect2> +<title>Memory Maps</title> +<para>The first level page table is located at physical address 0xc0004000. + No second level tables are used. <note><title>NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note><programlisting>Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x003fffff 4Mb FLASH (nCS0) +0x18000000 - 0x18ffffff Internal PCI bus - 2 x i82559 ethernet +0x40000000 - 0x4fffffff External IO or PCI bus +0x80000000 - 0xbfffffff SA-1110 Internal Registers +0xc0000000 - 0xc7ffffff DRAM Bank 0 - 32Mb SDRAM +0xc8000000 - 0xcfffffff DRAM Bank 1 - empty +0xe0000000 - 0xe7ffffff Cache Clean + +Virtual Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x001fffff Y Y DRAM - 8Mb to 32Mb +0x18000000 - 0x180fffff N N Internal PCI bus - 2 x i82559 ethernet +0x40000000 - 0x4fffffff N N External IO or PCI bus +0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) +0x80000000 - 0xbfffffff N N SA-1110 Internal Registers +0xc0000000 - 0xc0ffffff N Y DRAM Bank 0: 8 or 16Mb +0xc8000000 - 0xc8ffffff N Y DRAM Bank 1: 8 or 16Mb or absent +0xe0000000 - 0xe7ffffff Y Y Cache Clean</programlisting> +</para> + +<para>The ethernet devices use a "PCI window" to communicate with the CPU. +This is 1Mb of SDRAM which is shared with the ethernet devices that are on +the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI +accesses see correct data in the correct order. By default it is configured +to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be +modified, and indeed must be, if less than 32Mb of SDRAM is installed, via +the memory layout tool, or by moving the section <computeroutput>__pci_window +</computeroutput> referred to by symbols <computeroutput>CYGMEM_SECTION_pci_window* +</computeroutput> in the linker script. </para> +<para>Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM +bank 0, the code can cope with any of these combinations also; "2 x " in this +context means one device in each DRAM Bank. <literallayout>1 x 8Mb = 8Mb 2 x 8Mb = 16Mb +1 x 16Mb = 16Mb 2 x 16Mb = 32Mb</literallayout>All are programmed the same +in the memory controller. </para> +<para>Startup code detects which is fitted and programs the memory map accordingly. +If the device(s) is 8Mb, then there are gaps in the physical memory map, because +a high order address bit is not connected. The gaps are the higher 2Mb out +of every 4Mb.</para> + +<para> The SA11x0 OS timer is used as a polled timer to provide timeout +support within RedBoot.</para> +</sect2> +<sect2> +<title>Nano Platform Port</title> +<para>The nano is in the set of SA11X0-based platforms. It uses the arm architectural +HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components + <literallayout>CYGPKG_HAL_ARM hal/arm/arch/ +CYGPKG_HAL_ARM_SA11X0 hal/arm/sa11x0/var +CYGPKG_HAL_ARM_SA11X0_NANO hal/arm/sa11x0/nano</literallayout> respectively. + </para> +<para>The target name is "nano" which includes all these, plus the ethernet +driver packages, flash driver, and so on.</para> +</sect2> +<sect2> +<title>Ethernet Driver</title> +<para>The ethernet driver is in two parts: </para> +<para>A generic ether driver for Intel i8255x series devices, specifically +the i82559, is <computeroutput>devs/eth/intel/i82559</computeroutput>. Its +package name is <computeroutput>CYGPKG_DEVS_ETH_INTEL_I82559</computeroutput>. + </para> +<para>The platform-specific ether driver is <computeroutput>devs/eth/arm/nano +</computeroutput>. Its package is <computeroutput>CYGPKG_DEVS_ETH_ARM_NANO +</computeroutput>. This tells the generic driver the address in IO memory +of the chip, for example, and other configuration details. This driver picks +up the ESA from RedBoot's configuration data - unless configured to use a +static ESA in the usual manner. </para> +</sect2><sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=nano +export ARCH_DIR=arm +export PLATFORM_DIR=sa11x0/nano +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="ipaq"> +<title>ARM/StrongARM(SA11X0) Compaq iPAQ PocketPC</title> +<indexterm><primary>Compaq iPAQ PocketPC</primary><secondary>installing and +testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Compaq iPAQ PocketPC</secondary></indexterm> +<sect2> +<title>Overview</title> +<para>RedBoot supports the serial port via cradle or cable, and Compact Flash +ethernet cards if fitted for communication and downloads. The LCD touchscreen +may also be used for the console, although by default RedBoot will switch +exclusively to one channel once input arrives. </para> +<para>The default serial port settings are 38400,8,N,1. RedBoot runs from +and supports flash management for the system flash region. </para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> + <row> + <entry>WinCE</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM, started from + <application>OSloader</application>.</entry> + <entry>redboot_WinCE.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + + + +</sect2> +<sect2> +<title>Initial Installation</title> +<para>RedBoot ROM and WinCE mode images are needed by the installation process. +</para> +<sect3> +<title>Installing RedBoot on the iPAQ using Windows/CE</title> +<para> +The Windows/CE environment originally shipped with the iPAQ contains a hidden +mini-loader, sometimes referred to as the "Parrot" loader. This loader can +be started by holding down the action button (the joypad) while resetting +the unit or when powering on. At this point, a blue bird will appear on +the LCD screen. Also at this point, a simple loader can be accessed over the +serial port at 115200/8N1. Using this loader, the contents of the iPAQ flash +memory can be saved to a Compact Flash memory card. +<note><title>NOTE</title><para>We have only tested this operation with a 32Mbyte CF memory card. +Given that the backup will take 16MBytes + 1KByte, something more than a 16MByte +card will be required.</para></note> +</para> +<para> +Use the "r2c" command to dump Flash contents to the CF memory card. Once this +completes, RedBoot can be installed with no fear since the Parrot loader can +be used to restore the Flash contents at a later time. +</para> +<para> +If you expect to completely recover the state of the iPAQ Win/CE environment, then +HotSync should be run to backup all "RAM" files as well before installing RedBoot. +</para> +<para>The next step in installing RedBoot on the iPAQ actually involves Windows/CE, +which is the native environment on the unit. Using WinCE, you need to +install an application which will run a RAM based version of RedBoot. Once +this is installed and running, RedBoot can be used to update the flash with +a native/ROM version of RedBoot. <itemizedlist> +<listitem><para>Using ActiveSync, copy the file OSloader to your iPAQ. </para> +</listitem> +<listitem><para>Using ActiveSync, copy the file redboot_WinCE.bin to the iPAQ +as bootldr in its root directory. Note: this is not the top level folder +displayed by Windows (Mobile Device), but rather the 'My Pocket PC' folder +within it.</para> +</listitem> +<listitem><para>Execute OSloader. If you didn't create a shortcut, then you +will have to poke around for it using the WinCE file explorer.</para> +</listitem> +<listitem><para>Choose the <guimenuitem>Tools->BootLdr->Run after loading +from file</guimenuitem> menu item. </para> +</listitem> +</itemizedlist>At this point, the RAM based version of RedBoot should be running. + You should be able to return to this point by just executing the last two +steps of the previous process if necessary.</para> +</sect3> +<sect3> +<title>Installing RedBoot on the iPAQ - using the Compaq boot loader</title> +<para>This method of installation is no longer supported. +If you have previously installed either the Compaq boot loader or older +versions of RedBoot, restore the Win/CE environment and proceed as outlined +above. +</para> +</sect3> +<sect3 id="setting-up-and-testing-redboot"> +<title>Setting up and testing RedBoot</title> +<para>When RedBoot first comes up, it will want to initialize its LCD touch +screen parameters. It does this by displaying a keyboard graphic and asks +you to press certain keys. Using the stylus, press and hold until the prompt +is withdrawn. When you lift the stylus, RedBoot will continue with the next +calibration. </para> +<para>Once the LCD touchscreen has been calibrated, RedBoot will start. The +calibration step can be skipped by pressing the <guibutton>return/abort</guibutton> +button on the unit (right most button with a curved arrow icon). Additionally, +the unit will assume default values if the screen is not touched within about +15 seconds. </para> +<para>Once RedBoot has started, you should get information similar to this +on the LCD screen. It will also appear on the serial port at 38400,8,N,1. + +<screen>RedBoot(tm) bootstrap and debug environment [ROM] +Non-certified release, version UNKNOWN - built 06:17:41, Mar 19 2001 +Platform: Compaq iPAQ Pocket PC (StrongARM 1110) + +Copyright (C) 2000, 2001, Red Hat, Inc. + +RAM: 0x00000000-0x01fc0000, 0x0001f200-0x01f70000 available +FLASH: 0x50000000 - 0x51000000, 64 blocks of 0x00040000 bytes +each.</screen> + +Since the LCD touchscreen is only 30 characters wide, some of this +data will be off the right hand side of the display. The joypad may be +used to pan left and right in order to see the full lines. </para> +<para>If you have a Compact Flash ethernet card, RedBoot should find +it. You'll need to have BOOTP enabled for this unit (see your +sysadmin for details). If it does, it will print a message like: + +<screen>... Waiting for network card: .Ready! +Socket Communications Inc: CF+ LPE Revision E 08/04/99 +IP: 192.168.1.34, Default server: 192.168.1.101</screen></para> +</sect3> + +<sect3 id="ipaq-install-rb-permanently"> +<title>Installing RedBoot permanently</title> +<para>Once you are satisfied with the setup and that RedBoot is operating +properly in your environment, you can set up your iPAQ unit to have RedBoot +be the bootstrap application. + +<caution><title>CAUTION</title> +<para>This step will destroy your Windows/CE environment.</para> +<para>Before you take this step, it is strongly recommended you save your WinCE FLASH contents +as outlined above using the "parrot" loader, or +by using the Compaq OSloader:<itemizedlist> + +<listitem><para>Using OSloader on the iPAQ, select the <guimenuitem>Tools->Flash->Save +to files...</guimenuitem>. menu item.</para> +</listitem> + +<listitem><para>Four (4) files, 4MB each in size will be created.</para> +</listitem> + +<listitem><para>After each file is created, copy the file to your computer, +then delete the file from the iPAQ to make room in the WinCE ramdisk for the +next file.</para></listitem> +</itemizedlist></para> + +</caution>You will need to download the version of RedBoot designed as the +ROM bootstrap. Then install it permanently using these commands: + <screen> +RedBoot> <userinput>lo -r -b 0x100000 redboot_ROM.bin</userinput> +RedBoot> <userinput>fi loc -f 0x50000000 -l 0x40000</userinput> +RedBoot> <userinput>fis init</userinput> +RedBoot> <userinput>fi unl -f 0x50040000 -l 0x40000</userinput> +RedBoot> <userinput>fi cr RedBoot -b 0x100000</userinput> +RedBoot> <userinput>fi loc -f 0x50040000 -l 0x40000</userinput> +RedBoot> <userinput>reset</userinput> +</screen> + +<warning><title>WARNING</title> +<para>You must type these commands exactly! Failure to do so may render your +iPAQ totally useless. Once you've done this, RedBoot should come up every +time you reset.</para> +</warning></para> +</sect3> + +<sect3> +<title>Restoring Windows/CE</title> +<para>To restore Windows/CE from the backup taken in <xref linkend="ipaq-install-rb-permanently">, +visit <ulink url="http://www.handhelds.org/projects/wincerestoration.html">http://www.handhelds.org/projects/wincerestoration.html</ulink> +for directions. +</para> +</sect3></sect2> + +<sect2> +<title>Additional commands</title> +<para>The <command>exec</command> command which allows the loading +and execution of Linux kernels, +is supported for this board (see <xref linkend="executing-programs">). The <command> +exec</command> parameters used for the iPAQ are:</para> +<variablelist><varlistentry> +<term>-b <replaceable><addr></replaceable></term> +<listitem><para>Location Linux kernel was loaded to</para></listitem></varlistentry> +<varlistentry><term> +-l <replaceable><len></replaceable></term> +<listitem><para>Length of kernel</para></listitem></varlistentry> +<varlistentry><term> +-c <replaceable>"params"</replaceable></term> +<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> +<varlistentry><term>-r <replaceable><addr></replaceable></term> +<listitem><para>'initrd' ramdisk location</para></listitem></varlistentry> +<varlistentry><term>-s <replaceable><len></replaceable></term> +<listitem><para>Length of initrd ramdisk</para></listitem></varlistentry> +</variablelist> +<para>Linux kernels may be run on the iPAQ using the sources from the anonymous +CVS repository at the Handhelds project (<ulink url="http://www.handhelds.org/"> +http://www.handhelds.org/</ulink>) with +the <filename>elinux.patch</filename> patch file applied. This file can be +found in the +<filename>misc/</filename> subdirectory of the iPAQ platform HAL in the +RedBoot sources, normally +<filename>hal/arm/sa11x0/ipaq/<replaceable>VERSION</replaceable>/misc/</filename> + </para> +<para> +On the iPAQ (and indeed all SA11x0 platforms), Linux expects to be loaded +at address 0xC0008000 and the entry point is also at 0xC0008000. +</para> + +</sect2> +<sect2> +<title>Memory Maps</title> +<para>RedBoot sets up the following memory map on the iPAQ: The first level +page table is located at physical address 0xC0004000. No second level tables +are used. <note><title>NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note> <programlisting>Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x01ffffff 16Mb to 32Mb FLASH (nCS0) [organized as below] + 0x000000 - 0x0003ffff Parrot Loader + 0x040000 - 0x0007ffff RedBoot + 0xf80000 - 0x00fbffff Fconfig data + 0xfc0000 - 0x00ffffff FIS directory +0x30000000 - 0x3fffffff Compact Flash +0x48000000 - 0x4bffffff iPAQ internal registers +0x80000000 - 0xbfffffff SA-1110 Internal Registers +0xc0000000 - 0xc1ffffff DRAM Bank 0 - 32Mb SDRAM +0xe0000000 - 0xe7ffffff Cache Clean + + +Virtual Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x01ffffff Y Y DRAM - 32Mb +0x30000000 - 0x3fffffff N N Compact Flash +0x48000000 - 0x4bffffff N N iPAQ internal registers +0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) +0x80000000 - 0xbfffffff N N SA-1110 Internal Registers +0xc0000000 - 0xc1ffffff N Y DRAM Bank 0: 32Mb +0xe0000000 - 0xe7ffffff Y Y Cache Clean </programlisting> </para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=ipaq +export ARCH_DIR=arm +export PLATFORM_DIR=sa11x0/ipaq +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2></sect1> + +<?Pub _newpage> +<sect1 id="cerfcube"> +<title>ARM/StrongARM(SA11X0) Intrinsyc CerfCube</title> +<indexterm><primary>Intrinsyc CerfCube</primary><secondary>installing and +testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Intrinsyc CerfCube</secondary></indexterm> +<sect2> +<title>Overview</title> +<para>RedBoot supports the serial port and the builtin +ethernet connection for communication and downloads. +</para> +<para>The default serial port settings are 38400,8,N,1. RedBoot runs from +and supports flash management for the system flash region. </para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + + +</sect2> +<sect2> +<title>Initial Installation</title> +<para> +The original boot loader supplied with the CerfCube can be used to install +RedBoot. Connect to the device using a serial port at 38400/8N1. +Copy the binary RedBoot ROM mode image to an available TFTP server. +Issue these commands to the Instrinsyc loader: +<screen> +<userinput>download tftp:<replaceable>x.x.x.x</replaceable> redboot_ROM.bin 0xc0000000</userinput> +<userinput>flashloader 0x00000000 0xc0000000 0x20000</userinput> +</screen> +where <replaceable>x.x.x.x</replaceable> is the IP address of the TFTP +server. +<note> +<title>NOTE</title> +<para> +Other installation methods may be available via the Intrinsyc loader. +Contact Intrinsyc for details. +</para> +</note> +</para> +</sect2> +<sect2> +<title>Additional commands</title> +<para>The <command>exec</command> command which allows the loading +and execution of Linux kernels, +is supported for this board (see <xref linkend="executing-programs">). The <command> +exec</command> parameters used for the CerfCube are:</para> +<variablelist><varlistentry> +<term>-b <replaceable><addr></replaceable></term> +<listitem><para>Location Linux kernel was loaded to</para></listitem></varlistentry> +<varlistentry><term> +-l <replaceable><len></replaceable></term> +<listitem><para>Length of kernel</para></listitem></varlistentry> +<varlistentry><term> +-c <replaceable>"params"</replaceable></term> +<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> +<varlistentry><term>-r <replaceable><addr></replaceable></term> +<listitem><para>'initrd' ramdisk location</para></listitem></varlistentry> +<varlistentry><term>-s <replaceable><len></replaceable></term> +<listitem><para>Length of initrd ramdisk</para></listitem></varlistentry> +</variablelist> + +</sect2> +<sect2> +<title>Memory Maps</title> +<para>RedBoot sets up the following memory map on the CerfCube: The first level +page table is located at physical address 0xC0004000. No second level tables +are used. <note><title>NOTE</title> +<para>The virtual memory maps in this section use a C and B column to indicate +whether or not the region is cached (C) or buffered (B).</para> +</note> <programlisting>Physical Address Range Description +----------------------- ---------------------------------- +0x00000000 - 0x01ffffff 16Mb to 32Mb FLASH (nCS0) [organized as below] + 0x000000 - 0x0001ffff RedBoot + 0x020000 - 0x0003ffff RedBoot [RAM version] + 0xfc0000 - 0x00fdffff Fconfig data + 0xfe0000 - 0x00ffffff FIS directory +0x0f000000 - 0x0fffffff Onboard ethernet +0x10000000 - 0x17ffffff CerfCube internal registers +0x20000000 - 0x3fffffff PCMCIA / Compact Flash +0x80000000 - 0xbfffffff SA-1110 Internal Registers +0xc0000000 - 0xc1ffffff DRAM Bank 0 - 32Mb SDRAM +0xe0000000 - 0xe7ffffff Cache Clean + + +Virtual Address Range C B Description +----------------------- - - ---------------------------------- +0x00000000 - 0x01ffffff Y Y DRAM - 32Mb +0x08000000 - 0x0fffffff N N Onboard ethernet controller +0x10000000 - 0x17ffffff N N CerfCube internal registers +0x20000000 - 0x3fffffff N N PCMCIA / Compact Flash +0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) +0x80000000 - 0xbfffffff N N SA-1110 Internal Registers +0xc0000000 - 0xc1ffffff N Y DRAM Bank 0: 32Mb +0xe0000000 - 0xe7ffffff Y Y Cache Clean </programlisting> </para> +</sect2> + +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=cerf +export ARCH_DIR=arm +export PLATFORM_DIR=sa11x0/cerf +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2></sect1> + + <sect1 id="iq80310"> -<title>Cyclone IQ80310</title> +<title>ARM/Xscale Cyclone IQ80310</title> <sect2> <title>Overview</title> <para><indexterm><primary>Cyclone IQ80310</primary><secondary>installing and @@ -13,7 +2619,7 @@ both serial ports and the built-in ether The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the onboard 8MB flash.</para> -<para>The following RedBoot mode configurations are supported: +<para>The following RedBoot configurations are supported: <informaltable frame="all"> <tgroup cols="4" colsep="1" rowsep="1" align="left"> @@ -81,11 +2687,11 @@ in the flash boot sector, use the manufa the ROMA mode image at address 0x40000. </para> <para>After booting the initial installation of RedBoot, this warning may -be printed: <programlisting>flash configuration checksum error or invalid key -</programlisting>This is normal, and indicates that the flash must be configured +be printed: <screen>flash configuration checksum error or invalid key +</screen>This is normal, and indicates that the flash must be configured for use by RedBoot. Even if the above message is not printed, it may be a good idea to reinitialize the flash anyway. Do this with the <command> -fis</command> command: <programlisting>RedBoot> <userinput>fis init</userinput> +fis</command> command: <screen>RedBoot> <userinput>fis init</userinput> About to initialize [format] flash image system - continue (y/n)? <userinput>y</userinput> *** Initialize flash Image System Warning: device contents not erased, some blocks may not be usable @@ -105,7 +2711,7 @@ Followed by the fconfig command: ... Unlock from 0x007c0000-0x007e0000: . ... Erase from 0x007c0000-0x007e0000: . ... Program from 0xa0013018-0xa0013418 at 0x007c0000: . - ... Lock from 0x007c0000-0x007e0000: .</programlisting></para> + ... Lock from 0x007c0000-0x007e0000: .</screen></para> <note><para>When later updating RedBoot in situ, it is important to use a matching ROM and RAM mode pair of images. So use either RAM/ROM @@ -115,10 +2721,10 @@ or RAMA/ROMA images. Do not mix them.</p <sect2> <title>Error codes</title> <para>RedBoot uses the two digit LED display to indicate errors during board -initialization. Possible error codes are: <programlisting>88 - Unknown Error +initialization. Possible error codes are: <literallayout>88 - Unknown Error 55 - I2C Error FF - SDRAM Error -01 - No Error </programlisting></para> +01 - No Error</literallayout></para> </sect2> <sect2> <title>Using RedBoot with ARM Bootloader </title> @@ -134,7 +2740,7 @@ positions are used by the ARM firmware a <para>A special RedBoot command, <command>diag</command>, is used to access a set of hardware diagnostics provided by the board manufacturer. To access the diagnostic menu, enter diag at the RedBoot prompt: -<programlisting> +<screen> RedBoot> <userinput>diag</userinput> Entering Hardware Diagnostics - Disabling Data Cache! 1 - Memory Tests @@ -153,7 +2759,7 @@ 13 - i960Rx/303 PCI Interrupt Test 14 - Internal Timer Test 15 - GPIO Test 0 - quit Enter the menu item number (0 to quit): -</programlisting> +</screen> Tests for various hardware subsystems are provided, and some tests require special hardware in order to execute normally. The Ethernet Configuration item may be used to set the board ethernet address.</para> @@ -344,7 +2950,7 @@ for networking and XModem file transfers <?Pub _newpage> <sect1 id="iq80321"> -<title>Intel IQ80321</title> +<title>ARM/Xscale Intel IQ80321</title> <sect2> <title>Overview</title> <para><indexterm><primary>Intel IQ80321</primary><secondary>installing and @@ -354,7 +2960,7 @@ the serial port and the built-in etherne The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the onboard 8MB flash.</para> -<para>The following RedBoot mode configurations are supported: +<para>The following RedBoot configurations are supported: <informaltable frame="all"> <tgroup cols="4" colsep="1" rowsep="1" align="left"> @@ -399,11 +3005,11 @@ 0x00000000 using the DOS utility. </para> <para>After booting the initial installation of RedBoot, this warning may -be printed: <programlisting>flash configuration checksum error or invalid key -</programlisting>This is normal, and indicates that the flash must be configured +be printed: <screen>flash configuration checksum error or invalid key +</screen>This is normal, and indicates that the flash must be configured for use by RedBoot. Even if the above message is not printed, it may be a good idea to reinitialize the flash anyway. Do this with the <command> -fis</command> command: <programlisting>RedBoot> <userinput>fis init</userinput> +fis</command> command: <screen>RedBoot> <userinput>fis init</userinput> About to initialize [format] FLASH image system - continue (y/n)? <userinput>y</userinput> *** Initialize FLASH Image System Warning: device contents not erased, some blocks may not be usable @@ -411,7 +3017,7 @@ About to initialize [format] FLASH image ... Erase from 0xf07e0000-0xf0800000: . ... Program from 0x01ddf000-0x01ddf400 at 0xf07e0000: . ... Lock from 0xf07e0000-0xf0800000: . -</programlisting></para></sect2> +</screen></para></sect2> <sect2> <title>Switch Settings</title> <para>The 80321 board is highly configurable through a number of switches and jumpers. @@ -453,7 +3059,7 @@ configuration: <para>RedBoot uses the two digit LED display to indicate status during board initialization. Possible codes are:</para> -<programlisting width=72> +<literallayout width=72> LED Actions ------------------------------------------------------------- Power-On/Reset @@ -483,9 +3089,9 @@ 94 Read remainder of EEPROM data. An error will result in one of the following error codes on the LEDs: - 77 BAD EEPROM checksum - 55 I2C protocol error - FF bank size error + 77 BAD EEPROM checksum + 55 I2C protocol error + FF bank size error A5 Setup DDR memory interface A6 @@ -533,14 +3139,14 @@ A2 Run through static constructors A1 Start up the eCos kernel or RedBoot -</programlisting> +</literallayout> </sect2> <sect2> <title>Special RedBoot Commands </title> <para>A special RedBoot command, <command>diag</command>, is used to access a set of hardware diagnostics. To access the diagnostic menu, enter <command>diag</command> at the RedBoot prompt: -<programlisting> +<screen> RedBoot> <userinput>diag</userinput> Entering Hardware Diagnostics - Disabling Data Cache! @@ -559,7 +3165,7 @@ 10 - PCI Bus test 11 - CPU Cache Loop (No Return) 0 - quit Enter the menu item number (0 to quit): -</programlisting> +</screen> Tests for various hardware subsystems are provided, and some tests require special hardware in order to execute normally. The Ethernet Configuration item may be used to set the board ethernet address.</para> @@ -571,7 +3177,7 @@ test is aborted and information about th the user will be prompted to enter the base address of the test range and its size. The numbers must be in hex with no leading “0x” </para> -<programlisting> +<screen> Enter the menu item number (0 to quit): <userinput>1</userinput> Base address of memory to test (in hex): <userinput>100000</userinput> @@ -591,7 +3197,7 @@ 32-bit address bar test: passed 8-bit address test: passed Byte address bar test: passed Memory test done. -</programlisting> +</screen> </sect3> <sect3> <title>Repeating Memory Tests</title> @@ -625,7 +3231,7 @@ LED cycles through 0 through F and a dec the current contents are invalid. In any case, this test will also allow the user to enter a six byte ethernet MAC address into the serial EEPROM. </para> -<programlisting> +<screen> Enter the menu item number (0 to quit): <userinput>6</userinput> @@ -634,7 +3240,7 @@ Enter desired MAC address: <userinput>00 Writing to the Serial EEPROM... Done ******** Reset The Board To Have Changes Take Effect ******** -</programlisting> +</screen> </sect3> <sect3> <title>Battery Status Test</title> @@ -825,112 +3431,413 @@ 0xfff00000 - 0xffffffff 0 0 0 Verde Me <para>The Verde programmable timer0 is used for timeout support for networking and XModem file transfers.</para> </sect2></sect1> + +<!-- ********************** CalmRISC ********************** --> <?Pub _newpage> -<sect1 id="brutus"> -<title>Intel SA1100 (Brutus) </title> +<sect1 id="CalmRISC16"> +<title>CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board </title> <sect2> <title>Overview</title> -<para><indexterm><primary>Intel-SA1100 (Brutus)</primary><secondary>installing +<para><indexterm><primary>Samsung CalmRISC16 Core EVB</primary><secondary>installing and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Intel SA1100 (Brutus)</secondary></indexterm>RedBoot -supports both board serial ports on the Brutus board. The default serial port -settings are 38400,8,N,1. flash management is not currently supported. </para> -<para>Two basic RedBoot configurations are supported:<itemizedlist> -<listitem><para>RedBoot running from the board's flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. +</primary><secondary>Samsung CalmRISC16 Core EVB</secondary></indexterm> The +Samsung CalmRISC16 evaluation platform consists of two boards connected by a +ribbon cable. One board contains the CPU core and memory. The other board is +called the MDSChip board and provides the host interface. The calmRISC16 is a +harvard architecture with separate 22-bit program and data addresses. The +instruction set provides no instruction for writing to program memory. The +MDSChip board firmware (called CalmBreaker) provides a pseudo register interface +so that code running on the core has access to a serial channel and a mechanism +to write to program memory. The serial channel is fixed at 57600-8-N-1 by the +firmware. The CalmBreaker firmware also provides a serial protocol which +allows a host to download a program and to start or stop the core board.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running via the MDSChip board.</entry> + <entry>redboot_ROM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> </para> -</listitem> -</itemizedlist></para> + </sect2> <sect2> <title>Initial Installation Method </title> -<para>Device programmer is used to program socketecflash parts.</para> +<para>The CalmRISC16 core is controlled through the MDSChip board. There is +no non-volatile storage available for RedBoot, so RedBoot must be downloaded +to the board on every power cycle. A small utility program is used to download +S-record files to the eval board. Sources and build instructions for this +utility are located in the RedBoot sources in: +<filename class="directory">packages/hal/calmrisc16/ceb/current/support +</filename></para> +<para>To download the RedBoot image, first press the reset button on the MDSChip +board. The green 'Run' LED on the core board should go off. Now, use the +utility to download the RedBoot image with: +<screen>$ <userinput>calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf</userinput> +</screen> +Note that the '-p /dev/term/b' specifies the serial port to use and will vary +from system to system. The download will take about two minutes. After it +finishes, start RedBoot with: +<screen>$ <userinput>calmbreaker -p /dev/term/b --run</userinput></screen> +The 'Run' LED on the core board should be on. Connecting to the MDSboard with +a terminal and typing enter should result in RedBoot reprinting the command +prompt. +</para> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>None.</para> +</sect2> +<sect2> +<title>Special Note on Serial Channel </title> +<para>The MDSChip board uses a relatively slow microcontroller to provide +the pseudo-register interface to the core board. This pseudo-register +interface provides access to the serial channel and write access to program +memory. Those interfaces are slow and the serial channel is easily overrun +by a fast host. For this reason, GDB must be told to limit the size of code +download packets to avoid serial overrun. This is done with the following +GDB command: +<screen>(gdb) <userinput>set download-write-size 25</userinput></screen> +</para> +</sect2> +<sect2> + +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=calm16_ceb +export ARCH_DIR=calmrisc16 +export PLATFORM_DIR=ceb +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="CalmRISC32"> +<title>CalmRISC/CalmRISC32 Samsung CalmRISC32 Core Evaluation Board </title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Samsung CalmRISC32 Core EVB</primary><secondary>installing +and testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Samsung CalmRISC32 Core EVB</secondary></indexterm> The +Samsung CalmRISC32 evaluation platform consists of two boards connected by a +ribbon cable. One board contains the CPU core and memory. The other board is +called the MDSChip board and provides the host interface. The calmRISC32 is a +harvard architecture with separate 32-bit program and data addresses. The +instruction set provides no instruction for writing to program memory. The +MDSChip board firmware (called CalmBreaker) provides a pseudo register interface +so that code running on the core has access to a serial channel and a mechanism +to write to program memory. The serial channel is fixed at 57600-8-N-1 by the +firmware. The CalmBreaker firmware also provides a serial protocol which +allows a host to download a program and to start or stop the core board.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running via the MDSChip board.</entry> + <entry>redboot_ROM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + +</sect2> +<sect2> +<title>Initial Installation Method </title> +<para>The calmRISC32 core is controlled through the MDSChip board. There is +no non-volatile storage available for RedBoot, so RedBoot must be downloaded +to the board on every power cycle. A small utility program is used to download +S-record files to the eval board. Sources and build instructions for this +utility are located in the RedBoot sources in: +<filename class="directory">packages/hal/calmrisc32/ceb/current/support +</filename></para> +<para>To download the RedBoot image, first press the reset button on the MDSChip +board. The green 'Run' LED on the core board should go off. Now, use the +utility to download the RedBoot image with: +<screen>$ <userinput>calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf</userinput> +</screen> +Note that the '-p /dev/term/b' specifies the serial port to use and will vary +from system to syetm. The download will take about two minutes. After it +finishes, start RedBoot with: +<screen>$ <userinput>calmbreaker -p /dev/term/b --run</userinput></screen> +The 'Run' LED on the core board should be on. Connecting to the MDSboard with +a terminal and typing enter should result in RedBoot reprinting the command +prompt. +</para> </sect2> <sect2> <title>Special RedBoot Commands </title> <para>None.</para> </sect2> <sect2> -<title>Memory Maps </title> -<para>The first level page table is located at physical address 0xc0004000. -No second level tables are used.<note><title>NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note><programlisting>Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x000fffff Boot ROM -0x08000000 - 0x083fffff Application flash -0x10000000 - 0x100fffff SRAM -0x18000000 - 0x180fffff Chip Select 3 -0x20000000 - 0x3fffffff PCMCIA -0x80000000 - 0xbfffffff SA-1100 Internal Registers -0xc0000000 - 0xc7ffffff DRAM Bank 0 -0xc8000000 - 0xcfffffff DRAM Bank 1 -0xd0000000 - 0xd7ffffff DRAM Bank 2 -0xd8000000 - 0xdfffffff DRAM Bank 3 -0xe0000000 - 0xe7ffffff Cache Clean - - -Virtual Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x003fffff Y Y DRAM Bank 0 -0x00400000 - 0x007fffff Y Y DRAM Bank 1 -0x00800000 - 0x00bfffff Y Y DRAM Bank 2 -0x00c00000 - 0x00ffffff Y Y DRAM Bank 3 -0x08000000 - 0x083fffff Y Y Application flash -0x10000000 - 0x100fffff Y N SRAM -0x20000000 - 0x3fffffff N N PCMCIA -0x40000000 - 0x400fffff Y Y Boot ROM -0x80000000 - 0xbfffffff N N SA-1100 Internal Registers -0xe0000000 - 0xe7ffffff Y Y Cache Clean</programlisting></para> -</sect2> -<sect2> -<title>Platform Resource Usage </title> -<para> -The SA11x0 OS timer is used as a polled timer to provide timeout -support for XModem file transfers.</para> +<title>Special Note on Serial Channel </title> +<para>The MDSChip board uses a relatively slow microcontroller to provide +the pseudo-register interface to the core board. This pseudo-register +interface provides access to the serial channel and write access to program +memory. Those interfaces are slow and the serial channel is easily overrun +by a fast host. For this reason, GDB must be told to limit the size of code +download packets to avoid serial overrun. This is done with the following +GDB command: +<screen>(gdb) <userinput>set download-write-size 25</userinput></screen> +</para> </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“brutus”, “arm” and “sa11x0/brutus” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/sa11x0/brutus/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=calm32_ceb +export ARCH_DIR=calmrisc32 +export PLATFORM_DIR=ceb +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2> </sect1> + +<!-- ******************************** FRV ********************* --> + <?Pub _newpage> -<sect1 id="ebsa285"> -<title>Intel StrongArm EBSA 285</title> +<sect1 id="frv400"> +<title>FRV/FRV400 Fujitsu FR-V 400 (MB-93091)</title> <sect2> <title>Overview</title> -<para><indexterm><primary>Intel StrongArm EBSA 285</primary><secondary>installing -and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Intel StrongArm EBSA 285</secondary></indexterm>RedBoot -uses the single EBSA-285 serial port. The default serial port settings are -38400,8,N,1. If the EBSA-285 is used as a host on a PCI backplane, ethernet -is supported using an Intel PRO/100+ ethernet adapter.</para> -<para>Management of onboard flash is also supported. Two basic RedBoot configurations -are supported: <itemizedlist> -<listitem><para>RedBoot running from the board's flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. + +<para><indexterm><primary>Fujitsu FR-V 400</primary> +<secondary>installing and testing</secondary></indexterm><indexterm><primary> +installing and testing +</primary><secondary>Fujitsu FR-V 400</secondary></indexterm> +RedBoot supports both serial ports, which are available via +the stacked serial connectors on the mother board. +The topmost port is the default and is considered to be port 0 by RedBoot. +The bottommost port is serial port 1. +The default serial port settings are 38400,8,N,1. +</para> +<para> +FLASH management is also supported, but only for the FLASH device in IC7. +This arrangement allows for IC8 to retain either the original Fujitsu board +firmware, or some application specific contents.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROMRAM</entry> + <entry>[ROMRAM]</entry> + <entry>RedBoot running from RAM, but contained in the + board's flash boot sector.</entry> + <entry>redboot_ROMRAM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> +</sect2> + +<sect2> +<title>Initial Installation Method </title> + +<para> +RedBoot can be installed by directly programming the FLASH device in IC7 +or by using the Fujitsu provided software to download and install a +version into the FLASH device. Complete instructions are provided +separately. </para> -</listitem> -</itemizedlist></para> + +</sect2> + +<sect2> +<title>Special RedBoot Commands</title> + +<para>None.</para> +</sect2> + +<sect2> +<title>Memory Maps</title> + +<para>The memory map of this platform is fixed by the hardware (cannot +be changed by software). The only attributes which can be modified are +control over cacheability, as noted below. +<screen> +Address Cache? Resource +00000000-03EFFFFF Yes SDRAM (via plugin DIMM) +03F00000-03FFFFFF No SDRAM (used for PCI window) +10000000-1FFFFFFF No MB86943 PCI bridge +20000000-201FFFFF No SRAM +21000000-23FFFFFF No Motherboard resources +24000000-25FFFFFF No PCI I/O space +26000000-2FFFFFFF No PCI Memory space +30000000-FDFFFFFF ?? Unused +FE000000-FEFFFFFF No I/O devices +FF000000-FF1FFFFF No IC7 - RedBoot FLASH +FF200000-FF3FFFFF No IC8 - unused FLASH +FF400000-FFFFFFFF No Misc other I/O +</screen> +</para> + +<note> <title>NOTE</title> +<para> +The only configuration currently suppored requires a 64MB SDRAM +DIMM to be present on the CPU card. No other memory configuration +is supported at this time. +</para> +</note> + +</sect2> + +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=frv400 +export ARCH_DIR=frv +export PLATFORM_DIR=frv400 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> +</sect2> + +</sect1> + +<!-- ********************************* IA32 *************************** --> +<?Pub _newpage> +<sect1 id="x86pc"> +<title>IA32/x86 x86-Based PC</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>x86 Based PC</primary><secondary>installing and +testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>x86 Based PC</secondary></indexterm>RedBoot supports +two serial ports and an Intel i82559 based ethernet card (for example an Intel +EtherExpress Pro 10/100) for communication and downloads. The default serial +port settings are 38400,8,N,1.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>Floppy</entry> + <entry>[Floppy]</entry> + <entry>RedBoot running from a boot floppy disk installed + in the A: drive of the PC.</entry> + <entry>redboot_ROM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + </sect2> <sect2> -<title>Initial Installation Method </title> -<para>A linux application is used to program the flash over the PCI bus. Sources -and build instructions for this utility are located in the RedBoot sources -in: <programlisting>.../packages/hal/arm/ebsa285/current/support/linux/safl_util -</programlisting></para> +<title>Initial Installation</title> +<para>RedBoot takes the form of a self-booting image that must be written +onto a formatted floppy disk. The process will erase any file system or data +that already exists on that disk, so proceed with caution.</para> +<para>For Red Hat Linux users, this can be done by:</para> +<screen>$ <userinput>dd conv=sync if=install/bin/redboot.bin of=/dev/fd0H1440 +</userinput></screen> +<para>For NT Cygwin users, this can be done by first ensuring that the raw +floppy device is mounted as <filename>/dev/fd0</filename>. To check if this +is the case, type the command <command>mount</command> at the Cygwin bash +prompt. If the floppy drive is already mounted, it will be listed as something +similar to the following line:</para> +<screen> \\.\a: /dev/fd0 user binmode</screen> +<para>If this line is not listed, then mount the floppy drive using the command: +</para> +<screen>$ <userinput>mount -f -b //./a: /dev/fd0</userinput></screen> +<para>To actually install the boot image on the floppy, use the command:</para> +<screen>$ <userinput>dd conv=sync if=install/bin/redboot.bin of=/dev/fd0 +</userinput></screen> +<para>Insert this floppy in the A: drive of the PC to be used as a target +and ensure that the BIOS is configured to boot from A: by default. On reset, +the PC will boot from the floppy and be ready to be debugged via either serial +line, or via the ethernet interface if it is installed.</para> +<note><title>NOTE</title> +<para>Unreliable floppy media may cause the write to silently fail. This +can be determined if the RedBoot image does not correctly +boot. In such cases, the floppy should be (unconditionally) reformatted +using the <command>fdformat</command> command on Linux, or +<command>format a: /u</command> on DOS/Windows.</para> +</note> </sect2> <sect2> -<title>Communication Channels </title> -<para>Serial, Intel PRO 10/100+ 82559 PCI ethernet card.</para> +<title>Flash management</title> +<para>PC RedBoot does not support any FLASH commands.</para> </sect2> <sect2> <title>Special RedBoot Commands </title> @@ -938,223 +3845,37 @@ in: <programlisting>.../packages/hal/arm </sect2> <sect2> <title>Memory Maps </title> -<para>Physical and virtual mapping are mapped one to one on the EBSA-285 using -a first level page table located at address 0x4000. No second level tables -are used. <note><title>NOTE </title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note><programlisting>Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x01ffffff Y Y SDRAM -0x40000000 - 0x400fffff N N 21285 Registers -0x41000000 - 0x413fffff Y N flash -0x42000000 - 0x420fffff N N 21285 CSR Space -0x50000000 - 0x50ffffff Y Y Cache Clean -0x78000000 - 0x78ffffff N N Outbound Write Flush -0x79000000 - 0x7c0fffff N N PCI IACK/Config/IO -0x80000000 - 0xffffffff N Y PCI Memory </programlisting></para> -</sect2> -<sect2> -<title>Platform Resource Usage </title> -<para>Timer3 is used as a polled timer to provide timeout support for networking -and XModem file transfers.</para> -</sect2> -<sect2> -<title>Building eCos Test Cases to run with old RedBoots</title> -<para>If using older versions of RedBoot, the default configuration for -EBSA-285 will send diagnostic output to the serial line only, not over an ethernet -connection. To allow eCos programs to use RedBoot to channel diagnostic output to -GDB whether connected by net or serial, enable the configuration option <programlisting> -CYGSEM_HAL_VIRTUAL_VECTOR_DIAG -"Do diagnostic IO via virtual vector table"</programlisting> located here -in the common HAL configuration tree: <programlisting>"eCos HAL" - "ROM monitor support" - "Enable use of virtual vector calling interface" - "Do diagnostic IO via virtual vector table"</programlisting>Other -than that, no special configuration is required to use RedBoot. </para> -<para>If you have been using built-in stubs to acquire support for thread-aware -debugging, you can still do that, but you must only use the serial device -for GDB connection and you must not enable the option mentioned above. However, -it is no longer necessary to do that to get thread-awareness; RedBoot is thread -aware.</para> -</sect2><sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“ebsa285”, “arm” and “ebsa285” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/ebsa285/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="sa1100mm"> -<title>Intel SA1100 Multimedia Board </title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Intel SA1100 Multimedia Board</primary><secondary> -installing and testing</secondary></indexterm><indexterm><primary>installing -and testing</primary><secondary>Intel SA1100 Multimedia Board</secondary> -</indexterm>RedBoot supports both board serial ports. The default serial port -settings are 38400,8,N,1. flash management is also supported. Two basic RedBoot -configurations are supported: n <itemizedlist> -<listitem><para>RedBoot running from the board's flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. +<para>All selectors are initialized to map the entire 32-bit address space +in the familiar protected mode flat model. Page translation is not used. +RAM up to 640K is mapped to 0x0 to 0xa0000. RAM above 640K is mapped +from address 0x100000 upwards. Space is reserved between 0xa0000 and +0x100000 for option ROMs and the BIOS. </para> -</listitem> -</itemizedlist></para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>A device programmer is used to program socketed flash parts.</para> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> </sect2> <sect2> -<title>Memory Maps </title> -<para>The first level page table is located at physical address 0xc0004000. -No second level tables are used.<note><title>NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note><programlisting>Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x000fffff Boot flash -0x08000000 - 0x083fffff Application flash -0x10000000 - 0x107fffff SA-1101 Board Registers -0x18000000 - 0x180fffff Ct8020 DSP -0x18400000 - 0x184fffff XBusReg -0x18800000 - 0x188fffff SysRegA -0x18c00000 - 0x18cfffff SysRegB -0x19000000 - 0x193fffff Spare CPLD A -0x19400000 - 0x197fffff Spare CPLD B -0x20000000 - 0x3fffffff PCMCIA -0x80000000 - 0xbfffffff SA1100 Internal Registers -0xc0000000 - 0xc07fffff DRAM Bank 0 -0xe0000000 - 0xe7ffffff Cache Clean -Virtual Address Range C B Description - - ------------------------ - - ---------------------------------- -0x00000000 - 0x007fffff Y Y DRAM Bank 0 -0x08000000 - 0x083fffff Y Y Application flash -0x10000000 - 0x100fffff N N SA-1101 Registers -0x18000000 - 0x180fffff N N Ct8020 DSP -0x18400000 - 0x184fffff N N XBusReg -0x18800000 - 0x188fffff N N SysRegA -0x18c00000 - 0x18cfffff N N SysRegB -0x19000000 - 0x193fffff N N Spare CPLD A -0x19400000 - 0x197fffff N N Spare CPLD B -0x20000000 - 0x3fffffff N N PCMCIA -0x50000000 - 0x500fffff Y Y Boot flash -0x80000000 - 0xbfffffff N N SA1100 Internal Registers -0xc0000000 - 0xc07fffff N Y DRAM Bank 0 -0xe0000000 - 0xe7ffffff Y Y Cache Clean</programlisting></para> -</sect2> -<sect2> -<title>Platform Resource Usage </title> -<para> The SA11x0 OS timer is used as a polled timer to provide timeout support -for XModem file transfers.</para> -</sect2><sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“sa1100mm”, “arm” and “sa11x0/sa1100mm” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/sa11x0/sa1100mm/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=pc +export ARCH_DIR=i386 +export PLATFORM_DIR=pc +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2> </sect1> -<?Pub _newpage> -<sect1 id="assabet"> -<title>Intel SA1110 (Assabet) </title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Intel SA1110 (Assabet)</primary><secondary>installing -and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Intel SA1110 (Assabet)</secondary></indexterm>RedBoot -supports the board serial port and the compact flash ethernet port. The default -serial port settings are 38400,8,N,1. RedBoot also supports flash management -on the Assabet. Two basic RedBoot configurations are supported: <itemizedlist> -<listitem><para>RedBoot running from the board's flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. -</para> -</listitem> -</itemizedlist></para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>A Windows or Linux utility is used to program flash over parallel port -driven JTAG interface. See board documentation for details on in situ flash -programming. </para> -<para>The flash parts are also socketed and may be programmed in a suitable -device programmer.</para> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Memory Maps </title> -<para>The first level page table is located at physical address 0xc0004000. -No second level tables are used.<note><title>NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note><programlisting>Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x07ffffff flash -0x08000000 - 0x0fffffff SA-1111 Board flash -0x10000000 - 0x17ffffff Board Registers -0x18000000 - 0x1fffffff Ethernet -0x20000000 - 0x2fffffff SA-1111 Board PCMCIA -0x30000000 - 0x3fffffff Compact Flash -0x40000000 - 0x47ffffff SA-1111 Board -0x48000000 - 0x4bffffff GFX -0x80000000 - 0xbfffffff SA-1110 Internal Registers -0xc0000000 - 0xc7ffffff DRAM Bank 0 -0xc8000000 - 0xcfffffff DRAM Bank 1 -0xd0000000 - 0xd7ffffff DRAM Bank 2 -0xd8000000 - 0xdfffffff DRAM Bank 3 -0xe0000000 - 0xe7ffffff Cache Clean - - -Virtual Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x01ffffff Y Y DRAM Bank 0 -0x08000000 - 0x0fffffff Y Y SA-1111 Board flash -0x10000000 - 0x17ffffff N N Board Registers -0x18000000 - 0x1fffffff N N Ethernet -0x20000000 - 0x2fffffff N N SA-1111 Board PCMCIA -0x30000000 - 0x3fffffff N N Compact Flash -0x40000000 - 0x47ffffff N N SA-1111 Board -0x48000000 - 0x4bffffff N N GFX -0x50000000 - 0x57ffffff Y Y flash -0x80000000 - 0xbfffffff N N SA-1110 Internal Registers -0xc0000000 - 0xc1ffffff N Y DRAM Bank 0 -0xe0000000 - 0xe7ffffff Y Y Cache Clean -The flash based RedBoot image occupies virtual addresses 0x50000000 - 0x5003ffff. -</programlisting></para> -</sect2> -<sect2> -<title>Platform Resource Usage </title> -<para>The SA11x0 OS timer is used as a polled timer to provide timeout support -for network and XModem file transfers.</para> -</sect2><sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“assabet”, “arm” and “sa11x0/assabet” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/sa11x0/assabet/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> + +<!-- *************** MIPS ******************* --> + <?Pub _newpage> <sect1 id="atlas"> -<title>MIPS Atlas Board with CoreLV 4Kc and CoreLV 5Kc </title> +<title>MIPS/MIPS32(CoreLV 4Kc)+MIPS64(CoreLV 5Kc) Atlas Board</title> <sect2> <title>Overview</title> <para><indexterm><primary>MIPS Atlas Board with CoreLV 4KC and CoreLV 5KC @@ -1163,13 +3884,40 @@ directory in the RedBoot source tree sho CoreLV 4KC and CoreLV 5KC</secondary></indexterm>RedBoot supports the DgbSer serial port and the built in ethernet port for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot runs from and supports -flash management for the system flash region. These configurations are supported: <itemizedlist> -<listitem><para>RedBoot running from the system flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the system flash -boot sector.</para> -</listitem> -</itemizedlist></para> +flash management for the system flash region.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + </sect2> <sect2> <title>Initial Installation</title> @@ -1179,10 +3927,10 @@ format in <xref linkend="Atlas-download- <sect3> <title>Quick download instructions</title> <para>Here are quick start instructions for downloading the prebuilt RedBoot -image. </para> +image.</para> <orderedlist> -<listitem><para>Locate the prebuilt files in the bin directory: <computeroutput> -deleteall.dl</computeroutput> and <computeroutput>redboot.dl</computeroutput>. +<listitem><para>Locate the prebuilt files in the bin directory: <filename> +deleteall.dl</filename> and <filename>redboot.dl</filename>. </para> </listitem> <listitem><para>Make sure switch S1-1 is OFF and switch S5-1 is ON. Reset @@ -1192,17 +3940,20 @@ the board and verify that the LED displa <listitem><para>Make sure your parallel port is connected to the 1284 port Of the Atlas board. </para> </listitem> -<listitem><para>Send the deleteall.dl file to the parallel port to erase previous -images: <programlisting>% cat deleteall.dl >/dev/lp0</programlisting> When -this is complete, the LED display should read “Deleted.” </para> +<listitem><para>Send the <filename>deleteall.dl</filename> file to the +parallel port to erase previous images: +<screen>$ <userinput>cat deleteall.dl >/dev/lp0</userinput></screen> +When this is complete, the LED display should read +<computeroutput>Deleted</computeroutput>.</para> </listitem> -<listitem><para>Send the RedBoot image to the board: <programlisting>% cat redboot.dl >/dev/lp0 -</programlisting>When this is complete, the LED display should show the last +<listitem><para>Send the ROM mode RedBoot image to the board: +<screen>$ <userinput>cat redboot.dl >/dev/lp0</userinput></screen> +When this is complete, the LED display should show the last address programmed. This will be something like: <computeroutput>1fc17000 </computeroutput>. </para> </listitem> <listitem><para>Change switch S5-1 to OFF and reset the board. The LED display -should read “RedBoot”. </para> +should read <computeroutput>RedBoot</computeroutput>. </para> </listitem> <listitem><para>Run the RedBoot <command>fis init</command> and <command>fconfig</command> commands to initialize the flash. @@ -1216,31 +3967,33 @@ and <xref linkend="Persistent-State-Flas <para>In order to download RedBoot to the Atlas board, it must be converted to the Atlas download format. There are different ways of doing this depending on which version of the developer's kit is shipped with the board. </para> -<para>The <citetitle>Atlas Developer's Kit</citetitle> CD contains an <computeroutput> -srec2flash</computeroutput> utility. The source code for this utility is part -of the <computeroutput>yamon/yamon-src-01.01.tar.gz</computeroutput> tarball -on the Dev Kit CD. The path in the expanded tarball is <computeroutput>yamon/bin/tools -</computeroutput>. To use <computeroutput>srec2flash</computeroutput> to -convert the S-record file: <programlisting>% srec2flash -EL -S29 redboot.srec >redboot.dl -</programlisting> The <citetitle>Atlas/Malta Developer's Kit</citetitle> CD -contains an <computeroutput>srecconv.pl</computeroutput> utility which requires -Perl. This utilty is part of the <computeroutput>yamon/yamon-src-02.00.tar.gz -</computeroutput> tarball on the Dev Kit CD. The path in the expanded tarball -is <computeroutput>yamon/bin/tools</computeroutput>. To use <computeroutput> -srecconv</computeroutput> to convert the S-record file: <programlisting> -% cp redboot_ROM.srec redboot_ROM.rec -% srecconv.pl -ES L -A 29 redboot_ROM </programlisting> The resulting file is -named redboot_ROM.fl.</para> +<para>The <citetitle>Atlas Developer's Kit</citetitle> CD contains an <application> +srec2flash</application> utility. The source code for this utility is part +of the <filename>yamon/yamon-src-01.01.tar.gz</filename> tarball +on the Dev Kit CD. The path in the expanded tarball is <filename +class="directory">yamon/bin/tools</filename>. To use +<application>srec2flash</application> to convert the S-record file: +<screen>$ <userinput>srec2flash -EL -S29 redboot.srec >redboot.dl</userinput></screen> +The <citetitle>Atlas/Malta Developer's Kit</citetitle> CD +contains an <application>srecconv.pl</application> utility which requires +Perl. This utilty is part of the <filename>yamon/yamon-src-02.00.tar.gz</filename> +tarball on the Dev Kit CD. The path in the expanded tarball +is <filename class="directory">yamon/bin/tools</filename>. To use <application> +srecconv</application> to convert the S-record file: +<screen>$ <userinput>cp redboot_ROM.srec redboot_ROM.rec</userinput> +$ <userinput>srecconv.pl -ES L -A 29 redboot_ROM</userinput></screen> +The resulting file is named <filename>redboot_ROM.fl</filename>.</para> </sect3></sect2> <sect2> <title>Flash management</title> <sect3 id="Atlas-Additional-fconfig-options"> <title>Additional config options</title> <para>The ethernet MAC address is stored in flash manually using the <command> -fconfig</command> command. You can use the YAMON <computeroutput>setenv -ethaddr</computeroutput> command to print out the board ethernet address. -Typically, it is: <programlisting>00:0d:a0:00:xx:xx</programlisting> where -xx.xx is the hex representation of the board serial number.</para> +fconfig</command> command. You can use the YAMON <command>setenv +ethaddr</command> command to print out the board ethernet address. +Typically, it is: <screen>00:0d:a0:00:<replaceable>xx:xx</replaceable></screen> where +<replaceable>xx.xx</replaceable> is the hex representation of the +board serial number.</para> </sect3> </sect2> <sect2> @@ -1329,18 +4082,29 @@ 0x1f000000 - 0x1fbfffff FPGA</programlis </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“atlas_mips32_4kc” or “atlas_mips64_5kc”, “mips” -and “atlas” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/mips/atlas/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=atlas_mips32_4kc +export TARGET=atlas_mips64_5kc +export ARCH_DIR=mips +export PLATFORM_DIR=atlas +</programlisting> + +Use one of the TARGET settings only. + +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2> </sect1> <?Pub _newpage> <sect1 id="malta"> -<title>MIPS Malta Board with CoreLV 4Kc and CoreLV 5Kc </title> +<title>MIPS/MIPS32(CoreLV 4Kc)+MIPS64(CoreLV 5Kc) Malta Board </title> <sect2> <title>Overview</title> <para><indexterm><primary>MIPS Malta Board with CoreLV 4KC and CoreLV 5KC @@ -1349,13 +4113,40 @@ directory in the RedBoot source tree sho CoreLV 4KC and CoreLV 5KC</secondary></indexterm>RedBoot supports both front facing serial ports and the built in ethernet port for communication and downloads. The default serial port settings are 38400,8,N,1. RedBoot runs from and supports -flash management for the system flash region. These configurations are supported: <itemizedlist> -<listitem><para>RedBoot running from the system flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the system flash -boot sector.</para> -</listitem> -</itemizedlist></para> +flash management for the system flash region.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> +</para> + </sect2> <sect2> <title>Initial Installation</title> @@ -1376,20 +4167,23 @@ the LED display reads <computeroutput>Fl <listitem><para>Make sure your parallel port is connected to the 1284 port Of the Atlas board. </para> </listitem> -<listitem><para>Send the deleteall.fl file to the parallel port to erase previous -images: <programlisting>% cat deleteall.fl >/dev/lp0</programlisting> When -this is complete, the LED display should read <computeroutput>Deleted.</computeroutput></para> +<listitem><para>Send the <filename>deleteall.fl</filename> file to the +parallel port to erase previous images: +<screen>$ <userinput>cat deleteall.fl >/dev/lp0</userinput></screen> +When this is complete, the LED display should read +<computeroutput>Deleted</computeroutput>.</para> </listitem> -<listitem><para>Send the RedBoot image to the board: <programlisting>% cat redboot_ROM.fl >/dev/lp0 -</programlisting> When this is complete, the LED display should show the last -address programmed. This will be something like: <computeroutput>1fc17000 -</computeroutput>. </para> +<listitem><para>Send the RedBoot image to the board: +<screen>$ <userinput>cat redboot_ROM.fl >/dev/lp0</userinput></screen> +When this is complete, the LED display should show the last address +programmed. This will be something like: +<computeroutput>1fc17000</computeroutput>. </para> </listitem> <listitem><para>Change switch S5-1 to OFF and reset the board. The LED display -should read “RedBoot”. </para> +should read <computeroutput>RedBoot</computeroutput>. </para> </listitem> -<listitem><para>Run the RedBoot <userinput>fis init</userinput> and <userinput> -fconfig</userinput> commands to initialize the flash. See <xref linkend="Flash-Image-System"> +<listitem><para>Run the RedBoot <command>fis init</command> and <command> +fconfig</command> commands to initialize the flash. See <xref linkend="Flash-Image-System"> and <xref linkend="Persistent-State-Flash"> for details. </para> </listitem> </orderedlist> @@ -1398,14 +4192,15 @@ and <xref linkend="Persistent-State-Flas <title>Malta download format</title> <para>In order to download RedBoot to the Malta board, it must be converted to the Malta download format.</para> -<para>The <citetitle>Atlas/Malta Developer's Kit</citetitle> CD contains an <computeroutput> -srecconv.pl</computeroutput> utility which requires Perl. This utility is part -of the <computeroutput>yamon/yamon-src-02.00.tar.gz</computeroutput> tarball -on the Dev Kit CD. The path in the expanded tarball is <computeroutput>yamon/bin/tools -</computeroutput>. To use <computeroutput>srecconv</computeroutput> to convert -the S-record file: <programlisting>% cp redboot_ROM.srec redboot_ROM.rec -% srecconv.pl -ES L -A 29 redboot_ROM </programlisting> The resulting file -is named redboot_ROM.fl.</para> +<para>The <citetitle>Atlas/Malta Developer's Kit</citetitle> CD contains an <application> +srecconv.pl</application> utility which requires Perl. This utility is part +of the <filename>yamon/yamon-src-02.00.tar.gz</filename> tarball +on the Dev Kit CD. The path in the expanded tarball is <filename +class="directory">yamon/bin/tools</filename>. To use +<application>srecconv</application> to convert the S-record file: +<screen>$ <userinput>cp redboot_ROM.srec redboot_ROM.rec</userinput> +$ <userinput>srecconv.pl -ES L -A 29 redboot_ROM</userinput></screen> +The resulting file is named <filename>redboot_ROM.fl</filename>.</para> </sect3></sect2> <sect2> @@ -1497,34 +4292,63 @@ 0xbf000000 - 0xbfffffff N N Board logic </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“malta_mips32_4kc”, “mips” and “malta” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/mips/malta/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=malta_mips32_4kc +export ARCH_DIR=mips +export PLATFORM_DIR=malta +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2></sect1> <?Pub _newpage> <sect1 id="ocelot"> -<title>PMC-Sierra MIPS RM7000 Ocelot</title> +<title>MIPS/RM7000 PMC-Sierra Ocelot</title> <sect2> <title>Overview</title> <para><indexterm><primary>PMC-Sierra MIPS RM7000 Ocelot</primary><secondary>installing and testing</secondary></indexterm><indexterm><primary>installing and testing </primary><secondary>PMC-Sierra MIPS RM7000 Ocelot</secondary></indexterm>RedBoot uses the front facing serial port. The default serial port settings are 38400,8,N,1. -RedBoot also supports ethernet. Management of onboard flash is also supported. -Two basic RedBoot configurations are supported:<itemizedlist> -<listitem><para>RedBoot running from the board's flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. +RedBoot also supports ethernet. Management of onboard flash is also supported.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROM</entry> + <entry>[ROM]</entry> + <entry>RedBoot running from the board's flash boot + sector.</entry> + <entry>redboot_ROM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> </para> -</listitem> -</itemizedlist></para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>Device programmer is used to program socketed flash parts.</para> </sect2> <sect2> @@ -1577,105 +4401,183 @@ 0x1fc00000 - 0x1fc7ffff flash</programli </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“ocelot”, “mips” and “rm7000/ocelot” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/mips/rm7000/ocelot/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=ocelot +export ARCH_DIR=mips +export PLATFORM_DIR=rm7000/ocelot +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2></sect1> + + <?Pub _newpage> -<sect1 id="mbx"> -<title>Motorola PowerPC MBX</title> +<sect1 id="vrc4375"> +<title>MIPS/VR4375 NEC DDB-VRC4375</title> <sect2> <title>Overview</title> -<para><indexterm><primary>Motorola PowerPC MBX</primary><secondary>installing -and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Motorola PowerPC MBX</secondary></indexterm>RedBoot uses -the SMC1/COM1 serial port. The default serial port settings are 38400,8,N,1. -Ethernet is also supported using the 10-base T connector. </para> -<para>Management of onboard flash is also supported. Two basic RedBoot configurations -are supported: <itemizedlist> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. + +<para><indexterm><primary>NEC DDB-VRC4375</primary> +<secondary>installing and testing</secondary></indexterm><indexterm><primary> +installing and testing</primary><secondary>NEC DDB-VRC4375 +</secondary></indexterm>RedBoot supports only serial port 1, which is connected to the upper +of the stacked serial connectors on the board. The default serial +port settings are 38400,8,N,1. FLASH management is also supported.</para> + +<para>The following RedBoot configurations are supported: + + <informaltable frame="all"> + <tgroup cols="4" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Configuration</entry> + <entry>Mode</entry> + <entry>Description</entry> + <entry>File</entry> + </row> + </thead> + <tbody> + <row> + <entry>ROMRAM</entry> + <entry>[ROMRAM]</entry> + <entry>RedBoot running from RAM, but contained in the + board's flash boot sector.</entry> + <entry>redboot_ROMRAM.ecm</entry> + </row> + <row> + <entry>RAM</entry> + <entry>[RAM]</entry> + <entry>RedBoot running from RAM with RedBoot in the + flash boot sector.</entry> + <entry>redboot_RAM.ecm</entry> + </row> +</tbody> +</tgroup> +</informaltable> </para> -</listitem> -<listitem><para>RedBoot running from the board's flash boot sector. </para> -</listitem> -</itemizedlist></para> + </sect2> + <sect2> <title>Initial Installation Method </title> -<para>Device programmer is used to program the XU1 socketed flash part (AM29F040B) -with the ROM version of RedBoot. - Use the on-board EPPC-Bug monitor to update -RedBoot. </para> -<para>This assumes that you have EPPC-Bug in the on-board flash. This can -be determined by setting up the board according to the following instructions -and powering up the board. </para> -<para>The EPPC-Bug prompt should appear on the SMC1 connector at 9600 baud, -8N1. </para> -<orderedlist> -<listitem><para>Set jumper 3 to 2-3 [allow XU1 flash to be programmed] </para> -</listitem> -<listitem><para>Set jumper 4 to 2-3 [boot EPPC-Bug] </para> -</listitem> -</orderedlist> -<para>If it is available, program the flash by following these steps: </para> -<orderedlist> -<listitem><para>Prepare EPPC-Bug for download: <programlisting>EPPC-Bug>lo 0 -</programlisting>At this point the monitor is ready for input. It will not -return the prompt until the file has been downloaded. </para> -</listitem> -<listitem><para>Use the terminal emulator's ASCII download feature (or a simple -clipboard copy/paste operation) to download the redboot.ppcbug file.</para> -<para>Note that on Linux, Minicom's ASCII download feature seems to be broken. -A workaround is to load the file into emacs (or another editor) and copy the -full contents to the clipboard. Then press the mouse paste-button (usually -the middle one) over the Minicom window. </para> -</listitem> -<listitem><para>Program the flash with the downloaded data: <programlisting> -EPPC-Bug>pflash 40000 60000 fc000000</programlisting></para> -</listitem> -<listitem><para>Switch off the power, and change jumper 4 to 1-2. Turn on -the power again. The board should now boot using the newly programmed RedBoot. -</para> -</listitem> -</orderedlist> -<para>To install RedBoot on a target that already has eCos GDB stubs, download -the RAM version of RedBoot and run it. Initialize the flash image directory: <programlisting> -RedBoot> fi init</programlisting>Then download the ROM version of RedBoot -and program it into flash: -<programlisting> -RedBoot> <userinput>load redboot_ROM.srec -b 0x80100000</userinput> -RedBoot> <userinput>fi cr RedBoot -f 0xFE000000 -b 0x00040000 -l 0x20000</userinput> -</programlisting></para> + +<para>A device programmer should be used to program a socketed FLASH part +(AMD 29F040). The board as delivered is configured for a 512K +EPROM. To install a FLASH ROM, Jumpers J30, J31 and J36 need to be +changed as described in the board's User Manual.</para> </sect2> + <sect2> -<title>Special RedBoot Commands </title> +<title>Special RedBoot Commands</title> + <para>None.</para> </sect2> + <sect2> -<title>Memory Maps </title> -<para>Memory Maps RedBoot sets up the following memory map on the MBX board.<programlisting> -Physical Address Range Description ------------------------ ----------- -0x00000000 - 0x003fffff DRAM -0xfa100000 - 0xfa100003 LEDs -0xfe000000 - 0xfe07ffff flash (AMD29F040B) -0xff000000 - 0xff0fffff MPC registers</programlisting></para> +<title>Memory Maps</title> + +<para>RedBoot sets up the memory map primarily as described in the board's +User Manual. There are some minor differences, noted in the following +table: +<screen> +Physical Virtual Resource +Addresses Addresses +00000000-01FFFFFF 80000000-81FFFFFF Base SDRAM (cached) +00000000-01FFFFFF A0000000-A1FFFFFF Base SDRAM (uncached) +0C000000-0C0BFFFF AC000000-AC0B0000 PCI IO space +0F000000-0F0001FF AF000000-AF0001FF VRC4375 Registers +1C000000-1C0FFFFF BC000000-BC0FFFFF VRC4372 Registers +1C100000-1DFFFFFF BC100000-BDFFFFFF PCI Memory space +1FC00000-1FC7FFFF BFC00000-BFC7FFFF FLASH ROM +80000000-8000000D C0000000-C000000D RTC +8000000E-80007FFF C000000E-C0007FFF NVRAM +81000000-81FFFFFF C1000000-C1FFFFFF Z85C30 DUART +82000000-82FFFFFF C2000000-C2FFFFFF Z8536 Timer +83000000-83FFFFFF C3000000-C3FFFFFF 8255 Parallel port +87000000-87FFFFFF C7000000-C7FFFFFF Seven segment display</screen> +</para> + +<note> <title>NOTE</title> +<para> +By default the VRC4375 SIMM control registers are not programmed +since the values used must depend on the SIMMs installed. If SIMMs +are to be used, correct values must be placed in these registers +before accessing the SIMM address range. +</para> +</note> + +<note> <title>NOTE</title> +<para> +The allocation of address ranges to devices in the PCI IO and +memory spaces is handled by the eCos PCI support library. They do +not correspond to those described in the board User Manual. +</para> +</note> + +<note> <title>NOTE</title> +<para> +The MMU has been set up to relocate the VRC4372 supported devices +mapped at physical addresses 0x8xxxxxxx to virtual addresses +0xCxxxxxxx. +</para> +</note> + </sect2> + +<sect2> +<title>Ethernet Driver</title> + +<para> +The ethernet driver is in two parts: +</para> + +<para> +A generic ether driver for the Intel i21143 device is located in +<filename class="directory">devs/eth/intel/i21143</filename>. Its package name is <computeroutput>CYGPKG_DEVS_ETH_INTEL_I21143</computeroutput>. +</para> + +<para> +The platform-specific ether driver is <filename +class="directory">devs/eth/mips/vrc4375</filename>. Its package is +<computeroutput>CYGPKG_DEVS_ETH_MIPS_VRC4375</computeroutput>. This +tells the generic driver the address in IO memory of the chip, for +example, and other configuration details. The ESA (MAC address) is by +default collected from on-board serial EEPROM, unless configured +statically within this package. +</para> +</sect2> + <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“mbx”, “powerpc” and “mbx” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/powerpc/mbx/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=vrc4373 +export ARCH_DIR=mips +export PLATFORM_DIR=vrc4373 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2> </sect1> + +<!-- ************************** PowerPC ********************** --> + <?Pub _newpage> <sect1 id="viper"> -<title>Analogue & Micro PowerPC 860T</title> +<title>PowerPC/MPC860T Analogue & Micro PowerPC 860T</title> <sect2> <title>Overview</title> <para><indexterm><primary>Analogue & Micro PowerPC 860T</primary><secondary>installing @@ -1710,267 +4612,87 @@ 0xff000000 - 0xff0fffff MPC registers</p </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“viper”, “powerpc” and “viper” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/powerpc/viper/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=viper +export ARCH_DIR=powerpc +export PLATFORM_DIR=viper +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2> </sect1> + <?Pub _newpage> -<sect1 id="e7t"> -<title>ARM Evaluator7T (e7t) board with ARM7TDMI</title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>ARM Evaluator7T</primary><secondary>installing and -testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>ARM Evaluator7T</secondary></indexterm>RedBoot supports -both serial ports for communication and downloads. The default serial port -settings are 38400,8,N,1.</para> -</sect2> -<sect2> -<title>Initial Installation</title> -<para>RedBoot is installed using the on-board boot environment. See the user -manual for full details.</para> -</sect2> -<sect2> -<title>Quick download instructions</title> -<para>Here are quick start instructions for downloading the prebuilt Redboot -image:</para> -<itemizedlist> -<listitem><para>Boot the board and press ENTER:</para> -<screen> - - ARM Evaluator7T Boot Monitor PreRelease 1.00 - Press ENTER within 2 seconds to stop autoboot - Boot: </screen> -</listitem> -<listitem><para>Erase the part of the flash where RedBoot will get programmed: -</para> -<screen> Boot: <userinput>flasherase 01820000 10000</userinput></screen> -</listitem> -<listitem><para>Prepare to download the UU-encoded version of the RedBoot -image:</para> -<screen> Boot: <userinput>download 10000</userinput> - Ready to download. Use 'transmit' option on terminal emulator to download file. -</screen> -</listitem> -<listitem><para>Either use ASCII transmit option in the terminal emulator, -or on Linux, simply cat the file to the serial port:<screen> $ <userinput> -cat redboot.UU > /dev/ttyS0</userinput></screen>When complete, you should -see:<screen> Loaded file redboot.bin at address 000100000, size = 41960 - Boot:</screen></para> -</listitem> -<listitem><para>Program the flash:<screen> Boot: <userinput>flashwrite 01820000 10000 10000 -</userinput></screen></para> -</listitem> -<listitem><para>And verify that the module is available:<screen> Boot: <userinput> -rommodules</userinput> - Header Base Limit - 018057c8 01800000 018059e7 BootStrapLoader v1.0 Apr 27 2000 10:33:58 - 01828f24 01820000 0182a3e8 RedBoot Apr 5 2001</screen></para> -</listitem> -<listitem><para>Reboot the board and you should see the RedBoot banner.</para> -</listitem> -</itemizedlist> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Memory Maps </title> -<para>RedBoot sets up the following memory map on the E7T board. <note><title> -NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note> <programlisting>Physical Address Range C B Description ------------------------ - - ----------- -0x00000000 - 0x0007ffff Y N SDRAM -0x03ff0000 - 0x03ffffff N N Microcontroller registers -0x01820000 - 0x0187ffff N N System flash (mirrored)</programlisting></para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“e7t”, “arm” and “e7t” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/e7t/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="integrator"> -<title>ARM Integrator board with ARM7TDMI or ARM966E</title> +<sect1 id="mbx"> +<title>PowerPC/MPC8XX Motorola MBX</title> <sect2> <title>Overview</title> -<para><indexterm><primary>ARM Integrator</primary><secondary>installing and -testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>ARM Integrator</secondary></indexterm>RedBoot supports -both serial ports for communication and downloads. The default serial port -settings are 38400,8,N,1.</para> -</sect2> -<sect2> -<title>Initial Installation</title> -<para>RedBoot is installed using the on-board bootPROM environment. See the user -manual for full details.</para> -</sect2> -<sect2> -<title>Quick download instructions</title> -<para>Here are quick start instructions for downloading the prebuilt Redboot -image:</para> -<itemizedlist> -<listitem><para>Set DIP switch S1[1] to the ON position and reset or -power the board up. You will see the bootPROM startup message on -serial port A (J14):</para> -<screen> -Initialising... - - -ARM bootPROM [Version 1.3] Rebuilt on Jun 26 2001 at 22:04:10 -Running on a Integrator Evaluation Board -Board Revision V1.0, ARM966E-S Processor -Memory Size is 16MBytes, Flash Size is 32MBytes -Copyright (c) ARM Limited 1999 - 2001. All rights reserved. -Board designed by ARM Limited -Hardware support provided at http://www.arm.com/ -For help on the available commands type ? or h -boot Monitor > -</screen> -</listitem> -<listitem> -<para>Issue the FLASH ROM load command: -</para> -<screen> -boot Monitor > <userinput>L</userinput> -Load Motorola S-Records into flash - -Deleting Image 0 - -The S-Record loader only accepts input on the serial port. -Type Ctrl/C to exit loader. -</screen> -</listitem> -<listitem><para>Either use the ASCII transmit option in the terminal emulator, -or on Linux, simply cat the file to the serial port: -</para> -<screen> -$ <userinput>cat redboot.srec > /dev/ttyS0</userinput> -</screen> -<para> -When complete, type Ctrl-C and you should see something similar to: -</para> -<screen> -................................ -................................ -.................... -Downloaded 5,394 records in 81 seconds. - -Overwritten block/s - 0 - -boot Monitor > -</screen> -</listitem> -<listitem><para>Set DIP switch S1[1] to the OFF position and reboot -the board and you should see the RedBoot banner.</para> -</listitem> -</itemizedlist> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Memory Maps </title> -<para>RedBoot sets up the following memory map on the Integrator board. <note><title> -NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note> -<programlisting> - -ARM7TDMI --------- - -Physical Address Range C B Description ------------------------ - - ----------- -0x00000000 - 0x0007ffff N N SSRAM -0x00080000 - 0x0fffffff N N SDRAM (depends on part fitted) -0x10000000 - 0x1fffffff N N System control and peripheral registers -0x20000000 - 0x23ffffff N N Boot ROM (contains boot Monitor) -0x24000000 - 0x27ffffff N N FLASH ROM (contains RedBoot) -0x28000000 - 0x2bffffff N N SSRAM echo area -0x40000000 - 0x5fffffff N N PCI Memory access windows -0x60000000 - 0x60ffffff N N PCI IO access window -0x61000000 - 0x61ffffff N N PCI config space window -0x62000000 - 0x6200ffff N N PCI bridge register window -0x80000000 - 0x8fffffff N N SDRAM echo area (used for PCI accesses) - - -ARM966E -------- - -Physical Address Range C B Description ------------------------ - - ----------- -0x00000000 - 0x000fffff N N SSRAM -0x00100000 - 0x0fffffff N N SDRAM (depends on part fitted) -0x10000000 - 0x1fffffff N N System control and peripheral registers -0x20000000 - 0x23ffffff N N Boot ROM (contains boot Monitor) -0x24000000 - 0x27ffffff N N FLASH ROM (contains RedBoot) -0x28000000 - 0x2bffffff N N SSRAM echo area -0x40000000 - 0x5fffffff N N PCI Memory access windows -0x60000000 - 0x60ffffff N N PCI IO access window -0x61000000 - 0x61ffffff N N PCI config space window -0x62000000 - 0x6200ffff N N PCI bridge register window -0x80000000 - 0x8fffffff N N SDRAM echo area (used for PCI accesses) - -</programlisting> -</para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should -be followed. The values for TARGET, ARCH_DIR and PLATFORM_DIR on this -platform are “integrator” or -“integrator_arm9”, “arm” and -“integrator” respectively. Note that the configuration -export files supplied in the <computeroutput> -hal/arm/integrator/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="pid"> -<title>ARM ARM7 PID, Dev7 and Dev9</title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>ARM ARM7 PID, Dev7 and Dev9</primary><secondary> -installing and testing</secondary></indexterm><indexterm><primary>installing -and testing</primary><secondary>ARM ARM7 PID, Dev7 and Dev9</secondary></indexterm>RedBoot -uses either of the serial ports. The default serial port settings are 38400,8,N,1. -Management of onboard flash is also supported. Two basic RedBoot configurations -are supported: <itemizedlist> -<listitem><para>RedBoot running from the board's flash boot sector.</para> -</listitem> +<para><indexterm><primary>Motorola PowerPC MBX</primary><secondary>installing +and testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Motorola PowerPC MBX</secondary></indexterm>RedBoot uses +the SMC1/COM1 serial port. The default serial port settings are 38400,8,N,1. +Ethernet is also supported using the 10-base T connector. </para> +<para>Management of onboard flash is also supported. Two basic RedBoot configurations +are supported: <itemizedlist> <listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. </para> </listitem> +<listitem><para>RedBoot running from the board's flash boot sector. </para> +</listitem> </itemizedlist></para> </sect2> <sect2> <title>Initial Installation Method </title> -<para>Device programmer is used to program socketed flash parts with ROM version -of RedBoot. </para> -<para>Alternatively, to install RedBoot on a target that already has eCos -GDB stubs, download the RAM version of RedBoot and run it. Initialize the -flash image directory: <command>fi init</command> Then -download the ROM version of RedBoot and program it into flash: <programlisting> -RedBoot> <userinput>load -b 0x00040000 -m ymodem</userinput> -RedBoot> <userinput>fi cr RedBoot -f 0x04000000 -b 0x00040000 -l 0x20000</userinput> -</programlisting></para> +<para>Device programmer is used to program the XU1 socketed flash part (AM29F040B) +with the ROM version of RedBoot. - Use the on-board EPPC-Bug monitor to update +RedBoot. </para> +<para>This assumes that you have EPPC-Bug in the on-board flash. This can +be determined by setting up the board according to the following instructions +and powering up the board. </para> +<para>The EPPC-Bug prompt should appear on the SMC1 connector at 9600 baud, +8N1. </para> +<orderedlist> +<listitem><para>Set jumper 3 to 2-3 [allow XU1 flash to be programmed] </para> +</listitem> +<listitem><para>Set jumper 4 to 2-3 [boot EPPC-Bug] </para> +</listitem> +</orderedlist> +<para>If it is available, program the flash by following these steps: </para> +<orderedlist> +<listitem><para>Prepare EPPC-Bug for download: <screen>EPPC-Bug>lo 0 +</screen>At this point the monitor is ready for input. It will not +return the prompt until the file has been downloaded. </para> +</listitem> +<listitem><para>Use the terminal emulator's ASCII download feature (or a simple +clipboard copy/paste operation) to download the redboot.ppcbug file.</para> +<para>Note that on Linux, Minicom's ASCII download feature seems to be broken. +A workaround is to load the file into emacs (or another editor) and copy the +full contents to the clipboard. Then press the mouse paste-button (usually +the middle one) over the Minicom window. </para> +</listitem> +<listitem><para>Program the flash with the downloaded data: <screen> +EPPC-Bug>pflash 40000 60000 fc000000</screen></para> +</listitem> +<listitem><para>Switch off the power, and change jumper 4 to 1-2. Turn on +the power again. The board should now boot using the newly programmed RedBoot. +</para> +</listitem> +</orderedlist> +<para>To install RedBoot on a target that already has eCos GDB stubs, download +the RAM version of RedBoot and run it. Initialize the flash image directory: <screen> +RedBoot> fi init</screen>Then download the ROM version of RedBoot +and program it into flash: +<screen> +RedBoot> <userinput>load redboot_ROM.srec -b 0x80100000</userinput> +RedBoot> <userinput>fi cr RedBoot -f 0xFE000000 -b 0x00040000 -l 0x20000</userinput> +</screen></para> </sect2> <sect2> <title>Special RedBoot Commands </title> @@ -1978,894 +4700,43 @@ RedBoot> <userinput>fi cr RedBoot -f 0x0 </sect2> <sect2> <title>Memory Maps </title> -<para>RedBoot sets up the following memory map on the PID board. <programlisting> +<para>Memory Maps RedBoot sets up the following memory map on the MBX board.<programlisting> Physical Address Range Description ----------------------- ----------- -0x00000000 - 0x0007ffff DRAM -0x04000000 - 0x04080000 flash -0x08000000 - 0x09ffffff ASB Expansion -0x0a000000 - 0x0bffffff APB Reference Peripheral -0x0c000000 - 0x0fffffff NISA Serial, Parallel and PC Card ports </programlisting></para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“pid”, “arm” and “pid” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/pid/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2></sect1> - -<?Pub _newpage> -<sect1 id="ipaq"> -<title>Compaq iPAQ PocketPC</title> -<indexterm><primary>Compaq iPAQ PocketPC</primary><secondary>installing and -testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Compaq iPAQ PocketPC</secondary></indexterm> -<sect2> -<title>Overview</title> -<para>RedBoot supports the serial port via cradle or cable, and Compact Flash -ethernet cards if fitted for communication and downloads. The LCD touchscreen -may also be used for the console, although by default RedBoot will switch -exclusively to one channel once input arrives. </para> -<para>The default serial port settings are 38400,8,N,1. RedBoot runs from -and supports flash management for the system flash region. </para> -</sect2> -<sect2> -<title>Initial Installation</title> -<para>Prebuilt images for the OSloader, redboot_ROM.bin -and redboot_WinCE.bin images mentioned in the instructions below are provided. -</para> -<sect3> -<title>Installing RedBoot on the iPAQ using Windows/CE</title> -<para> -The Windows/CE environment originally shipped with the iPAQ contains a hidden -mini-loader, sometimes referred to as the "Parrot" loader. This loader can -be started by holding down the action button (the joypad) while resetting -the unit or when powering on. At this point, a blue bird will appear on -the LCD screen. Also at this point, a simple loader can be accessed over the -serial port at 115200/8N1. Using this loader, the contents of the iPAQ flash -memory can be saved to a Compact Flash memory card. -<note><title>NOTE</title><para>We have only tested this operation with a 32Mbyte CF memory card. -Given that the backup will take 16MBytes + 1KByte, something more than a 16MByte -card will be required.</para></note> -</para> -<para> -Use the "r2c" command to dump Flash contents to the CF memory card. Once this -completes, RedBoot can be installed with no fear since the Parrot loader can -be used to restore the Flash contents at a later time. -</para> -<para> -If you expect to completely recover the state of the iPAQ Win/CE environment, then -HotSync should be run to backup all "RAM" files as well before installing RedBoot. -</para> -<para>The next step in installing RedBoot on the iPAQ actually involves Windows/CE, -which is the native environment on the unit. Using WinCE, you need to -install an application which will run a RAM based version of RedBoot. Once -this is installed and running, RedBoot can be used to update the flash with -a native/ROM version of RedBoot. <itemizedlist> -<listitem><para>Using ActiveSync, copy the file OSloader to your iPAQ. </para> -</listitem> -<listitem><para>Using ActiveSync, copy the file redboot_WinCE.bin to the iPAQ -as bootldr in its root directory. Note: this is not the top level folder -displayed by Windows (Mobile Device), but rather the 'My Pocket PC' folder -within it.</para> -</listitem> -<listitem><para>Execute OSloader. If you didn't create a shortcut, then you -will have to poke around for it using the WinCE file explorer.</para> -</listitem> -<listitem><para>Choose the <guimenuitem>Tools->BootLdr->Run after loading -from file</guimenuitem> menu item. </para> -</listitem> -</itemizedlist>At this point, the RAM based version of RedBoot should be running. - You should be able to return to this point by just executing the last two -steps of the previous process if necessary.</para> -</sect3> -<sect3> -<title>Installing RedBoot on the iPAQ - using the Compaq boot loader</title> -<para>This method of installation is no longer supported. -If you have previously installed either the Compaq boot loader or older -versions of RedBoot, restore the Win/CE environment and proceed as outlined -above. -</para> -</sect3> -<sect3 id="setting-up-and-testing-redboot"> -<title>Setting up and testing RedBoot</title> -<para>When RedBoot first comes up, it will want to initialize its LCD touch -screen parameters. It does this by displaying a keyboard graphic and asks -you to press certain keys. Using the stylus, press and hold until the prompt -is withdrawn. When you lift the stylus, RedBoot will continue with the next -calibration. </para> -<para>Once the LCD touchscreen has been calibrated, RedBoot will start. The -calibration step can be skipped by pressing the <guibutton>return/abort</guibutton> -button on the unit (right most button with a curved arrow icon). Additionally, -the unit will assume default values if the screen is not touched within about -15 seconds. </para> -<para>Once RedBoot has started, you should get information similar to this -on the LCD screen. It will also appear on the serial port at 38400,8,N,1. - <programlisting>RedBoot(tm) bootstrap and debug environment [ROM] -Red Hat certified release, version R1.xx - built 06:17:41, Mar 19 2001 -Platform: Compaq iPAQ Pocket PC (StrongARM 1110) - -Copyright (C) 2000, 2001, Red Hat, Inc. - -RAM: 0x00000000-0x01fc0000, 0x0001f200-0x01f70000 available -FLASH: 0x50000000 - 0x51000000, 64 blocks of 0x00040000 bytes each.</programlisting>Since -the LCD touchscreen is only 30 characters wide, some of this data will be -off the right hand side of the display. The joypad may be used to pan left -and right in order to see the full lines. </para> -<para>If you have a Compact Flash ethernet card, RedBoot should find it. -You'll need to have BOOTP enabled for this unit (see your sysadmin for details). - If it does, it will print a message like: <programlisting>... Waiting for network card: .Ready! -Socket Communications Inc: CF+ LPE Revision E 08/04/99 -IP: 192.168.1.34, Default server: 192.168.1.101</programlisting></para> -</sect3> -<sect3 id="ipaq-install-rb-permanently"> -<title>Installing RedBoot permanently</title> -<para>Once you are satisfied with the setup and that RedBoot is operating -properly in your environment, you can set up your iPAQ unit to have RedBoot -be the bootstrap application. <caution><title>CAUTION</title> -<para>This step will destroy your Windows/CE environment.</para> -<para>Before you take this step, it is strongly recommended you save your WinCE FLASH contents -as outlined above using the "parrot" loader, or -by using the Compaq OSloader: <itemizedlist> -<listitem><para>Using OSloader on the iPAQ, select the <guimenuitem>Tools->Flash->Save -to files...</guimenuitem>. menu item.</para> -</listitem> -<listitem><para>Four (4) files, 4MB each in size will be created.</para> -</listitem> -<listitem><para>After each file is created, copy the file to your computer, -then delete the file from the iPAQ to make room in the WinCE ramdisk for the -next file.</para> -</listitem> -</itemizedlist></para> -</caution>You will need to download the version of RedBoot designed as the -ROM bootstrap. Then install it permanently using these commands: - <programlisting> -RedBoot> <userinput>lo -r -b 0x100000 /tftpboot/redboot_ROM.bin</userinput> -RedBoot> <userinput>fi loc -f 0x50000000 -l 0x40000</userinput> -RedBoot> <userinput>fis init</userinput> -RedBoot> <userinput>fi unl -f 0x50040000 -l 0x40000</userinput> -RedBoot> <userinput>fi cr RedBoot -b 0x100000</userinput> -RedBoot> <userinput>fi loc -f 0x50040000 -l 0x40000</userinput> -RedBoot> <userinput>reset</userinput> -</programlisting> <warning><title>WARNING</title> -<para>You must type these commands exactly! Failure to do so may render your -iPAQ totally useless. Once you've done this, RedBoot should come up every -time you reset.</para> -</warning></para> -</sect3> -<sect3> -<title>Restoring Windows/CE</title> -<para>To restore Windows/CE from the backup taken in <xref linkend="ipaq-install-rb-permanently">, -visit <ulink url="http://www.handhelds.org/projects/wincerestoration.html">http://www.handhelds.org/projects/wincerestoration.html</ulink> -for directions. -</para> -</sect3></sect2> -<sect2> -<title>Additional commands</title> -<para>The <command>exec</command> command which allows the loading -and execution of Linux kernels, -is supported for this board (see <xref linkend="executing-programs">). The <command> -exec</command> parameters used for the iPAQ are:</para> -<variablelist><varlistentry> -<term>-b <replaceable><addr></replaceable></term> -<listitem><para>Location Linux kernel was loaded to</para></listitem></varlistentry> -<varlistentry><term> --l <replaceable><len></replaceable></term> -<listitem><para>Length of kernel</para></listitem></varlistentry> -<varlistentry><term> --c <replaceable>"params"</replaceable></term> -<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> -<varlistentry><term>-r <replaceable><addr></replaceable></term> -<listitem><para>'initrd' ramdisk location</para></listitem></varlistentry> -<varlistentry><term>-s <replaceable><len></replaceable></term> -<listitem><para>Length of initrd ramdisk</para></listitem></varlistentry> -</variablelist> -<para>Linux kernels may be run on the iPAQ using the sources from the anonymous -CVS repository at the Handhelds project (<ulink url="http://www.handhelds.org/"> -http://www.handhelds.org/</ulink>) with -the <filename>elinux.patch</filename> patch file applied. This file can be -found in the -<filename>misc/</filename> subdirectory of the iPAQ platform HAL in the -RedBoot sources, normally -<filename>hal/arm/sa11x0/ipaq/<replaceable>VERSION</replaceable>/misc/</filename> - </para> -<para> -On the iPAQ (and indeed all SA11x0 platforms), Linux expects to be loaded -at address 0xC0008000 and the entry point is also at 0xC0008000. -</para> - -</sect2> -<sect2> -<title>Memory Maps</title> -<para>RedBoot sets up the following memory map on the iPAQ: The first level -page table is located at physical address 0xC0004000. No second level tables -are used. <note><title>NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note> <programlisting>Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x01ffffff 16Mb to 32Mb FLASH (nCS0) [organized as below] - 0x000000 - 0x0003ffff Parrot Loader - 0x040000 - 0x0007ffff RedBoot - 0xf80000 - 0x00fbffff Fconfig data - 0xfc0000 - 0x00ffffff FIS directory -0x30000000 - 0x3fffffff Compact Flash -0x48000000 - 0x4bffffff iPAQ internal registers -0x80000000 - 0xbfffffff SA-1110 Internal Registers -0xc0000000 - 0xc1ffffff DRAM Bank 0 - 32Mb SDRAM -0xe0000000 - 0xe7ffffff Cache Clean - - -Virtual Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x01ffffff Y Y DRAM - 32Mb -0x30000000 - 0x3fffffff N N Compact Flash -0x48000000 - 0x4bffffff N N iPAQ internal registers -0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) -0x80000000 - 0xbfffffff N N SA-1110 Internal Registers -0xc0000000 - 0xc1ffffff N Y DRAM Bank 0: 32Mb -0xe0000000 - 0xe7ffffff Y Y Cache Clean </programlisting> </para> +0x00000000 - 0x003fffff DRAM +0xfa100000 - 0xfa100003 LEDs +0xfe000000 - 0xfe07ffff flash (AMD29F040B) +0xff000000 - 0xff0fffff MPC registers</programlisting></para> </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“ipaq”, “arm” and “sa11x0/ipaq” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/sa11x0/ipaq/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2></sect1> - -<?Pub _newpage> -<sect1 id="cerfcube"> -<title>Intrinsyc CerfCube</title> -<indexterm><primary>Intrinsyc CerfCube</primary><secondary>installing and -testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Intrinsyc CerfCube</secondary></indexterm> -<sect2> -<title>Overview</title> -<para>RedBoot supports the serial port and the builtin -ethernet connection for communication and downloads. -</para> -<para>The default serial port settings are 38400,8,N,1. RedBoot runs from -and supports flash management for the system flash region. </para> -</sect2> -<sect2> -<title>Initial Installation</title> -<para>Prebuilt images for redboot_ROM.bin -mentioned in the instructions below are provided. -</para> -<sect3> -<title>Installing RedBoot on the CerfCube using the Intrinsyc loader</title> -<para> -The original boot loader supplied with the CerfCube can be used to install -RedBoot. Connect to the device using a serial port at 38400/8N1. -Copy the redboot_ROM.bin image to an available TFTP server. -Issue these commands to the Instrinsyc loader. + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: <programlisting> - download tftp:xxx.x.x.xx redboot_ROM.bin 0xc0000000 - flashloader 0x00000000 0xc0000000 0x20000 -</programlisting> -where xxx.x.x.xx is the IP address of the TFTP server. -<note> -<title>NOTE</title> -<para> -Other installation methods may be available via the Intrinsyc loader. -Contact Intrinsyc for details. -</para> -</note> -</para> -</sect3> -<sect3 id="setting-up-and-testing-cerfcube-redboot"> -<title>Setting up and testing RedBoot</title> -<para>Once RedBoot has started, you should get information similar to this -on the serial port at 38400,8,N,1. -<programlisting>RedBoot(tm) bootstrap and debug environment [ROM] -Red Hat certified release, version R1.xx - built 06:17:41, Mar 19 2001 -Platform: Intrinsyc CerfCube (StrongARM 1110) - -Copyright (C) 2000, 2001, 2002, Red Hat, Inc. - -RAM: 0x00000000-0x02000000, 0x00012708-0x01fd1000 available -FLASH: 0x50000000 - 0x51000000, 128 blocks of 0x00020000 bytes each. +export TARGET=mbx +export ARCH_DIR=powerpc +export PLATFORM_DIR=mbx </programlisting> </para> -</sect3> -</sect2> -<sect2> -<title>Additional commands</title> -<para>The <command>exec</command> command which allows the loading -and execution of Linux kernels, -is supported for this board (see <xref linkend="executing-programs">). The <command> -exec</command> parameters used for the CerfCube are:</para> -<variablelist><varlistentry> -<term>-b <replaceable><addr></replaceable></term> -<listitem><para>Location Linux kernel was loaded to</para></listitem></varlistentry> -<varlistentry><term> --l <replaceable><len></replaceable></term> -<listitem><para>Length of kernel</para></listitem></varlistentry> -<varlistentry><term> --c <replaceable>"params"</replaceable></term> -<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> -<varlistentry><term>-r <replaceable><addr></replaceable></term> -<listitem><para>'initrd' ramdisk location</para></listitem></varlistentry> -<varlistentry><term>-s <replaceable><len></replaceable></term> -<listitem><para>Length of initrd ramdisk</para></listitem></varlistentry> -</variablelist> - -</sect2> -<sect2> -<title>Memory Maps</title> -<para>RedBoot sets up the following memory map on the CerfCube: The first level -page table is located at physical address 0xC0004000. No second level tables -are used. <note><title>NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note> <programlisting>Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x01ffffff 16Mb to 32Mb FLASH (nCS0) [organized as below] - 0x000000 - 0x0001ffff RedBoot - 0x020000 - 0x0003ffff RedBoot [RAM version] - 0xfc0000 - 0x00fdffff Fconfig data - 0xfe0000 - 0x00ffffff FIS directory -0x0f000000 - 0x0fffffff Onboard ethernet -0x10000000 - 0x17ffffff CerfCube internal registers -0x20000000 - 0x3fffffff PCMCIA / Compact Flash -0x80000000 - 0xbfffffff SA-1110 Internal Registers -0xc0000000 - 0xc1ffffff DRAM Bank 0 - 32Mb SDRAM -0xe0000000 - 0xe7ffffff Cache Clean - - -Virtual Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x01ffffff Y Y DRAM - 32Mb -0x08000000 - 0x0fffffff N N Onboard ethernet controller -0x10000000 - 0x17ffffff N N CerfCube internal registers -0x20000000 - 0x3fffffff N N PCMCIA / Compact Flash -0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) -0x80000000 - 0xbfffffff N N SA-1110 Internal Registers -0xc0000000 - 0xc1ffffff N Y DRAM Bank 0: 32Mb -0xe0000000 - 0xe7ffffff Y Y Cache Clean </programlisting> </para> -</sect2> - -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“cerf”, “arm” and “sa11x0/ipaq” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/sa11x0/cerf/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2></sect1> - -<?Pub _newpage> -<sect1 id="edb7xxx"> -<title>Cirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312) </title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Cirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312)</primary> -<secondary>installing and testing</secondary></indexterm><indexterm><primary> -installing and testing</primary><secondary>Cirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312) -</secondary></indexterm>RedBoot supports both serial ports on the board and -the ethernet port. The default serial port settings are 38400,8,N,1. RedBoot -also supports flash management on the EDB7xxx for the NOR flash only. Two -basic RedBoot configurations are supported: <itemizedlist> -<listitem><para>RedBoot running from the board's flash boot sector.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. -</para> -</listitem> -<listitem><para>EDB7312 only: RedBoot running from RAM copied directly from the -flash boot sector. -</para> -</listitem> -</itemizedlist></para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>A Windows or Linux utility is used to program flash using serial port -#1 via on-chip programming firmware. See board documentation for details on -in situ flash programming. </para> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Memory Maps </title> -<para>The MMU page tables and LCD display buffer, if enabled, are located -at the end of DRAM. <note><title>NOTE -</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note><programlisting> -Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x01ffffff NOR Flash (EDB7211, EDB7212) -0x00000000 - 0x00ffffff NOR Flash (EDB7312) -0x10000000 - 0x11ffffff NAND Flash -0x20000000 - 0x2fffffff Expansion 2 -0x30000000 - 0x3fffffff Expansion 3 -0x40000000 - 0x4fffffff PCMCIA 0 -0x50000000 - 0x5fffffff PCMCIA 1 -0x60000000 - 0x600007ff On-chip SRAM -0x80000000 - 0x8fffffff I/O registers -0xc0000000 - 0xc1ffffff DRAM (EDB7211, EDB7212) -0xc0000000 - 0xc0ffffff DRAM (EDB7312) - -Virtual Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x01ffffff Y Y DRAM -0x00000000 - 0x00fcffff Y Y DRAM (EDB7312) -0x20000000 - 0x2fffffff N N Expansion 2 -0x30000000 - 0x3fffffff N N Expansion 3 -0x40000000 - 0x4fffffff N N PCMCIA 0 -0x50000000 - 0x5fffffff N N PCMCIA 1 -0x60000000 - 0x600007ff Y Y On-chip SRAM -0x80000000 - 0x8fffffff N N I/O registers -0xc0000000 - 0xc001ffff N Y LCD buffer (if configured) -0xe0000000 - 0xe1ffffff Y Y NOR Flash (EDB7211, EDB7212) -0xe0000000 - 0xe0ffffff Y Y NOR Flash (EDB7312) -0xf0000000 - 0xf1ffffff Y Y NAND Flash - -The flash based RedBoot image occupies virtual addresses 0xe0000000 - 0xe003ffff. -</programlisting></para> -</sect2> -<sect2> -<title>Platform Resource Usage</title> -<para>The EP7xxx timer #2 is used as a polled timer to provide timeout support -for network and XModem file transfers.</para> -</sect2><sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for ARCH_DIR and PLATFORM_DIR on this platform are -“arm” and “edb7xxx” respectively. -The value for TARGET is either “edb7211” or “edb7212” - or “edb7312”, -depending on the desired platform. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/edb7xxx/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used, and the correct -edb7XXX variant chosen.</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2> </sect1> -<?Pub _newpage> -<sect1 id="nano"> -<title>Bright Star Engineering commEngine and nanoEngine</title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>commEngine</primary><secondary>installing and testing -</secondary></indexterm><indexterm><primary>nanoEngine</primary><secondary> -installing and testing</secondary></indexterm><indexterm><primary>installing -and testing</primary><secondary>commEngine</secondary></indexterm><indexterm> -<primary>installing and testing</primary><secondary>nanoEngine</secondary> -</indexterm>RedBoot supports a serial port and the built in ethernet port -for communication and downloads. The default serial port settings are 38400,8,N,1. -RedBoot runs from and supports flash management for the system flash region. -These configurations are supported:<itemizedlist> -<listitem><para>RedBoot running from the first free block at 0x40000</para> -</listitem> -<listitem><para>RedBoot running from RAM</para> -</listitem> -</itemizedlist></para> -</sect2> -<sect2> -<title>Initial Installation</title> -<para>Unlike other targets, the nanoEngine comes equipped with boot firmware -which you cannot modify. See chapter 5, "nanoEngine Firmware" of the <citetitle> -nanoEngine Hardware Reference Manual</citetitle> (we refer to "July 17, 2000 -Rev 0.6") from Bright Star Engineering. </para> -<para>Because of this, eCos, and therefore Redboot, only supports RAM and -POST startup types, rather than the more usual ROM, RAM and optionally, POST. -</para> -<para>Briefly, the POST-startup RedBoot image lives in flash following the -BSE firmware. The BSE firmware is configured, using its standard <computeroutput> -bootcmd</computeroutput> parameter, to jump into the RedBoot image at startup. -</para> -</sect2> -<sect2> -<title>Download Instructions</title> -<para>You can perform the initial load of the POST-startup RedBoot image into -flash using the BSE firmware's <command>load</command> command. -This will load a binary file, using TFTP, and program it into flash in one -operation. Because no memory management is used in the BSE firmware, flash -is mapped from address zero upwards, so the address for the RedBoot POST image -is 0x40000. You must use the binary version of RedBoot for this, <filename> -redboot-post.bin</filename>. </para> -<para>This assumes you have set up the other BSE firmware config parameters -such that it can communicate over your network to your TFTP server. <screen> - -><userinput>load /tftpboot/redboot-post.bin 40000</userinput> -loading ... erasing blk at 00040000 -erasing blk at 00050000 -94168 bytes loaded cksum 00008579 -done -> -> <userinput>set bootcmd "go 40000"</userinput> -> <userinput>get</userinput> -myip = 10.16.19.198 -netmask = 255.255.255.0 -eth = 0 -gateway = 10.16.19.66 -serverip = 10.16.19.66 -bootcmd = go 40000 -> </screen> <note><title>NOTE</title> -<para>the BSE firmware runs its serial IO at 9600 Baud; RedBoot runs instead -at 38400 Baud. You must select the right baud rate in your terminal program -to be able to set up the BSE firmware.</para> -</note> After a reset, the BSE firmware will print <screen>Boot: BSE 2000 Sep 12 2000 14:00:30 -autoboot: "go 40000" [hit ESC to abort]</screen>and then RedBoot starts, switching -to 38400 Baud.</para> -<para>Once you have installed a bootable RedBoot in the system in this manner, -we advise re-installing using the generic method described in <xref linkend="updating-redboot"> -in order that the Flash Image System contains an appropriate description of -the flash entries.</para> -</sect2> -<sect2> -<title>Cohabiting with POST in Flash</title> -<para>The configuration export file named <filename>redboot_POST.ecm</filename> -configures redboot to build for execution at address 0x50040000 (or, during -bootup, 0x00040000). This is to allow power-on self-test (POST) code or immutable -firmware to live in the lower addresses of the flash and to run before RedBoot -gets control. The assumption is that RedBoot will be entered at its base address -in physical memory, that is 0x00040000. </para> -<para>Alternatively, for testing, you can call it in an already running system -by using <userinput>go 0x50040040</userinput> at another RedBoot prompt, or -a branch to that address. The address is where the reset vector points, and -is reported by RedBoot's <userinput>tftp load</userinput> command and listed -by the <userinput>fis list</userinput> command, amongst other places. </para> -<para>Using the POST configuration enables a normal config option which causes -linking and initialization against memory layout files called "...post..." -rather than "...rom..." or "...ram..." in the <computeroutput>include/pkgconf -</computeroutput> directory. Specifically: <programlisting>665 Feb 9 17:57 include/pkgconf/mlt_arm_sa11x0_nano_post.h -839 Feb 9 17:57 include/pkgconf/mlt_arm_sa11x0_nano_post.ldi -585 Feb 9 17:57 include/pkgconf/mlt_arm_sa11x0_nano_post.mlt</programlisting>It -is these you should edit if you wish to move that execution address from 0x50040000 -in the POST configuration. Startup type naturally remains ROM in this configuration. - </para> -<para>Because the nanoEngine contains immutable boot firmware at the start -of flash, RedBoot for this target is configured to reserve that area in the -Flash Image System, and to create by default an entry for the POST startup -RedBoot. -<programlisting> -RedBoot> <userinput>fis list</userinput> -Name FLASH addr Mem addr Length Entry point -(reserved) 0x50000000 0x50000000 0x00040000 0x00000000 -RedBoot[post] 0x50040000 0x00100000 0x00020000 0x50040040 -RedBoot config 0x503E0000 0x503E0000 0x00010000 0x00000000 -FIS directory 0x503F0000 0x503F0000 0x00010000 0x00000000 -RedBoot> -</programlisting> -The entry "(reserved)" ensures that the FIS cannot attempt -to overwrite the BSE firmware, thus ensuring that the board remains bootable -and recoverable even after installing a broken RedBoot image.</para> -</sect2> -<sect2> -<title>Special RedBoot Commands</title> -<para>The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers -installed, but these have no associated serial EEPROM in which to record their -Ethernet Station Address (ESA, or MAC address). The BSE firmware records an -ESA for the device it uses, but this information is not available to RedBoot; -we cannot share it.</para> -<para>To keep the ESAs for the two ethernet interfaces, two new items of RedBoot -configuration data are introduced. You can list them with the RedBoot command <command> -fconfig -l</command> thus: -<programlisting> -RedBoot> <userinput>fconfig -l</userinput> -Run script at boot: false -Use BOOTP for network configuration: false -Local IP address: 10.16.19.91 -Default server IP address: 10.16.19.66 -Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99 -Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A -GDB connection port: 9000 -Network debug at boot time: false -RedBoot></programlisting>You should set them before running RedBoot or eCos -applications with the board connected to a network. The <command>fconfig -</command> command can be used as for any configuration data item; -the entire ESA is entered in one line.</para> -</sect2> -<sect2> -<title>Memory Maps</title> -<para>The first level page table is located at physical address 0xc0004000. - No second level tables are used. <note><title>NOTE</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note><programlisting>Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x003fffff 4Mb FLASH (nCS0) -0x18000000 - 0x18ffffff Internal PCI bus - 2 x i82559 ethernet -0x40000000 - 0x4fffffff External IO or PCI bus -0x80000000 - 0xbfffffff SA-1110 Internal Registers -0xc0000000 - 0xc7ffffff DRAM Bank 0 - 32Mb SDRAM -0xc8000000 - 0xcfffffff DRAM Bank 1 - empty -0xe0000000 - 0xe7ffffff Cache Clean - -Virtual Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x001fffff Y Y DRAM - 8Mb to 32Mb -0x18000000 - 0x180fffff N N Internal PCI bus - 2 x i82559 ethernet -0x40000000 - 0x4fffffff N N External IO or PCI bus -0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) -0x80000000 - 0xbfffffff N N SA-1110 Internal Registers -0xc0000000 - 0xc0ffffff N Y DRAM Bank 0: 8 or 16Mb -0xc8000000 - 0xc8ffffff N Y DRAM Bank 1: 8 or 16Mb or absent -0xe0000000 - 0xe7ffffff Y Y Cache Clean</programlisting>The FLASH based -RedBoot POST-startup image occupies virtual addresses 0x50040000 - 0x5005ffff. -</para> -<para>The ethernet devices use a "PCI window" to communicate with the CPU. -This is 1Mb of SDRAM which is shared with the ethernet devices that are on -the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI -accesses see correct data in the correct order. By default it is configured -to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be -modified, and indeed must be, if less than 32Mb of SDRAM is installed, via -the memory layout tool, or by moving the section <computeroutput>__pci_window -</computeroutput> referred to by symbols <computeroutput>CYGMEM_SECTION_pci_window* -</computeroutput> in the linker script. </para> -<para>Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM -bank 0, the code can cope with any of these combinations also; "2 x " in this -context means one device in each DRAM Bank. <programlisting>1 x 8Mb = 8Mb 2 x 8Mb = 16Mb -1 x 16Mb = 16Mb 2 x 16Mb = 32Mb</programlisting>All are programmed the same -in the memory controller. </para> -<para>Startup code detects which is fitted and programs the memory map accordingly. -If the device(s) is 8Mb, then there are gaps in the physical memory map, because -a high order address bit is not connected. The gaps are the higher 2Mb out -of every 4Mb. The SA11x0 OS timer is used as a polled timer to provide timeout -support within RedBoot.</para> -</sect2> -<sect2> -<title>Nano Platform Port</title> -<para>The nano is in the set of SA11X0-based platforms. It uses the arm architectural -HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components - <programlisting>CYGPKG_HAL_ARM hal/arm/arch/ -CYGPKG_HAL_ARM_SA11X0 hal/arm/sa11x0/var -CYGPKG_HAL_ARM_SA11X0_NANO hal/arm/sa11x0/nano</programlisting> respectively. - </para> -<para>The target name is "nano" which includes all these, plus the ethernet -driver packages, flash driver, and so on.</para> -</sect2> -<sect2> -<title>Ethernet Driver</title> -<para>The ethernet driver is in two parts: </para> -<para>A generic ether driver for Intel i8255x series devices, specifically -the i82559, is <computeroutput>devs/eth/intel/i82559</computeroutput>. Its -package name is <computeroutput>CYGPKG_DEVS_ETH_INTEL_I82559</computeroutput>. - </para> -<para>The platform-specific ether driver is <computeroutput>devs/eth/arm/nano -</computeroutput>. Its package is <computeroutput>CYGPKG_DEVS_ETH_ARM_NANO -</computeroutput>. This tells the generic driver the address in IO memory -of the chip, for example, and other configuration details. This driver picks -up the ESA from RedBoot's configuration data - unless configured to use a -static ESA in the usual manner. </para> -</sect2><sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“nano”, “arm” and “sa11x0/nano” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/sa11x0/nano/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="x86pc"> -<title>x86 Based PC</title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>x86 Based PC</primary><secondary>installing and -testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>x86 Based PC</secondary></indexterm>RedBoot supports -two serial ports and an Intel i82559 based ethernet card (for example an Intel -EtherExpress Pro 10/100) for communication and downloads. The default serial -port settings are 38400,8,N,1. RedBoot runs from a boot floppy disk installed -in the A: drive of the PC.</para> -</sect2> -<sect2> -<title>Initial Installation</title> -<para>RedBoot takes the form of a self-booting image that must be written -onto a formatted floppy disk. The process will erase any file system or data -that already exists on that disk, so proceed with caution.</para> -<para>For Red Hat Linux users, this can be done by:</para> -<screen> $ <userinput>dd conv=sync if=install/bin/redboot.bin of=/dev/fd0H1440 -</userinput></screen> -<para>For NT Cygwin users, this can be done by first ensuring that the raw -floppy device is mounted as <filename>/dev/fd0</filename>. To check if this -is the case, type the command <userinput>mount</userinput> at the Cygwin bash -prompt. If the floppy drive is already mounted, it will be listed as something -similar to the following line:</para> -<screen> \\.\a: /dev/fd0 user binmode</screen> -<para>If this line is not listed, then mount the floppy drive using the command: -</para> -<screen> $ <userinput>mount -f -b //./a: /dev/fd0</userinput></screen> -<para>To actually install the boot image on the floppy, use the command:</para> -<screen> $ <userinput>dd conv=sync if=install/bin/redboot.bin of=/dev/fd0 -</userinput></screen> -<para>Insert this floppy in the A: drive of the PC to be used as a target -and ensure that the BIOS is configured to boot from A: by default. On reset, -the PC will boot from the floppy and be ready to be debugged via either serial -line, or via the ethernet interface if it is installed.</para> -<note><title>NOTE</title> -<para>Unreliable floppy media may cause the write to silently fail. This -can be determined if the RedBoot image does not correctly -boot. In such cases, the floppy should be (unconditionally) reformatted -using the <command>fdformat</command> command on Linux, or -<command>format a: /u</command> on DOS/Windows.</para> -</note> -</sect2> -<sect2> -<title>Flash management</title> -<para>PC RedBoot does not support any FLASH commands.</para> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Memory Maps </title> -<para>All selectors are initialized to map the entire 32-bit address space -in the familiar protected mode flat model. Page translation is not used. -RAM up to 640K is mapped to 0x0 to 0xa0000. RAM above 640K is mapped -from address 0x100000 upwards. Space is reserved between 0xa0000 and -0x100000 for option ROMs and the BIOS. -</para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“pc”, “i386” and “pc” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/i386/pc/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used. In particular, the -<filename>redboot_FLOPPY.ecm</filename> file is used for building a version -of RedBoot suitable for booting off a floppy disk.</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="CalmRISC16"> -<title>Samsung CalmRISC16 Core Evaluation Board </title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Samsung CalmRISC16 Core EVB</primary><secondary>installing -and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Samsung CalmRISC16 Core EVB</secondary></indexterm> The -Samsung CalmRISC16 evaluation platform consists of two boards connected by a -ribbon cable. One board contains the CPU core and memory. The other board is -called the MDSChip board and provides the host interface. The calmRISC16 is a -harvard architecture with separate 22-bit program and data addresses. The -instruction set provides no instruction for writing to program memory. The -MDSChip board firmware (called CalmBreaker) provides a pseudo register interface -so that code running on the core has access to a serial channel and a mechanism -to write to program memory. The serial channel is fixed at 57600-8-N-1 by the -firmware. The CalmBreaker firmware also provides a serial protocol which -allows a host to download a program and to start or stop the core board.</para> -<para>Only a ROM startup RedBoot configuration is supported.</para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>The CalmRISC16 core is controlled through the MDSChip board. There is -no non-volatile storage available for RedBoot, so RedBoot must be downloaded -to the board on every power cycle. A small utility program is used to download -S-record files to the eval board. Sources and build instructions for this -utility are located in the RedBoot sources in: -<programlisting> .../packages/hal/calmrisc16/ceb/current/support -</programlisting></para> -<para>To download the RedBoot image, first press the reset button on the MDSChip -board. The green 'Run' LED on the core board should go off. Now, use the -utility to download the RedBoot image with: -<programlisting> % calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf -</programlisting> -Note that the '-p /dev/term/b' specifies the serial port to use and will vary -from system to syetm. The download will take about two minutes. After it -finishes, start RedBoot with: -<programlisting> % calmbreaker -p /dev/term/b --run</programlisting> -The 'Run' LED on the core board should be on. Connecting to the MDSboard with -a terminal and typing enter should result in RedBoot reprinting the command -prompt. -</para> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Special Note on Serial Channel </title> -<para>The MDSChip board uses a relatively slow microcontroller to provide -the pseudo-register interface to the core board. This pseudo-register -interface provides access to the serial channel and write access to program -memory. Those interfaces are slow and the serial channel is easily overrun -by a fast host. For this reason, GDB must be told to limit the size of code -download packets to avoid serial overrun. This is done with the following -GDB command: -<programlisting> (gdb) set download-write-size 25</programlisting> -</para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“calm16_ceb”, “calmrisc16” and “ceb” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/calmrisc16/ceb/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="CalmRISC32"> -<title>Samsung CalmRISC32 Core Evaluation Board </title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Samsung CalmRISC32 Core EVB</primary><secondary>installing -and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Samsung CalmRISC32 Core EVB</secondary></indexterm> The -Samsung CalmRISC32 evaluation platform consists of two boards connected by a -ribbon cable. One board contains the CPU core and memory. The other board is -called the MDSChip board and provides the host interface. The calmRISC32 is a -harvard architecture with separate 32-bit program and data addresses. The -instruction set provides no instruction for writing to program memory. The -MDSChip board firmware (called CalmBreaker) provides a pseudo register interface -so that code running on the core has access to a serial channel and a mechanism -to write to program memory. The serial channel is fixed at 57600-8-N-1 by the -firmware. The CalmBreaker firmware also provides a serial protocol which -allows a host to download a program and to start or stop the core board.</para> -<para>Only a ROM startup RedBoot configuration is supported.</para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>The calmRISC32 core is controlled through the MDSChip board. There is -no non-volatile storage available for RedBoot, so RedBoot must be downloaded -to the board on every power cycle. A small utility program is used to download -S-record files to the eval board. Sources and build instructions for this -utility are located in the RedBoot sources in: -<programlisting> .../packages/hal/calmrisc32/ceb/current/support -</programlisting></para> -<para>To download the RedBoot image, first press the reset button on the MDSChip -board. The green 'Run' LED on the core board should go off. Now, use the -utility to download the RedBoot image with: -<programlisting> % calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf -</programlisting> -Note that the '-p /dev/term/b' specifies the serial port to use and will vary -from system to syetm. The download will take about two minutes. After it -finishes, start RedBoot with: -<programlisting> % calmbreaker -p /dev/term/b --run</programlisting> -The 'Run' LED on the core board should be on. Connecting to the MDSboard with -a terminal and typing enter should result in RedBoot reprinting the command -prompt. -</para> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Special Note on Serial Channel </title> -<para>The MDSChip board uses a relatively slow microcontroller to provide -the pseudo-register interface to the core board. This pseudo-register -interface provides access to the serial channel and write access to program -memory. Those interfaces are slow and the serial channel is easily overrun -by a fast host. For this reason, GDB must be told to limit the size of code -download packets to avoid serial overrun. This is done with the following -GDB command: -<programlisting> (gdb) set download-write-size 25</programlisting> -</para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“calm32_ceb”, “calmrisc32” and “ceb” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/calmrisc32/ceb/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> + + + + +<!-- ********************** SuperH ************************ --> + + <?Pub _newpage> <sect1 id="edk7708"> -<title>Hitachi EDK7708 (edk7708)</title> +<title>SuperH/SH3(SH7708) Hitachi EDK7708</title> <sect2> <title>Overview</title> <para><indexterm><primary>Hitachi SH EDK7708</primary><secondary>installing @@ -2900,148 +4771,26 @@ 0xb8000000 - 0xb80000ff LED ON </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“edk7708”, “sh” and “edk7708” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/sh/edk7708/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> - -<?Pub _newpage> -<sect1 id="se77x9"> -<title>Hitachi Solution Engine 77X9 (SE77X9)</title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Hitachi SH SE77X9</primary><secondary>installing -and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Hitachi SH SE77X9</secondary></indexterm>This -description covers the MS7729SE01 and MS7709SSE0101 variants. See <xref linkend="se7709"> -for instructions for the MS7709SE01 variant.</para> - -<para>RedBoot uses -the COM1 and COM2 serial ports. The default serial port settings are 38400,8,N,1. -Ethernet is also supported using the 10-base T connector. </para> -<para>Management of onboard flash is also supported. Two basic RedBoot configurations -are supported: <itemizedlist> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=edk7708 +export ARCH_DIR=sh +export PLATFORM_DIR=edk7708 +</programlisting> </para> -</listitem> -<listitem><para>RedBoot running from the board's flash boot sector. </para> -</listitem> -</itemizedlist></para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>The Solution Engine ships with the Hitachi boot monitor in EPROM -which allows for initial programming of RedBoot:</para> - -<orderedlist> -<listitem><para>Set switches SW4-3 and SW4-4 to ON [boot from EPROM]</para> -</listitem> -<listitem><para>Connect a serial cable to COM2 and power up the board.</para> -</listitem> -<listitem><para>After the boot monitor banner, invoke the flash -download/program command:<programlisting>Ready >fl</programlisting></para> -</listitem> -<listitem><para>The monitor should now ask for input: -<programlisting>Flash ROM data copy to RAM -Please Send A S-format Record</programlisting>At this point copy the -RedBoot ROM SREC file to the serial port:<programlisting> -$ cat redboot_ROM.eprom.srec > /dev/ttyS0</programlisting>Eventually you -should see something like<programlisting>Start Addrs = A1000000 -End Addrs = A1xxxxxx -Transfer complete</programlisting> from the monitor. -</para></listitem> -<listitem><para>Set switch SW4-3 to OFF [boot from flash] and reboot the board. You -should now see the RedBoot banner.</para> -</listitem> -</orderedlist> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>The <command>exec</command> command which allows the loading -and execution of Linux kernels -is supported for this board (see <xref linkend="executing-programs">). The <command> -exec</command> parameters used for the SE77x9 are:</para> -<variablelist> -<varlistentry> -<term>-b <replaceable><addr></replaceable></term> -<listitem><para>Parameter block address. This is normally the first -page of the kernel image and defaults to 0x8c101000</para></listitem></varlistentry> - -<varlistentry><term>-i <replaceable><addr></replaceable></term> -<listitem><para>Start address of initrd -image</para></listitem></varlistentry> - -<varlistentry><term>-j <replaceable><size></replaceable></term> -<listitem><para>Size of initrd image</para></listitem></varlistentry> - -<varlistentry><term>-c <replaceable>"args"</replaceable></term> -<listitem><para>Kernel arguments string</para></listitem></varlistentry> - -<varlistentry><term> --m <replaceable><flags></replaceable></term> -<listitem><para>Mount rdonly flags. If set to a non-zero value the -root partition will be mounted read-only.</para></listitem></varlistentry> - -<varlistentry><term> --f <replaceable><flags></replaceable></term> -<listitem><para>RAM disk flags. Should normally be 0x4000</para></listitem></varlistentry> - -<varlistentry><term>-r <replaceable><device number></replaceable></term> -<listitem><para>Root device specification. /dev/ram is 0x0101</para></listitem></varlistentry> - -<varlistentry><term>-l <replaceable><type></replaceable></term> -<listitem><para>Loader type</para></listitem></varlistentry> - -</variablelist> - -<para>Finally the kernel entry address can be specified as an optional -argument. The default is 0x8c102000</para> - -<para> -On the SE77x9, Linux expects to be loaded at address 0x8c101000 with -the entry point at 0x8c102000. This is configurable in the kernel -using the CONFIG_MEMORY_START option. -</para> - -</sect2> -<sect2> -<title>Memory Maps </title> -<para>RedBoot sets up the following memory map on the SE77x9 board.<programlisting> -Physical Address Range Description ------------------------ ----------- -0x80000000 - 0x803fffff Flash (MBM29LV160) -0x81000000 - 0x813fffff EPROM (M27C800) -0x8c000000 - 0x8dffffff SDRAM -0xb0000000 - 0xb03fffff Ethernet (DP83902A) -0xb0400000 - 0xb07fffff SuperIO (FDC37C935A) -0xb0800000 - 0xb0bfffff Switches -0xb0c00000 - 0xbfffffff LEDs -0xb1800000 - 0xb1bfffff PCMCIA (MaruBun) -</programlisting></para> -</sect2> -<sect2> -<title>Ethernet Driver</title> -<para>The ethernet driver uses a hardwired ESA which can, at present, -only be changed in CDL.</para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“se77x9”, “sh” and “se77x9” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/sh/se77x9/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> + </sect2> </sect1> <?Pub _newpage> <sect1 id="se7709"> -<title>Hitachi Solution Engine 7709 (SE77X9)</title> +<title>SuperH/SH3(SH7709) Hitachi Solution Engine 7709</title> <sect2> <title>Overview</title> <para><indexterm><primary>Hitachi SH SE7709</primary><secondary>installing @@ -3073,16 +4822,16 @@ which allows for initial programming of <listitem><para>Connect a serial cable to CN1 (SCI) and power up the board.</para> </listitem> <listitem><para>After the boot monitor banner, invoke the flash -download/program command:<programlisting>Ready >fl</programlisting></para> +download/program command:<screen>Ready >fl</screen></para> </listitem> <listitem><para>The monitor should now ask for input: -<programlisting>Flash ROM data copy to RAM -Please Send A S-format Record</programlisting>At this point copy the -RedBoot ROM SREC file to the serial port:<programlisting> -$ cat redboot_SE7709RP_ROM.eprom.srec > /dev/ttyS0</programlisting>Eventually you -should see something like<programlisting>Start Addrs = A1000000 +<screen>Flash ROM data copy to RAM +Please Send A S-format Record</screen>At this point copy the +RedBoot ROM SREC file to the serial port:<screen> +$ cat redboot_SE7709RP_ROM.eprom.srec > /dev/ttyS0</screen>Eventually you +should see something like<screen>Start Addrs = A1000000 End Addrs = A1xxxxxx -Transfer complete</programlisting> from the monitor. +Transfer complete</screen> from the monitor. </para></listitem> <listitem><para>Set switch SW4-1 to OFF [boot from flash] and reboot the board. You should now see the RedBoot banner.</para> @@ -3164,19 +4913,305 @@ only be changed in CDL.</para> </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“se77x9”, “sh” and “se77x9” respectively. -Note that the configuration export files (containing SE7709RP -substring) supplied in the <computeroutput> -hal/sh/se77x9/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=se77x9 +export ARCH_DIR=sh +export PLATFORM_DIR=se77x9 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="hs7729pci"> +<title>SuperH/SH3(SH7729) Hitachi HS7729PCI</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Hitachi SH HS7729PCI</primary><secondary>installing +and testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Hitachi SH HS7729PCI</secondary></indexterm>RedBoot uses +the COM1 and COM2 serial ports (and the debug port on the +motherboard). +The default serial port settings are 38400,8,N,1. +Ethernet is also supported using a D-Link DFE-530TX PCI plugin card.</para> +<para>Management of onboard flash is also supported. Two basic RedBoot configurations +are supported: <itemizedlist> +<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. +</para> +</listitem> +<listitem><para>RedBoot running from the board's flash boot sector. </para> +</listitem> +</itemizedlist></para> +</sect2> +<sect2> +<title>Initial Installation Method </title> +<para>A copy of the ROM startup version of RedBoot must be programmed +into the two EPROMs. Two files with a split version of the ROM image is +provided: it is also possible to recreate these from the redboot.bin +file, but requires the split_word.c program in +hal/sh/hs7729pci/<replaceable>VERSION</replaceable>/misc to be built +and executed with the redboot.bin filename as sole argument.</para> + +<para>After doing this it is advised that another ROM version of +RedBoot is programmed into the flash, and that copy be used for +booting the board. This allows for software programmed updates of +RedBoot instead of having to reprogram the EPROMs.</para> + +<orderedlist> +<listitem><para>Program the EPROMs with RedBoot. The .lo image should +go in socket M1 and the .hi image in socket M2. +</para> +</listitem> +<listitem><para>Set switch SW1-6 to ON [boot from EPROM]</para> +</listitem> +<listitem><para>Follow the instructions under Flash management for +updating the flash copy of RedBoot, but use +<screen>-f 0x80400000</screen> due to setting of +the SW1-6 switch.</para> +</listitem> +<listitem><para>Set switch SW1-6 to OFF [boot from flash] and reboot the board. You +should now see the RedBoot banner. At this time you may want to issue +the command <command>fis init</command> to initialize +the flash table with the correct addresses.</para> +</listitem> +</orderedlist> + + +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>The <command>exec</command> command which allows the loading +and execution of Linux kernels +is supported for this board (see <xref linkend="executing-programs">). The <command> +exec</command> parameters used for the HS7729PCI are:</para> +<variablelist> +<varlistentry> +<term>-b <replaceable><addr></replaceable></term> +<listitem><para>Parameter block address. This is normally the first +page of the kernel image and defaults to 0x8c101000</para></listitem></varlistentry> + +<varlistentry><term>-i <replaceable><addr></replaceable></term> +<listitem><para>Start address of initrd +image</para></listitem></varlistentry> + +<varlistentry><term>-j <replaceable><size></replaceable></term> +<listitem><para>Size of initrd image</para></listitem></varlistentry> + +<varlistentry><term>-c <replaceable>"args"</replaceable></term> +<listitem><para>Kernel arguments string</para></listitem></varlistentry> + +<varlistentry><term> +-m <replaceable><flags></replaceable></term> +<listitem><para>Mount rdonly flags. If set to a non-zero value the +root partition will be mounted read-only.</para></listitem></varlistentry> + +<varlistentry><term> +-f <replaceable><flags></replaceable></term> +<listitem><para>RAM disk flags. Should normally be 0x4000</para></listitem></varlistentry> + +<varlistentry><term>-r <replaceable><device number></replaceable></term> +<listitem><para>Root device specification. /dev/ram is 0x0101</para></listitem></varlistentry> + +<varlistentry><term>-l <replaceable><type></replaceable></term> +<listitem><para>Loader type</para></listitem></varlistentry> + +</variablelist> + +<para>Finally the kernel entry address can be specified as an optional +argument. The default is 0x8c102000</para> + +<para> +On the HS7729PCI, Linux expects to be loaded at address 0x8c101000 with +the entry point at 0x8c102000. This is configurable in the kernel +using the CONFIG_MEMORY_START option. +</para> + +</sect2> +<sect2> +<title>Memory Maps </title> +<para>RedBoot sets up the following memory map on the HS7729PCI board.<programlisting> +Physical Address Range Description +----------------------- ----------- +0x80000000 - 0x803fffff Flash (MBM29LV160) +0x80400000 - 0x807fffff EPROM (M27C800) +0x82000000 - 0x82ffffff SRAM +0x89000000 - 0x89ffffff SRAM +0x8c000000 - 0x8fffffff SDRAM +0xa8000000 - 0xa800ffff SuperIO (FDC37C935A) +0xa8400000 - 0xa87fffff USB function (ML60851C) +0xa8800000 - 0xa8bfffff USB host (SL11HT) +0xa8c00000 - 0xa8c3ffff Switches +0xa8c40000 - 0xa8c7ffff LEDs +0xa8c80000 - 0xa8cfffff Interrupt controller +0xb0000000 - 0xb3ffffff PCI (SD0001) +0xb8000000 - 0xbbffffff PCMCIA (MaruBun) +</programlisting></para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=hs7729pci +export ARCH_DIR=sh +export PLATFORM_DIR=hs7729pci +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> +</sect2> +</sect1> + +<?Pub _newpage> +<sect1 id="se77x9"> +<title>SuperH/SH3(SH77X9) Hitachi Solution Engine 77X9</title> +<sect2> +<title>Overview</title> +<para><indexterm><primary>Hitachi SH SE77X9</primary><secondary>installing +and testing</secondary></indexterm><indexterm><primary>installing and testing +</primary><secondary>Hitachi SH SE77X9</secondary></indexterm>This +description covers the MS7729SE01 and MS7709SSE0101 variants. See <xref linkend="se7709"> +for instructions for the MS7709SE01 variant.</para> + +<para>RedBoot uses +the COM1 and COM2 serial ports. The default serial port settings are 38400,8,N,1. +Ethernet is also supported using the 10-base T connector. </para> +<para>Management of onboard flash is also supported. Two basic RedBoot configurations +are supported: <itemizedlist> +<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. +</para> +</listitem> +<listitem><para>RedBoot running from the board's flash boot sector. </para> +</listitem> +</itemizedlist></para> +</sect2> +<sect2> +<title>Initial Installation Method </title> +<para>The Solution Engine ships with the Hitachi boot monitor in EPROM +which allows for initial programming of RedBoot:</para> + +<orderedlist> +<listitem><para>Set switches SW4-3 and SW4-4 to ON [boot from EPROM]</para> +</listitem> +<listitem><para>Connect a serial cable to COM2 and power up the board.</para> +</listitem> +<listitem><para>After the boot monitor banner, invoke the flash +download/program command:<screen>Ready >fl</screen></para> +</listitem> +<listitem><para>The monitor should now ask for input: +<screen>Flash ROM data copy to RAM +Please Send A S-format Record</screen>At this point copy the +RedBoot ROM SREC file to the serial port:<screen> +$ cat redboot_ROM.eprom.srec > /dev/ttyS0</screen>Eventually you +should see something like<screen>Start Addrs = A1000000 +End Addrs = A1xxxxxx +Transfer complete</screen> from the monitor. +</para></listitem> +<listitem><para>Set switch SW4-3 to OFF [boot from flash] and reboot the board. You +should now see the RedBoot banner.</para> +</listitem> +</orderedlist> +</sect2> +<sect2> +<title>Special RedBoot Commands </title> +<para>The <command>exec</command> command which allows the loading +and execution of Linux kernels +is supported for this board (see <xref linkend="executing-programs">). The <command> +exec</command> parameters used for the SE77x9 are:</para> +<variablelist> +<varlistentry> +<term>-b <replaceable><addr></replaceable></term> +<listitem><para>Parameter block address. This is normally the first +page of the kernel image and defaults to 0x8c101000</para></listitem></varlistentry> + +<varlistentry><term>-i <replaceable><addr></replaceable></term> +<listitem><para>Start address of initrd +image</para></listitem></varlistentry> + +<varlistentry><term>-j <replaceable><size></replaceable></term> +<listitem><para>Size of initrd image</para></listitem></varlistentry> + +<varlistentry><term>-c <replaceable>"args"</replaceable></term> +<listitem><para>Kernel arguments string</para></listitem></varlistentry> + +<varlistentry><term> +-m <replaceable><flags></replaceable></term> +<listitem><para>Mount rdonly flags. If set to a non-zero value the +root partition will be mounted read-only.</para></listitem></varlistentry> + +<varlistentry><term> +-f <replaceable><flags></replaceable></term> +<listitem><para>RAM disk flags. Should normally be 0x4000</para></listitem></varlistentry> + +<varlistentry><term>-r <replaceable><device number></replaceable></term> +<listitem><para>Root device specification. /dev/ram is 0x0101</para></listitem></varlistentry> + +<varlistentry><term>-l <replaceable><type></replaceable></term> +<listitem><para>Loader type</para></listitem></varlistentry> + +</variablelist> + +<para>Finally the kernel entry address can be specified as an optional +argument. The default is 0x8c102000</para> + +<para> +On the SE77x9, Linux expects to be loaded at address 0x8c101000 with +the entry point at 0x8c102000. This is configurable in the kernel +using the CONFIG_MEMORY_START option. +</para> + +</sect2> +<sect2> +<title>Memory Maps </title> +<para>RedBoot sets up the following memory map on the SE77x9 board.<programlisting> +Physical Address Range Description +----------------------- ----------- +0x80000000 - 0x803fffff Flash (MBM29LV160) +0x81000000 - 0x813fffff EPROM (M27C800) +0x8c000000 - 0x8dffffff SDRAM +0xb0000000 - 0xb03fffff Ethernet (DP83902A) +0xb0400000 - 0xb07fffff SuperIO (FDC37C935A) +0xb0800000 - 0xb0bfffff Switches +0xb0c00000 - 0xbfffffff LEDs +0xb1800000 - 0xb1bfffff PCMCIA (MaruBun) +</programlisting></para> +</sect2> +<sect2> +<title>Ethernet Driver</title> +<para>The ethernet driver uses a hardwired ESA which can, at present, +only be changed in CDL.</para> +</sect2> +<sect2> +<title>Rebuilding RedBoot</title> + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: +<programlisting> +export TARGET=se77x9 +export ARCH_DIR=sh +export PLATFORM_DIR=se77x9 +</programlisting> +</para> + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> </sect2> </sect1> <?Pub _newpage> <sect1 id="se7751"> -<title>Hitachi Solution Engine 7751 (SE7751)</title> +<title>SuperH/SH4(SH7751) Hitachi Solution Engine 7751</title> <sect2> <title>Overview</title> <para><indexterm><primary>Hitachi SH SE7751</primary><secondary>installing @@ -3204,16 +5239,16 @@ which allows for initial programming of <listitem><para>Connect a serial cable to COM1 and power up the board.</para> </listitem> <listitem><para>After the boot monitor banner, invoke the flash -download/program command:<programlisting>Ready >fl</programlisting></para> +download/program command:<screen>Ready >fl</screen></para> </listitem> <listitem><para>The monitor should now ask for input: -<programlisting>Flash ROM data copy to RAM -Please Send A S-format Record</programlisting>At this point copy the -RedBoot ROM SREC file to the serial port:<programlisting> -$ cat redboot_ROM.eprom.srec > /dev/ttyS0</programlisting>Eventually you -should see something like<programlisting>Start Addrs = A1000000 +<screen>Flash ROM data copy to RAM +Please Send A S-format Record</screen>At this point copy the +RedBoot ROM SREC file to the serial port:<screen> +$ cat redboot_ROM.eprom.srec > /dev/ttyS0</screen>Eventually you +should see something like<screen>Start Addrs = A1000000 End Addrs = A1xxxxxx -Transfer complete</programlisting> from the monitor. +Transfer complete</screen> from the monitor. </para></listitem> <listitem><para>Set switch SW5-3 to OFF [boot from flash] and reboot the board. You should now see the RedBoot banner.</para> @@ -3292,1170 +5327,20 @@ only be changed in CDL.</para> </sect2> <sect2> <title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“se7751”, “sh” and “se7751” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/sh/se7751/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> - -<?Pub _newpage> -<sect1 id="hs7729pci"> -<title>Hitachi HS7729PCI</title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Hitachi SH HS7729PCI</primary><secondary>installing -and testing</secondary></indexterm><indexterm><primary>installing and testing -</primary><secondary>Hitachi SH HS7729PCI</secondary></indexterm>RedBoot uses -the COM1 and COM2 serial ports (and the debug port on the -motherboard). -The default serial port settings are 38400,8,N,1. -Ethernet is also supported using a D-Link DFE-530TX PCI plugin card.</para> -<para>Management of onboard flash is also supported. Two basic RedBoot configurations -are supported: <itemizedlist> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. -</para> -</listitem> -<listitem><para>RedBoot running from the board's flash boot sector. </para> -</listitem> -</itemizedlist></para> -</sect2> -<sect2> -<title>Initial Installation Method </title> -<para>A copy of the ROM startup version of RedBoot must be programmed -into the two EPROMs. Two files with a split version of the ROM image is -provided: it is also possible to recreate these from the redboot.bin -file, but requires the split_word.c program in -hal/sh/hs7729pci/<replaceable>VERSION</replaceable>/misc to be built -and executed with the redboot.bin filename as sole argument.</para> - -<para>After doing this it is advised that another ROM version of -RedBoot is programmed into the flash, and that copy be used for -booting the board. This allows for software programmed updates of -RedBoot instead of having to reprogram the EPROMs.</para> - -<orderedlist> -<listitem><para>Program the EPROMs with RedBoot. The .lo image should -go in socket M1 and the .hi image in socket M2. -</para> -</listitem> -<listitem><para>Set switch SW1-6 to ON [boot from EPROM]</para> -</listitem> -<listitem><para>Follow the instructions under Flash management for -updating the flash copy of RedBoot, but use -<programlisting>-f 0x80400000</programlisting> due to setting of -the SW1-6 switch.</para> -</listitem> -<listitem><para>Set switch SW1-6 to OFF [boot from flash] and reboot the board. You -should now see the RedBoot banner. At this time you may want to issue -the command <programlisting>fis init</programlisting> to initialize -the flash table with the correct addresses.</para> -</listitem> -</orderedlist> - - -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>The <command>exec</command> command which allows the loading -and execution of Linux kernels -is supported for this board (see <xref linkend="executing-programs">). The <command> -exec</command> parameters used for the HS7729PCI are:</para> -<variablelist> -<varlistentry> -<term>-b <replaceable><addr></replaceable></term> -<listitem><para>Parameter block address. This is normally the first -page of the kernel image and defaults to 0x8c101000</para></listitem></varlistentry> - -<varlistentry><term>-i <replaceable><addr></replaceable></term> -<listitem><para>Start address of initrd -image</para></listitem></varlistentry> - -<varlistentry><term>-j <replaceable><size></replaceable></term> -<listitem><para>Size of initrd image</para></listitem></varlistentry> - -<varlistentry><term>-c <replaceable>"args"</replaceable></term> -<listitem><para>Kernel arguments string</para></listitem></varlistentry> - -<varlistentry><term> --m <replaceable><flags></replaceable></term> -<listitem><para>Mount rdonly flags. If set to a non-zero value the -root partition will be mounted read-only.</para></listitem></varlistentry> - -<varlistentry><term> --f <replaceable><flags></replaceable></term> -<listitem><para>RAM disk flags. Should normally be 0x4000</para></listitem></varlistentry> - -<varlistentry><term>-r <replaceable><device number></replaceable></term> -<listitem><para>Root device specification. /dev/ram is 0x0101</para></listitem></varlistentry> - -<varlistentry><term>-l <replaceable><type></replaceable></term> -<listitem><para>Loader type</para></listitem></varlistentry> - -</variablelist> - -<para>Finally the kernel entry address can be specified as an optional -argument. The default is 0x8c102000</para> - -<para> -On the HS7729PCI, Linux expects to be loaded at address 0x8c101000 with -the entry point at 0x8c102000. This is configurable in the kernel -using the CONFIG_MEMORY_START option. -</para> - -</sect2> -<sect2> -<title>Memory Maps </title> -<para>RedBoot sets up the following memory map on the HS7729PCI board.<programlisting> -Physical Address Range Description ------------------------ ----------- -0x80000000 - 0x803fffff Flash (MBM29LV160) -0x80400000 - 0x807fffff EPROM (M27C800) -0x82000000 - 0x82ffffff SRAM -0x89000000 - 0x89ffffff SRAM -0x8c000000 - 0x8fffffff SDRAM -0xa8000000 - 0xa800ffff SuperIO (FDC37C935A) -0xa8400000 - 0xa87fffff USB function (ML60851C) -0xa8800000 - 0xa8bfffff USB host (SL11HT) -0xa8c00000 - 0xa8c3ffff Switches -0xa8c40000 - 0xa8c7ffff LEDs -0xa8c80000 - 0xa8cfffff Interrupt controller -0xb0000000 - 0xb3ffffff PCI (SD0001) -0xb8000000 - 0xbbffffff PCMCIA (MaruBun) -</programlisting></para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are -“hs7729pci”, “sh” and “hs7729pci” respectively. -Note that the configuration export files supplied in the <computeroutput> -hal/sh/hs7729pci/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> - - -<?Pub _newpage> -<sect1 id="at91"> -<title>Atmel AT91 Evaluation Board (EB40)</title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Atmel AT91/EB40</primary> -<secondary>installing and testing</secondary></indexterm><indexterm><primary> -installing and testing</primary><secondary>Atmel AT91/EB40 -</secondary></indexterm>RedBoot supports both serial ports. -The default serial port settings are 38400,8,N,1. RedBoot -also supports minimal flash management on the EB40. -However, since the flash device (AT29LV1024) is so small (only the upper 64K is -available for general use), only 'fconfig' is -supported, along with the simple flash write command, 'fis write'. -Two -basic RedBoot configurations are supported: <itemizedlist> -<listitem><para>RedBoot running from RAM, but contained in the board's flash boot sector -(ROMRAM mode).</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. -</para> -</listitem> -</itemizedlist> -The RAM version is only used during the initialization of RedBoot the first time. -</para> -</sect2> - -<sect2> -<title>Initial Installation Method </title> -<para> -This development board comes with ARM's debug tool, Angel, installed in flash. -At this time, Angel will not be replaced. Rather, RedBoot will be placed in -the alternate half of flash. Switch SW1 is used which monitor to boot. Selecting -SW1 to "lower mem" will choose Angel. Select SW1 to "Upper mem" for RedBoot once -it has been installed. -</para> -<para> -Set SW1 to "lower mem" and connect serial port A to a host computer. Using GDB -from the host and Angel on the board, download the RAM based version of RedBoot -to the board. Once this is started, the Angel session must be interrupted (on -Linux this can be done using ^Z). Follow this by connecting to the board using -minicom at 38400-8N1. At this point, RedBoot will be running on the board in -RAM. Now, download the ROMRAM version and program it to flash. Be sure and -first set SW1 to "upper mem". -<programlisting> -arm-elf-gdb redboot_RAM.elf -(gdb) tar rdi s=/dev/ttyS0 -Angel Debug Monitor (serial) 1.04 (Advanced RISC Machines SDT 2.5) for -AT91EB40 (2.00) -Angel Debug Monitor rebuilt on Apr 07 2000 at 12:40:31 -Serial Rate: 9600 -Connected to ARM RDI target. -(gdb) set $ps=0xd3 -(gdb) lo -Loading section .rom_vectors, size 0x40 lma 0x2020000 -Loading section .text, size 0x7fd8 lma 0x2020040 -Loading section .rodata, size 0x15a0 lma 0x2028018 -Loading section .data, size 0x2e4 lma 0x20295b8 -Start address 0x2020040 , load size 39068 -Transfer rate: 6250 bits/sec, 500 bytes/write. -(gdb) c -Continuing. -</programlisting> -At this point, interrupt the Angel session and start minicom. -<programlisting> -RedBoot> <userinput>ve</userinput> - -RedBoot(tm) bootstrap and debug environment [RAM] -Red Hat certified release, version R1.xx - built 14:09:27, Jul 20 2001 - -Platform: Atmel AT91/EB40 (ARM7TDMI) -Copyright (C) 2000, 2001, Red Hat, Inc. - -RAM: 0x02000000-0x02080000, 0x020116d8-0x0207fd00 available -FLASH: 0x01010000 - 0x01020000, 256 blocks of 0x00000100 bytes each. - -RedBoot> <userinput>load -m ymodem -b %{FREEMEMLO}</userinput> -</programlisting> -Use minicom to send the file redboot_ROMRAM.srec via YModem. -<programlisting> -RedBoot> <userinput>fi wr -f 0x01010000 -b %{FREEMEMLO} -l 0xe000</userinput> -</programlisting> -Set switch SW1 to "upper mem", press the "reset" pushbutton and RedBoot -should come up on the board. -</para> -</sect2> -<sect2> -<title>Special RedBoot Commands </title> -<para>None.</para> -</sect2> -<sect2> -<title>Memory Maps </title> -<para>This processor has no MMU, so the only memory map is for physical addresses. + +<para>These shell variables provide the platform-specific information +needed for building RedBoot according to the procedure described in +<xref linkend="Rebuilding-Redboot">: <programlisting> -Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x00000fff On-chip SRAM -0x01000000 - 0x0101ffff Flash -0x02000000 - 0x0207ffff RAM -0xffe00000 - 0xffffffff I/O registers - -The flash based RedBoot image occupies virtual addresses 0x01010000 - 0x0101dfff -</programlisting></para> - -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for PLATFORM_DIR on this platform is -“at91”. -The value for TARGET is “eb40”. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/at91/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used. -The ROMRAM configuration should be used to build the RedBoot image to be -programmed into flash. The RAM configuration is used for the initial download -of RedBoot. -</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="asb2305"> -<title>Matsushita MN103E010 (AM33/2.0) ASB2305 Board</title> -<sect2> -<title>Overview</title> -<para> -<indexterm> -<primary>Matsushita MN103E010 (AM33/2.0) ASB2305 Board</primary> -<secondary>installing and testing</secondary> -</indexterm> -<indexterm> -<primary>installing and testing</primary> -<secondary>Matsushita MN103E010 (AM33/2.0) ASB2305 Board</secondary> -</indexterm> -RedBoot supports the debug serial port and the built in ethernet port for communication and -downloads. The default serial port settings are 115200,8,N,1 with RTS/CTS flow control. RedBoot can -run from either flash, and can support flash management for either the boot PROM or the system -flash regions. These configurations are supported: -<itemizedlist> -<listitem><para>RedBoot running from the boot PROM and able to access the system flash (the -redboot_ROM.bin image should be used for this).</para> -</listitem> -<listitem><para>RedBoot running from the system flash and able to access the boot PROM (the -redboot_FLASH.bin image should be used for this).</para> -</listitem> -<listitem><para>RedBoot running from RAM and able to access the boot PROM (the -redboot_RAM.bin image should be used for this).</para> -</listitem> -</itemizedlist> -</para></sect2> -<sect2> -<title>Initial Installation</title> -<para>Unless a pre-programmed system flash module is available to be plugged into a new board, -RedBoot must be installed with the aid of a JTAG interface unit. To achieve this, the RAM based -RedBoot must be loaded directly into RAM by JTAG and started, and then <emphasis>that</emphasis> -must be used to store the ROM based RedBoot into the boot PROM.</para> -<para>These instructions assume that you have binary images of the RAM-based and boot PROM-based -RedBoot images available.</para> -<sect3> -<title>Preparing to program the board</title> -<para>If the board is to be programmed, whether via JTAG or RedBoot, some hardware settings need to -be changed:</para> -<itemizedlist> -<listitem> -<para>Jumper across ST18 on the board to allow write access to the boot PROM.</para> -</listitem> -<listitem> -<para>Set DIP switch S1-3 to OFF to allow RedBoot to write to the system flash.</para> -</listitem> -<listitem> -<para>Set the switch S5 (on the front of the board) to boot from whichever flash is -<emphasis>not</emphasis> being programmed. Note that the RedBoot image cannot access the flash from -which it is currently executing (it can only access the other flash).</para> -</listitem> -</itemizedlist> -<para> -The RedBoot binary image files should also be copied to the TFTP pickup area on the host providing -TFTP services if that is how RedBoot should pick up the images it is going to program into the -flash. Alternatively, the images can be passed by YMODEM over the serial link. -</para> -</sect3> -<sect3> -<title>Preparing to use the JTAG debugger</title> -<para>The JTAG debugger will also need setting up:</para> -<orderedlist> -<listitem><para>Install the JTAG debugger software (WICE103E) on a PC running Windows (WinNT is -probably the best choice for this) in “C:/PanaX”.</para> -</listitem> -<listitem><para>Install the Matsushita provided “project” into the -“C:/Panax/wice103e/prj” directory.</para> -</listitem> -<listitem><para>Install the RedBoot image files into the “C:/Panax/wice103e/prj” -directory under the names redboot.ram and redboot.prom.</para> -</listitem> -<listitem><para>Make sure the PC's BIOS has the parallel port set to full bidirectional -mode.</para> -</listitem> -<listitem><para>Connect the JTAG debugger to the PC's parallel port.</para> -</listitem> -<listitem><para>Connect the JTAG debugger to the board.</para> -</listitem> -<listitem><para>Set the switch on the front of the board to boot from “boot -PROM”.</para> -</listitem> -<listitem><para>Power up the JTAG debugger and then power up the board.</para> -</listitem> -<listitem><para>Connect the board's Debug Serial port to a computer by a null modem cable.</para> -</listitem> -<listitem><para>Start minicom or some other serial communication software and set for 115200 baud, -1-N-8 with hardware (RTS/CTS) flow control.</para> -</listitem> -</orderedlist> -</sect3> -<sect3> -<title>Loading the RAM-based RedBoot via JTAG</title> -<para>To perform the first half of the operation, the following steps should be followed:</para> -<orderedlist> -<listitem><para>Start the JTAG debugger software.</para> -</listitem> -<listitem> -<para>Run the following commands at the JTAG debugger's prompt to set up the MMU registers on the -CPU.</para> -<programlisting> -ed 0xc0002000, 0x12000580 - -ed 0xd8c00100, 0x8000fe01 -ed 0xd8c00200, 0x21111000 -ed 0xd8c00204, 0x00100200 -ed 0xd8c00208, 0x00000004 - -ed 0xd8c00110, 0x8400fe01 -ed 0xd8c00210, 0x21111000 -ed 0xd8c00214, 0x00100200 -ed 0xd8c00218, 0x00000004 - -ed 0xd8c00120, 0x8600ff81 -ed 0xd8c00220, 0x21111000 -ed 0xd8c00224, 0x00100200 -ed 0xd8c00228, 0x00000004 - -ed 0xd8c00130, 0x8680ff81 -ed 0xd8c00230, 0x21111000 -ed 0xd8c00234, 0x00100200 -ed 0xd8c00238, 0x00000004 - -ed 0xd8c00140, 0x9800f801 -ed 0xd8c00240, 0x00140000 -ed 0xd8c00244, 0x11011100 -ed 0xd8c00248, 0x01000001 - -ed 0xda000000, 0x55561645 -ed 0xda000004, 0x000003c0 -ed 0xda000008, 0x9000fe01 -ed 0xda00000c, 0x9200fe01 -ed 0xda000000, 0xa89b0654 +export TARGET=se7751 +export ARCH_DIR=sh +export PLATFORM_DIR=se7751 </programlisting> -</listitem> -<listitem> -<para>Run the following commands at the JTAG debugger's prompt to tell it what regions of the CPU's -address space it can access:</para> -<programlisting> -ex 0x80000000,0x81ffffff,/mexram -ex 0x84000000,0x85ffffff,/mexram -ex 0x86000000,0x867fffff,/mexram -ex 0x86800000,0x87ffffff,/mexram -ex 0x8c000000,0x8cffffff,/mexram -ex 0x90000000,0x93ffffff,/mexram -</programlisting> -</listitem> -<listitem><para>Instruct the debugger to load the RAM RedBoot image into RAM:</para> -<programlisting> -_pc=90000000 -u_pc -rd redboot.ram,90000000 -</programlisting> -</listitem> -<listitem><para>Load the boot PROM RedBoot into RAM:</para> -<programlisting> -rd redboot.prom,91020000 -</programlisting> -</listitem> -<listitem><para>Start RedBoot in RAM:</para> -<programlisting> -g -</programlisting> -<para>Note that RedBoot may take some time to start up, as it will attempt to query a BOOTP or DHCP -server to try and automatically get an IP address for the board. Note, however, that it should send -a plus over the serial port immediately, and the 7-segment LEDs should display “rh -8”.</para> -</listitem> -</orderedlist> -</sect3> -<sect3> -<title>Loading the boot PROM-based RedBoot via the RAM RedBoot</title> -<para>Once the RAM RedBoot is up and running, it can be communicated with by way of the serial -port. Commands can now be entered directly to RedBoot for flashing the boot PROM.</para> -<orderedlist> -<listitem><para>Instruct RedBoot to initialise the boot PROM:</para> -<programlisting> -fi init -</programlisting> -</listitem> -<listitem><para>Write the previously loaded redboot.prom image into the boot PROM:</para> -<programlisting> -fi write -f 0x80000000 -b 0x91020000 -l 0x00020000 -</programlisting> -</listitem> -<listitem><para>Check that RedBoot has written the image:</para> -<programlisting> -dump -b 0x91020000 -dump -b 0x80000000 -</programlisting> -<para>Barring the difference in address, the two dumps should be the same.</para> -</listitem> -<listitem><para>Close the JTAG software and power-cycle the board. The RedBoot banners should be -displayed again over the serial port, followed by the RedBoot prompt. The boot PROM-based RedBoot -will now be running.</para> -</listitem> -<listitem><para>Power off the board and unjumper ST18 to write-protect the contents of the boot -PROM. Then power the board back up.</para> -</listitem> -<listitem><para>Run the following command to initialise the system flash:</para> -<programlisting> -fi init -</programlisting> -<para>Then program the system flash based RedBoot into the system flash:</para> -<programlisting> -load -r -b 0x91020000 /tftpboot/redboot_FLASH.bin -fi write -f 0x84000000 -b 0x91020000 -l 0x00020000 -</programlisting> -<note> -<title>NOTE</title> -<para>RedBoot arranges the flashes on booting such that they always appear at the same addresses, -no matter which one was booted from.</para> -</note> -</listitem> -<listitem> -<para>A similar sequence of commands can be used to program the boot PROM when RedBoot has been -booted from an image stored in the system flash. -</para> -<programlisting> -load -r -b 0x91020000 /tftpboot/redboot_ROM.bin -fi write -f 0x80000000 -b 0x91020000 -l 0x00020000 -</programlisting> -<para>See <xref linkend="Persistent-State-Flash"> for details on configuring the RedBoot in -general, and also <xref linkend="Flash-Image-System"> for more details on programming the system -flash.</para> -</listitem> -</orderedlist> -</sect3> -</sect2> -<sect2> -<title>Additional Commands</title> -<para>The <command>exec</command> command which allows the loading and execution of -Linux kernels, is supported for this architecture (see <xref linkend="executing-programs">). The -<command>exec</command> parameters used for ASB2305 board are:</para> -<variablelist> -<varlistentry><term> --w <replaceable><time></replaceable></term> -<listitem><para>Wait time in seconds before starting kernel</para></listitem></varlistentry> -<varlistentry><term> --c <replaceable>"params"</replaceable></term> -<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> -<varlistentry><term><replaceable><addr></replaceable></term> -<listitem><para>Kernel entry point, defaulting to the entry point of the last image -loaded</para></listitem></varlistentry> -</variablelist> -<para>The parameter string is stored in the on-chip memory at location 0x8C001000, and is prefixed -by “cmdline:” if it was supplied.</para> -</sect2> -<sect2> -<title>Memory Maps </title> -<para>RedBoot sets up the following memory map on the ASB2305 board.</para> -<note> -<title>NOTE</title> -<para>The regions mapped between 0x80000000-0x9FFFFFFF are cached by the CPU. However, all those -regions can be accessed uncached by adding 0x20000000 to the address.</para> -</note> -<programlisting> -Physical Address Range Description ------------------------ ----------- -0x80000000 - 0x9FFFFFFF Cached Region -0x80000000 - 0x81FFFFFF Boot PROM -0x84000000 - 0x85FFFFFF System Flash -0x86000000 - 0x86007FFF 64Kbit Sys Config EEPROM -0x86F90000 - 0x86F90003 4x 7-segment LEDs -0x86FA0000 - 0x86FA0003 Software DIP Switches -0x86FB0000 - 0x86FB001F PC16550 Debug Serial Port -0x8C000000 - 0x8FFFFFFF On-Chip Memory (repeated 16Kb SRAM) -0x90000000 - 0x93FFFFFF SDRAM -0x98000000 - 0x9BFFFFFF Paged PCI Memory Space (64Mb) -0x9C000000 - 0x9DFFFFFF PCI Local SRAM (32Mb) -0x9E000000 - 0x9E03FFFF PCI I/O Space -0x9E040000 - 0x9E0400FF AM33-PCI Bridge Registers -0x9FFFFFF4 - 0x9FFFFFF7 PCI Memory Page Register -0x9FFFFFF8 - 0x9FFFFFFF PCI Config Registers -0xA0000000 - 0xBFFFFFFF Uncached Mirror Region -0xC0000000 - 0xDFFFFFFF CPU Control Registers -</programlisting> -<para>The ASB2305 HAL makes use of the on-chip memory in the following way:</para> -<programlisting> -0x8C000000 - 0x8C0000FF hal_vsr_table -0x8C000100 - 0x8C0001FF hal_virtual_vector_table -0x8C001000 - Linux command line (RedBoot exec command) - - 0x8C003FFF Emergency DoubleFault Exception Stack -</programlisting> -<para>Currently the CPU's interrupt table lies at the beginning of the RedBoot image, which must -therefore be aligned to a 0xFF000000 mask.</para> -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-RedBoot"> should be followed. The values for -TARGET, ARCH_DIR and PLATFORM_DIR on this platform are “asb2305”, “mn10300” -and “asb2305” respectively. Note that the configuration export files supplied in the -<computeroutput> hal/mn10300/asb2305/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used.</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="aaed2000"> -<title>Agilent AAED2000 ARM9 (aaed) </title> -<sect2> -<title>Overview</title> -<para><indexterm><primary>Agilent AAED2000 ARM9 (aaed)</primary> -<secondary>installing and testing</secondary></indexterm><indexterm><primary> -installing and testing</primary><secondary>Agilent AAED2000 ARM9 (aaed) -</secondary></indexterm>RedBoot supports the serial and ethernet ports -on the board. The default serial port settings are 38400,8,N,1. -RedBoot also supports flash management on the AAED2000. -Two basic RedBoot configurations are supported: <itemizedlist> -<listitem><para>RedBoot being automatically executed by the on-board -ARM Boot Monitor, running from RAM.</para> -</listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector. </para> -</listitem> -</itemizedlist></para> - -</sect2> - -<sect2> -<title>Initial Installation Method </title> -<para>It is possible to install RedBoot in one of two ways. Either as -the primary bootmonitor on the board (installed to blocks 0-1 of the -flash) or as the secondary bootmonitor on the board (installed to -blocks 1-2 of the flash).</para> - -<para>Presently, only the former method is supported.</para> -<!-- Nuke the above line if uncommenting this block -<para>When installed as the secondary bootmonitor, the ARM bootmonitor -remains in flash and auto-executes RedBoot (but only when RedBoot is -smaller than 128KB - which means it cannot include the LCD driver). -It is of crucial importance that no RedBoot configured to be -primary bootmonitor is executed on a board where RedBoot is actually -supposed to be the secondary bootmonitor since it may cause corruption -of the flash. Installing RedBoot as the primary booter is -adviced.</para> ---> - -<sect3><title>RedBoot as Primary Bootmonitor</title> - -<para>RedBoot is installed in flash using the on-board ARM Boot -Monitor.</para> -<para>Boot the board while pressing SPACE. This should bring up the -Boot Monitor: -<programlisting>ARM bootPROM [Version 1.3] Rebuilt on Jul 16 2001 at 16:21:36 -Running on a P920 board Evaluation Board -Board Revision V1.0, ARM920T processor Processor -Memory Size is 32MBytes, Flash Size is 32MBytes -Copyright (c) ARM Limited 1999 - 2001. All rights reserved. -Board designed by ARM Limited -Hardware support provided at http://www.arm.com/ -For help on the available commands type ? or h -boot Monitor > -</programlisting> - -Download the RAM startup version of RedBoot configured as a primary -bootmonitor using the ARM bootmonitor's SREC-download command: - -<programlisting>boot Monitor > <userinput>m</userinput> -Load Motorola S-Record image into memory and execute it -The S-Record loader only accepts input on the serial port. -Record addresses must be between 0x00008000 and 0x01E0F510. -Type Ctrl/C to exit loader. -</programlisting> - -Use the terminal emulator's ASCII upload command, or (on Linux) simply -cat the file to the serial port: - -<programlisting>$ <userinput>cat redboot_primary_RAM/redboot.srec >/dev/ttyS1</userinput> -</programlisting> - -You should see RedBoot start up: - -<programlisting>FLASH configuration checksum error or invalid key -Ethernet eth0: MAC address 00:30:d3:03:04:99 -IP: 192.168.42.111, Default server: 192.168.42.3 - -RedBoot(tm) bootstrap and debug environment [RAM] -Non-certified release, version UNKNOWN - built 13:15:40, Nov 9 2001 - -Platform: AAED2000 system (ARM9) [Primary] -Copyright (C) 2000, 2001, Red Hat, Inc. - -RAM: 0x00000000-0x01f80000, 0x0006f208-0x01f51000 available -FLASH: 0x60000000 - 0x62000000, 256 blocks of 0x00020000 bytes each. -RedBoot></programlisting> - -As can be seen from the output above, the network has been configured -to give the board an IP address and information about the default -server. If things are not set up on your network, you can still -continue, but use the Y-modem download method when loading the RedBoot -ROMRAM image. - -Now initialize RedBoot's FIS: - -<programlisting>RedBoot> <userinput>fi init</userinput> -About to initialize [format] FLASH image system - continue (y/n)? <userinput>y</userinput> -*** Initialize FLASH Image System - Warning: device contents not erased, some blocks may not be usable -... Erase from 0x61fe0000-0x62000000: . -... Program from 0x01f5f000-0x01f5f300 at 0x61fe0000: . -</programlisting> - -Download the ROMRAM version of RedBoot via ethernet: - -<programlisting>RedBoot> <userinput>load -b 0x100000 redboot_primary_ROMRAM/redboot.srec</userinput> -</programlisting> - -or using serial Y-modem protocol: - -<programlisting>RedBoot> <userinput>load -mode ymodem -b 0x100000</userinput> -</programlisting> - -(Use the terminal emulator's Y-modem upload command to send the file -<filename>redboot_primary_ROMRAM/redboot.srec</filename>.) - -When the image has been downloaded, program it into flash: - -<programlisting>Address offset = 0x00ff8000 -Entry point: 0x00008040, address range: 0x00008000-0x0002da80 -RedBoot> <userinput>fi cr RedBoot -b 0x100000</userinput> -An image named 'RedBoot' exists - continue (y/n)? <userinput>y</userinput> -* CAUTION * about to program 'RedBoot' - at 0x60000000..0x6003ffff from 0x00100000 - continue (y/n)? <userinput>y</userinput> -... Erase from 0x60000000-0x60040000: .. -... Program from 0x00100000-0x00140000 at 0x60000000: .. -... Erase from 0x61fe0000-0x62000000: . -... Program from 0x01f5f000-0x01f7f000 at 0x61fe0000: . -</programlisting> - -Now reset the board. You should see the RedBoot banner.</para> - -</sect3> - -<!-- -<sect3><title>RedBoot as Secondary Bootmonitor</title> - -<para>RedBoot is installed in flash using the on-board ARM Boot -Monitor.</para> -<para>Boot the board while pressing SPACE. This should bring up the -Boot Monitor: -<programlisting>ARM bootPROM [Version 1.3] Rebuilt on Jul 16 2001 at 16:21:36 -Running on a P920 board Evaluation Board -Board Revision V1.0, ARM920T processor Processor -Memory Size is 32MBytes, Flash Size is 32MBytes -Copyright (c) ARM Limited 1999 - 2001. All rights reserved. -Board designed by ARM Limited -Hardware support provided at http://www.arm.com/ -For help on the available commands type ? or h -boot Monitor > -</programlisting> - -Download the RAM startup version of RedBoot configured as a secondary -bootmonitor using the ARM bootmonitor's SREC-download command: - -<programlisting>boot Monitor > <userinput>m</userinput> -Load Motorola S-Record image into memory and execute it -The S-Record loader only accepts input on the serial port. -Record addresses must be between 0x00008000 and 0x01E0F510. -Type Ctrl/C to exit loader. -</programlisting> - -Use the terminal emulator's ASCII upload command, or (on Linux) simply -cat the file to the serial port: - -<programlisting>$ <userinput>cat redboot_secondary_RAM.srec >/dev/ttyS1</userinput> -</programlisting> - -You should see RedBoot start up: - -<programlisting>FLASH configuration checksum error or invalid key -Ethernet eth0: MAC address 00:30:d3:03:04:99 -IP: 192.168.42.111, Default server: 192.168.42.3 - -RedBoot(tm) bootstrap and debug environment [RAM] -Non-certified release, version UNKNOWN - built 12:31:13, Nov 9 2001 - -Platform: AAED2000 system (ARM9) [Secondary] -Copyright (C) 2000, 2001, Red Hat, Inc. - -RAM: 0x00000000-0x01f80000, 0x00063568-0x01f51000 available -FLASH: 0x60000000 - 0x62000000, 256 blocks of 0x00020000 bytes each. -</programlisting> - -As can be seen from the output above, the network has been configured -to give the board an IP address and information about the default -server. If things are not set up on your network, you can still -continue, but use the Y-modem download method when loading the RedBoot -ROMRAM image. - -Next step is to erase all of the flash, except where the ARM booter resides: - -<programlisting>RedBoot> <userinput>fi erase -f 0x60020000 -l 0x01fe0000</userinput> -... Erase from 0x60020000-0x62000000: .......................................... -................................................................................ -................................................................................ -..................................................... -</programlisting> - -Then initialize RedBoot's FIS: - -<programlisting>RedBoot> <userinput>fi init</userinput> -About to initialize [format] FLASH image system - continue (y/n)? <userinput>y</userinput> -*** Initialize FLASH Image System - Warning: device contents not erased, some blocks may not be usable -... Erase from 0x61fc0000-0x61fe0000: . -... Program from 0x01fdf000-0x01fff000 at 0x61fc0000: . -</programlisting> - -Download the ROMRAM version of RedBoot via ethernet: - -<programlisting>RedBoot> <userinput>load -raw -b 0x100000 redboot_secondary_ROMRAM.arm.bin</userinput> -</programlisting> - -or using serial Y-modem protocol: - -<programlisting>RedBoot> <userinput>load -raw -mode ymodem -b 0x100000</userinput> -</programlisting> - -(Use the terminal emulator's Y-modem upload command to send the file -<filename>redboot_secondary_ROMRAM.arm.bin</filename>.) - -When the image has been downloaded, program it into flash: - -<programlisting>RedBoot> <userinput>fi cr RedBoot -b 0x100000</userinput> -An image named 'RedBoot' exists - continue (y/n)? <userinput>y</userinput> -* CAUTION * about to program 'RedBoot' - at 0x60020000..0x6005ffff from 0x00100000 - continue (y/n)? <userinput>y</userinput> -... Erase from 0x60020000-0x60060000: .. -... Program from 0x00100000-0x00140000 at 0x60020000: .. -... Erase from 0x61fc0000-0x61fe0000: . -... Program from 0x01f5f000-0x01f7f000 at 0x61fc0000: . -</programlisting> - -Now reset the board. You might see the ARM Monitor complain: - -<programlisting>Failed to boot from flash. -The ARM Boot Monitor SIB can not be found. -Press any key to continue. -</programlisting> - -This is due to due to the flash having been erased. Press a key, and -execute the "validate flash contents" command: - -<programlisting>boot Monitor > <userinput>v</userinput> - -There are 254 128KByte blocks of Application Flash: - -No images found! -================ - -System Information Blocks -========================= -Address Owner Size Idx Rev -~~~~~~~ ~~~~~ ~~~~ ~~~ ~~~ -0x05FE0000 ARM Boot Monitor 312 0 0 - - -Blocks of unknown type -====================== -Block Size Footer Type -~~~~~ ~~~~ ~~~~~~~~~~~ - 252 1 0x52420000 -boot Monitor > -</programlisting> - -This causes the last block of the flash to be initialized with the ARM -Boot Monitor ID, necessary for the Monitor to work properly. When -resetting the board now, it should automatically start RedBoot. If you -ever need to get into the ARM Boot Monitor again, reset the board -while pressing the SPACE key. - -</para></sect3> ---> - + +<para>The names of configuration files are listed above with the +description of the associated modes.</para> </sect2> - -<sect2> -<title>Special RedBoot Commands </title> -<para>The <command>exec</command> command which allows the loading -and execution of Linux kernels, -is supported for this board (see <xref linkend="executing-programs">). The <command> -exec</command> parameters used for the AAED2000 are:</para> -<variablelist><varlistentry> -<term>-b <replaceable><addr></replaceable></term> -<listitem><para>Location Linux kernel was loaded to</para></listitem></varlistentry> -<varlistentry><term> --l <replaceable><len></replaceable></term> -<listitem><para>Length of kernel</para></listitem></varlistentry> -<varlistentry><term> --c <replaceable>"params"</replaceable></term> -<listitem><para>Parameters passed to kernel</para></listitem></varlistentry> -<varlistentry><term>-r <replaceable><addr></replaceable></term> -<listitem><para>'initrd' ramdisk location</para></listitem></varlistentry> -<varlistentry><term>-s <replaceable><len></replaceable></term> -<listitem><para>Length of initrd ramdisk</para></listitem></varlistentry> -</variablelist> - -<para>The parameters for kernel image base and size are automatically -set after a load operation. So one way of starting the kernel would -be: - -<programlisting>RedBoot> load -r -b 0x100000 zImage -Raw file loaded 0x00100000-0x001a3d6c -RedBoot> exec -c "console=ttyAC0,38400" -Using base address 0x00100000 and length 0x000a3d6c -Uncompressing Linux..... -</programlisting> - -An image could also be put in flash and started directly: - -<programlisting>RedBoot> exec -b 0x60040000 -l 0xc0000 -c "console=ttyAC0,38400" -Uncompressing Linux..... -</programlisting> - -</para> - -</sect2> -<sect2> -<title>Memory Maps </title> -<para>The MMU page tables are located at 0x4000. <note><title>NOTE -</title> -<para>The virtual memory maps in this section use a C and B column to indicate -whether or not the region is cached (C) or buffered (B).</para> -</note><programlisting>Physical Address Range Description ------------------------ ---------------------------------- -0x00000000 - 0x01ffffff Flash -0x10000000 - 0x100fffff Ethernet -0x30000000 - 0x300fffff Board registers -0x40000000 - 0x4fffffff PCMCIA Slot (0) -0x50000000 - 0x5fffffff Compact Flash Slot (1) -0x80000000 - 0x800037ff I/O registers -0xb0060000 - 0xb00fffff On-chip SRAM -0xf0000000 - 0xfd3fffff SDRAM - -Virtual Address Range C B Description ------------------------ - - ---------------------------------- -0x00000000 - 0x01f7ffff Y Y SDRAM -0x01f80000 - 0x01ffffff Y Y SDRAM (used for LCD frame buffer) -0x10000000 - 0x100fffff N N Ethernet -0x30000000 - 0x300fffff N N Board registers -0x40000000 - 0x4fffffff N N PCMCIA Slot (0) -0x50000000 - 0x5fffffff N N Compact Flash Slot (1) -0x60000000 - 0x61ffffff N N Flash -0x80000000 - 0x800037ff N N I/O registers -0xf0000000 - 0xffffffff N N SDRAM (uncached) - -</programlisting></para> - -</sect2> -<sect2> -<title>Rebuilding RedBoot</title> -<para>The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. -The values for ARCH_DIR and PLATFORM_DIR on this platform are -“arm” and “arm9/aaed2000” respectively. -The value for TARGET is “aaed”. -Note that the configuration export files supplied in the <computeroutput> -hal/arm/arm9/aaed2000/<replaceable>VERSION</replaceable>/misc</computeroutput> -directory in the RedBoot source tree should be used. -</para> -</sect2> -</sect1> -<?Pub _newpage> -<sect1 id="vrc4375"> -<title>NEC DDB-VRC4375</title> -<sect2> -<title>Overview</title> - -<para><indexterm><primary>NEC DDB-VRC4375</primary> -<secondary>installing and testing</secondary></indexterm><indexterm><primary> -installing and testing</primary><secondary>NEC DDB-VRC4375 -</secondary></indexterm>RedBoot supports only serial port 1, which is connected to the upper -of the stacked serial connectors on the board. The default serial -port settings are 38400,8,N,1. FLASH management is also supported. Two -basic RedBoot configurations are supported: - -<itemizedlist> -<listitem><para>RedBoot running from RAM which has been relocated from the board's -flash boot sector.</para></listitem> -<listitem><para>RedBoot running from RAM with RedBoot in the flash boot sector.</para></listitem> -</itemizedlist></para> - -<para>Since the normal RedBoot configuration does not use the FLASH ROM -except during startup, it is unnecessary to load a RAM-based RedBoot -before reprogramming the FLASH.</para> - -</sect2> - -<sect2> -<title>Initial Installation Method </title> - -<para>A device programmer should be used to program a socketed FLASH part -(AMD 29F040). The board as delivered is configured for a 512K -EPROM. To install a FLASH ROM, Jumpers J30, J31 and J36 need to be -changed as described in the board's User Manual.</para> -</sect2> - -<sect2> -<title>Special RedBoot Commands</title> - -<para>None.</para> -</sect2> - -<sect2> -<title>Memory Maps</title> - -<para>RedBoot sets up the memory map primarily as described in the board's -User Manual. There are some minor differences, noted in the following -table: -<screen> -Physical Virtual Resource -Addresses Addresses -00000000-01FFFFFF 80000000-81FFFFFF Base SDRAM (cached) -00000000-01FFFFFF A0000000-A1FFFFFF Base SDRAM (uncached) -0C000000-0C0BFFFF AC000000-AC0B0000 PCI IO space -0F000000-0F0001FF AF000000-AF0001FF VRC4375 Registers -1C000000-1C0FFFFF BC000000-BC0FFFFF VRC4372 Registers -1C100000-1DFFFFFF BC100000-BDFFFFFF PCI Memory space -1FC00000-1FC7FFFF BFC00000-BFC7FFFF FLASH ROM -80000000-8000000D C0000000-C000000D RTC -8000000E-80007FFF C000000E-C0007FFF NVRAM -81000000-81FFFFFF C1000000-C1FFFFFF Z85C30 DUART -82000000-82FFFFFF C2000000-C2FFFFFF Z8536 Timer -83000000-83FFFFFF C3000000-C3FFFFFF 8255 Parallel port -87000000-87FFFFFF C7000000-C7FFFFFF Seven segment display</screen> -</para> - -<note> <title>NOTE</title> -<para> -By default the VRC4375 SIMM control registers are not programmed -since the values used must depend on the SIMMs installed. If SIMMs -are to be used, correct values must be placed in these registers -before accessing the SIMM address range. -</para> -</note> - -<note> <title>NOTE</title> -<para> -The allocation of address ranges to devices in the PCI IO and -memory spaces is handled by the eCos PCI support library. They do -not correspond to those described in the board User Manual. -</para> -</note> - -<note> <title>NOTE</title> -<para> -The MMU has been set up to relocate the VRC4372 supported devices -mapped at physical addresses 0x8xxxxxxx to virtual addresses -0xCxxxxxxx. -</para> -</note> - -</sect2> - -<sect2> -<title>Ethernet Driver</title> - -<para> -The ethernet driver is in two parts: -</para> - -<para> -A generic ether driver for the Intel i21143 device is located in -<computeroutput>devs/eth/intel/i21143</computeroutput>. Its package name is <computeroutput>CYGPKG_DEVS_ETH_INTEL_I21143</computeroutput>. -</para> - -<para> -The platform-specific ether driver is <computeroutput>devs/eth/mips/vrc4375</computeroutput>. Its package is -<computeroutput>CYGPKG_DEVS_ETH_MIPS_VRC4375</computeroutput>. This tells the generic driver the address in -IO memory of the chip, for example, and other configuration details. The -ESA (MAC address) is by default collected from on-board serial EEPROM, -unless configured statically within this package. -</para> -</sect2> - -<sect2> -<title>Rebuilding RedBoot</title> - -<para> -The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. The values for -TARGET, ARCH_DIR and PLATFORM_DIR on this platform are “vrc4375”, -“mips” and “vrc4375” respectively. The configuration export files -supplied in the <computeroutput>hal/mips/vrc4375/<replaceable>VERSION</replaceable>/misc</computeroutput> directory in the RedBoot -source tree should be used. In general only the ROMRAM variant should -need to be used. -</para> -</sect2> - -</sect1> -<?Pub _newpage> -<sect1 id="frv400"> -<title>Fujitsu FR-V 400 (MB-93091)</title> -<sect2> -<title>Overview</title> - -<para><indexterm><primary>Fujitsu FR-V 400</primary> -<secondary>installing and testing</secondary></indexterm><indexterm><primary> -installing and testing -</primary><secondary>Fujitsu FR-V 400</secondary></indexterm> -RedBoot supports both serial ports, which are available via -the stacked serial connectors on the mother board. -The topmost port is the default and is considered to be port 0 by RedBoot. -The bottommost port is serial port 1. -The default serial port settings are 38400,8,N,1. -</para> -<para> -FLASH management is also supported, but only for the FLASH device in IC7. -This arrangement allows for IC8 to retain either the original Fujitsu board -firmware, or some application specific contents. -Two basic RedBoot configurations are supported: - -<itemizedlist> - <listitem> - <para> - RedBoot running from RAM which has been relocated from the board's - flash boot sector. This mode is known as ROMRAM. - </para> - </listitem> - <listitem> - <para> - RedBoot running from RAM, loaded by some other means. - </para> - </listitem> -</itemizedlist> - -</para> - -<para>Since the normal RedBoot configuration does not use the FLASH ROM -except during startup, it is unnecessary to load a RAM-based RedBoot -before reprogramming the FLASH.</para> - -</sect2> - -<sect2> -<title>Initial Installation Method </title> - -<para> -RedBoot can be installed by directly programming the FLASH device in IC7 -or by using the Fujitsu provided software to download and install a -version into the FLASH device. Complete instructions are provided -separately. -</para> - -</sect2> - -<sect2> -<title>Special RedBoot Commands</title> - -<para>None.</para> -</sect2> - -<sect2> -<title>Memory Maps</title> - -<para>The memory map of this platform is fixed by the hardware (cannot -be changed by software). The only attributes which can be modified are -control over cacheability, as noted below. -<screen> -Address Cache? Resource -00000000-03EFFFFF Yes SDRAM (via plugin DIMM) -03F00000-03FFFFFF No SDRAM (used for PCI window) -10000000-1FFFFFFF No MB86943 PCI bridge -20000000-201FFFFF No SRAM -21000000-23FFFFFF No Motherboard resources -24000000-25FFFFFF No PCI I/O space -26000000-2FFFFFFF No PCI Memory space -30000000-FDFFFFFF ?? Unused -FE000000-FEFFFFFF No I/O devices -FF000000-FF1FFFFF No IC7 - RedBoot FLASH -FF200000-FF3FFFFF No IC8 - unused FLASH -FF400000-FFFFFFFF No Misc other I/O -</screen> -</para> - -<note> <title>NOTE</title> -<para> -The only configuration currently suppored requires a 64MB SDRAM -DIMM to be present on the CPU card. No other memory configuration -is supported at this time. -</para> -</note> - -</sect2> - -<sect2> -<title>Rebuilding RedBoot</title> - -<para> -The instructions in <xref linkend="Rebuilding-Redboot"> should be followed. The values for -TARGET, ARCH_DIR and PLATFORM_DIR on this platform are “frv400”, -“frv” and “frv400” respectively. The configuration export files -supplied in the <computeroutput>hal/frv/frv400/<replaceable>VERSION</replaceable>/misc</computeroutput> directory in the RedBoot -source tree should be used. In general only the ROMRAM variant should -need to be used. -</para> -</sect2> - </sect1> </chapter>
--- a/packages/redboot/current/doc/redboot_rebuilding.sgml +++ b/packages/redboot/current/doc/redboot_rebuilding.sgml @@ -81,13 +81,14 @@ chosen platform. <para>Then import the appropriate platform RedBoot configuration file, here for RAM configuration: <screen> -$ <userinput>ecosconfig import <filename>${ECOS_REPOSITORY}/hal/sh/se7751/current/misc/redboot_RAM.ecm</filename></userinput> +$ <userinput>ecosconfig import <filename>${ECOS_REPOSITORY}/hal/sh/se7751/<replaceable>VERSION</replaceable>/misc/redboot_RAM.ecm</filename></userinput> $ <userinput>ecosconfig tree</userinput> </screen> Replace architecture ("sh"), platform ("se7751") and version -("current") with those appropriate for the chosen platform and the -version number of its HAL package. Also replace the configuration name -("redboot_RAM.ecm") with that of the appropriate configuration file. +("<replaceable>VERSION</replaceable>") with those appropriate for the +chosen platform and the version number of its HAL package. Also +replace the configuration name ("redboot_RAM.ecm") with that of the +appropriate configuration file. </para> <para>RedBoot can now be built: @@ -105,7 +106,7 @@ details are described in the form of she the steps to build RedBoot are: <programlisting> export REDBOOT_CFG=redboot_ROM -export VERSION=current +export VERSION=<replaceable>VERSION</replaceable> mkdir /tmp/${REDBOOT_CFG} cd /tmp/${REDBOOT_CFG} ecosconfig new ${TARGET} redboot @@ -125,26 +126,26 @@ version of the platform package. <title>Rebuilding RedBoot from the <application>Configuration Tool</application></title> <para>To rebuild RedBoot from the <application>Configuration -Tool</application>, open the template window (Build->Templates) and +Tool</application>, open the template window (<guimenuitem>Build->Templates</guimenuitem>) and select the appropriate Hardware target and in Packages select "redboot". Then press OK. Depending on the platform, a number of conflicts may need to be resolved before the build can be started; select "Continue".</para> <para>Import the desired RedBoot configuration file from the platform HAL -(File->Import...). Depending on the platform, a number of +(<guimenuitem>File->Import...</guimenuitem>). Depending on the platform, a number of conflicts may need to be resolved before the build can be started; select "Continue". For example, if the platform selected is Hitachi SE7751 board and the RAM configuration RedBoot should be built, import the file -<filename>hal/sh/se7751/current/misc/redboot_RAM.ecm</filename>.</para> +<filename>hal/sh/se7751/<replaceable>VERSION</replaceable>/misc/redboot_RAM.ecm</filename>.</para> <para>Save the configuration somewhere suitable with enough disk space -for building RedBoot (File->Save...). Choose the name according to +for building RedBoot (<guimenuitem>File->Save...</guimenuitem>). Choose the name according to the RedBoot configuration, for example <filename>redboot_RAM.ecc</filename>.</para> -<para>Then start the build (Build->Library) and wait for it to +<para>Then start the build (<guimenuitem>Build->Library</guimenuitem>) and wait for it to complete. The resulting RedBoot files will be in the associated install directory, for the example this would be <filename class="directory">redboot_RAM_install/bin</filename>.</para>
--- a/packages/redboot/current/src/load.c +++ b/packages/redboot/current/src/load.c @@ -134,7 +134,6 @@ load_elf_image(getc_t getc, terminate_t unsigned long offset = 0; int phx, len, ch; unsigned char *addr; - bool first_addr = true; unsigned long addr_offset = 0; unsigned long highest_address = 0; unsigned long lowest_address = 0xFFFFFFFF; @@ -179,35 +178,43 @@ load_elf_image(getc_t getc, terminate_t #endif offset += sizeof(phdr[0]); } + if (base) { + // Set address offset based on lowest address in file. + addr_offset = 0xFFFFFFFF; + for (phx = 0; phx < ehdr.e_phnum; phx++) { + if (phdr[phx].p_vaddr < addr_offset) { + addr_offset = phdr[phx].p_vaddr; + } + } + addr_offset = (unsigned long)base - addr_offset; + } else { + addr_offset = 0; + } for (phx = 0; phx < ehdr.e_phnum; phx++) { - if ((phdr[phx].p_type == PT_LOAD) && (phdr[phx].p_offset != 0)) { + if (phdr[phx].p_type == PT_LOAD) { // Loadable segment + addr = (unsigned char *)phdr[phx].p_vaddr; + len = phdr[phx].p_filesz; + if ((unsigned long)addr < lowest_address) { + lowest_address = (unsigned long)addr; + } + addr += addr_offset; if (offset > phdr[phx].p_offset) { - diag_printf("Can't load ELF file - program headers out of order\n"); - return 0; - } - while (offset < phdr[phx].p_offset) { - if ((*getc)() < 0) { - diag_printf(SHORT_DATA); + if ((phdr[phx].p_offset + len) < offset) { + diag_printf("Can't load ELF file - program headers out of order\n"); return 0; } - offset++; + addr += offset - phdr[phx].p_offset; + } else { + while (offset < phdr[phx].p_offset) { + if ((*getc)() < 0) { + diag_printf(SHORT_DATA); + return 0; + } + offset++; + } } // Copy data into memory - addr = (unsigned char *)phdr[phx].p_paddr; - len = phdr[phx].p_filesz; - if (first_addr) { - if (base) { - addr_offset = (unsigned long)base - (unsigned long)addr; - } else { - addr_offset = 0; - } - first_addr = false; - } - addr += addr_offset; - if ((unsigned long)(addr-addr_offset) < lowest_address) { - lowest_address = (unsigned long)(addr - addr_offset); - } while (len-- > 0) { #ifdef CYGSEM_REDBOOT_VALIDATE_USER_RAM_LOADS if ((addr < user_ram_start) || (addr > user_ram_end)) {