Mercurial > flash_v2
changeset 860:8e23fe1ac05e
Improve processor type support. Add baud rate generator allocation.
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--- a/packages/hal/powerpc/adder/current/ChangeLog +++ b/packages/hal/powerpc/adder/current/ChangeLog @@ -1,3 +1,7 @@ +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * cdl/hal_powerpc_adder.cdl: New option for setting processor type. + 2003-03-20 Gary Thomas <gary@mlbassoc.com> * src/hal_aux.c (hal_platform_init): Fix SCC2/SCC3 routing.
--- a/packages/hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl +++ b/packages/hal/powerpc/adder/current/cdl/hal_powerpc_adder.cdl @@ -9,7 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## Copyright (C) 2002 Gary Thomas +## Copyright (C) 2002, 2003 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -68,6 +68,8 @@ cdl_package CYGPKG_HAL_POWERPC_ADDER { implements CYGNUM_HAL_QUICC_SMC2 implements CYGNUM_HAL_QUICC_SCC3 + requires { CYGHWR_HAL_POWERPC_MPC8XX == "850" } + define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_adder.h>"
--- a/packages/hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm +++ b/packages/hal/powerpc/adder/current/misc/redboot_ROMRAM.ecm @@ -19,6 +19,7 @@ cdl_configuration eCos { package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; package -hardware CYGPKG_DEVS_ETH_POWERPC_QUICC current ; package -hardware CYGPKG_DEVS_ETH_POWERPC_ADDER current ; + package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC current ; package -template CYGPKG_HAL current ; package -template CYGPKG_INFRA current ; package -template CYGPKG_REDBOOT current ; @@ -54,6 +55,10 @@ cdl_option CYGSEM_HAL_ROM_MONITOR { inferred_value 1 }; +cdl_component CYGHWR_HAL_POWERPC_MPC8XX { + inferred_value 850 +}; + cdl_component CYG_HAL_STARTUP { user_value ROMRAM };
--- a/packages/hal/powerpc/cogent/current/ChangeLog +++ b/packages/hal/powerpc/cogent/current/ChangeLog @@ -1,3 +1,7 @@ +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * cdl/hal_powerpc_cogent.cdl: New options for setting processor type. + 2003-03-07 Gary Thomas <gary@mlbassoc.com> * include/plf_stub.h: Remove [confusing] platform specific include.
--- a/packages/hal/powerpc/cogent/current/cdl/hal_powerpc_cogent.cdl +++ b/packages/hal/powerpc/cogent/current/cdl/hal_powerpc_cogent.cdl @@ -9,6 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -65,6 +66,8 @@ cdl_package CYGPKG_HAL_POWERPC_COGENT { implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + requires { CYGHWR_HAL_POWERPC_MPC8XX == "823" } + define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_cogent.h>"
--- a/packages/hal/powerpc/mbx/current/ChangeLog +++ b/packages/hal/powerpc/mbx/current/ChangeLog @@ -1,3 +1,7 @@ +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * cdl/hal_powerpc_mbx.cdl: New option for setting processor type. + 2003-03-11 Mark Salter <msalter@redhat.com> * src/redboot_linux_exec.c (do_exec): Call eth_drv_stop as necessary.
--- a/packages/hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl +++ b/packages/hal/powerpc/mbx/current/cdl/hal_powerpc_mbx.cdl @@ -9,7 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## Copyright (C) 2002 Gary Thomas +## Copyright (C) 2002, 2003 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -67,6 +67,8 @@ cdl_package CYGPKG_HAL_POWERPC_MBX { implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT implements CYGNUM_HAL_QUICC_SMC1 + requires { CYGHWR_HAL_POWERPC_MPC8XX == "860" } + define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_mbx.h>"
--- a/packages/hal/powerpc/mpc8xx/current/ChangeLog +++ b/packages/hal/powerpc/mpc8xx/current/ChangeLog @@ -1,3 +1,14 @@ +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * src/var_intr.c: + * include/var_intr.h: Clean up for new CDL (processor type) layout. + + * src/var_misc.c: + * include/var_cache.h: Better processor/variant support. + + * cdl/hal_powerpc_mpc8xx.cdl: Rearrange options to handle processor + type more flexibly. + 2003-03-06 Gary Thomas <gary@mlbassoc.com> * src/var_misc.c: Can only reset CPM if not relying on a ROM monitor.
--- a/packages/hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl +++ b/packages/hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl @@ -9,7 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## Copyright (C) 2002 Gary Thomas +## Copyright (C) 2002, 2003 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -102,33 +102,15 @@ cdl_package CYGPKG_HAL_POWERPC_MPC8xx { puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 250000" } - cdl_component CYGPKG_HAL_POWERPC_MPC823 { - display "PowerPC 823 microprocessor" - implements CYGINT_HAL_POWERPC_VARIANT - description " - The PowerPC 823 microprocessor. This is an embedded part that in - addition to the PowerPC processor core has built in peripherals - such as memory controllers, DMA controllers, serial ports and - timers/counters." - } - - cdl_component CYGPKG_HAL_POWERPC_MPC850 { - display "PowerPC 850 microprocessor" + cdl_component CYGHWR_HAL_POWERPC_MPC8XX { + display "PowerPC 8xx microprocessor family" + flavor data + legal_values { "823" "850" "852T" "855T" "860" "860T" "862T" "862P" } + default_value "860" implements CYGINT_HAL_POWERPC_VARIANT description " - The PowerPC 850 microprocessor. This is an embedded part that in - addition to the PowerPC processor core has built in peripherals - such as memory controllers, DMA controllers, serial ports and - timers/counters." - } - - cdl_component CYGPKG_HAL_POWERPC_MPC860 { - display "PowerPC 860 microprocessor" - default_value 1 - implements CYGINT_HAL_POWERPC_VARIANT - description " - The PowerPC 860 microprocessor. This is an embedded part that in - addition to the PowerPC processor core has built in peripherals + The PowerPC 8xx microprocessor family. These are embedded parts + that in addition to the PowerPC processor core have built in peripherals such as memory controllers, DMA controllers, serial ports and timers/counters."
--- a/packages/hal/powerpc/mpc8xx/current/include/var_cache.h +++ b/packages/hal/powerpc/mpc8xx/current/include/var_cache.h @@ -11,6 +11,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -67,7 +68,23 @@ //----------------------------------------------------------------------------- // Cache dimensions - these vary between the 8xx sub-models -#if defined(CYGPKG_HAL_POWERPC_MPC860) +#if defined(CYGHWR_HAL_POWERPC_MPC8XX_862P) +// Data cache +#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache +#endif // defined(CYGHWR_HAL_POWERPC_MPC862P) + +#if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) // Data cache #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line @@ -77,9 +94,10 @@ #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line #define HAL_ICACHE_WAYS 2 // Associativity of the cache -#endif // defined(CYGPKG_HAL_POWERPC_MPC860) +#endif // defined(CYGHWR_HAL_POWERPC_MPC860) -#if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) +#if defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_850) // Data cache #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line @@ -89,7 +107,11 @@ #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line #define HAL_ICACHE_WAYS 2 // Associativity of the cache -#endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) +#endif // defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850) + +#ifndef HAL_ICACHE_SIZE +#error Missing cache definitions for this processor? +#endif #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
--- a/packages/hal/powerpc/mpc8xx/current/include/var_intr.h +++ b/packages/hal/powerpc/mpc8xx/current/include/var_intr.h @@ -11,6 +11,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -43,7 +44,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): nickg -// Contributors:nickg, jskov, jlarmour, hmt +// Contributors:nickg, jskov, jlarmour, hmt, gthomas // Date: 2000-04-02 // Purpose: Variant interrupt support // Description: The macros defined here provide the HAL APIs for handling @@ -96,7 +97,7 @@ #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0 #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGHWR_HAL_POWERPC_MPC8XX // The MPC860 does not generate DSI and ISI: instead it goes to machine // check, so that a software VM system can then call into vectors 0x300 or // 0x400 if the address is truly invalid rather than merely not in the TLB @@ -223,7 +224,7 @@ #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGHWR_HAL_POWERPC_MPC8XX static __inline__ void cyg_hal_interrupt_mask ( cyg_uint32 vector ) @@ -681,7 +682,7 @@ cyg_hal_interrupt_set_level ( cyg_uint32 //-------------------------------------------------------------------------- // Interrupt arbiters -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGHWR_HAL_POWERPC_MPC8XX externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector, CYG_ADDRWORD data); @@ -692,7 +693,7 @@ externC cyg_uint32 hal_arbitration_isr_r externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector, CYG_ADDRWORD data); -#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 +#endif // ifdef CYGHWR_HAL_POWERPC_MPC8XX //----------------------------------------------------------------------------- // Symbols used by assembly code
--- a/packages/hal/powerpc/mpc8xx/current/src/var_intr.c +++ b/packages/hal/powerpc/mpc8xx/current/src/var_intr.c @@ -9,6 +9,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -41,7 +42,7 @@ //#####DESCRIPTIONBEGIN#### // // Author(s): jskov -// Contributors: jskov +// Contributors: jskov, gthomas // Date: 2000-02-11 // Purpose: PowerPC variant interrupt handlers // Description: This file contains code to handle interrupt related issues @@ -56,7 +57,6 @@ #include <cyg/hal/hal_arbiter.h> //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -#ifdef CYGPKG_HAL_POWERPC_MPC860 // Since the interrupt sources do not have fixed vectors on the 860 // SIU, some arbitration is required. @@ -176,7 +176,6 @@ hal_arbitration_isr_cpm (CYG_ADDRWORD ve return 0; } -#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 externC void hal_variant_IRQ_init(void)
--- a/packages/hal/powerpc/mpc8xx/current/src/var_misc.c +++ b/packages/hal/powerpc/mpc8xx/current/src/var_misc.c @@ -9,7 +9,7 @@ // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// Copyright (C) 2002 Gary Thomas +// Copyright (C) 2002, 2003 Gary Thomas // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -107,20 +107,25 @@ hal_variant_idle_thread_action( cyg_uint // // The MPC8xx CPUs do not have BATs. Fortunately we don't currently // use the MMU, so we can simulate BATs by using the TLBs. + +#if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \ + defined(CYGHWR_HAL_POWERPC_MPC8XX_862P) +#define NUM_TLBS 32 +#elif defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850) +#define NUM_TLBS 8 +#else +#error Missing TLB information for this platform +#endif + int cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, cyg_int32 size, cyg_uint8 flags) { cyg_uint32 epn, rpn, twc, ctr = 0; - int max_tlbs; - -#if defined(CYGPKG_HAL_POWERPC_MPC860) - // There are 32 TLBs. - max_tlbs = 32; -#elif defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) - // There are 8 TLBs. - max_tlbs = 8; -#endif epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV; rpn = ((phys & MI_RPN_RPNMASK) @@ -133,7 +138,7 @@ cyg_hal_map_memory (int id,CYG_ADDRESS v twc |= MI_TWC_G; // Ignore attempts to use more than max_tlbs. - while (id < max_tlbs && size > 0) { + while (id < NUM_TLBS && size > 0) { ctr = id << MI_CTR_INDX_SHIFT; // Instruction TLB. @@ -170,7 +175,6 @@ cyg_hal_map_memory (int id,CYG_ADDRESS v return id; } - // Initialize MMU to a sane (NOP) state. // // Initialize TLBs with 0, Valid bits unset. @@ -179,19 +183,10 @@ cyg_hal_clear_MMU (void) { cyg_uint32 ctr = 0; int id; - int max_tlbs; - -#if defined(CYGPKG_HAL_POWERPC_MPC860) - // There are 32 TLBs. - max_tlbs = 32; -#elif defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850) - // There are 8 TLBs. - max_tlbs = 8; -#endif CYGARC_MTSPR (M_CASID, 0); - for (id = 0; id < max_tlbs; id++) { + for (id = 0; id < NUM_TLBS; id++) { ctr = id << MI_CTR_INDX_SHIFT; // Instruction TLBs.
--- a/packages/hal/powerpc/quicc/current/ChangeLog +++ b/packages/hal/powerpc/quicc/current/ChangeLog @@ -1,3 +1,17 @@ +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * src/quicc_smc1.c: Use new baud rate generator allocation functions. + Merge SMC and SCC output functions. + + * src/cpm.c: Add new function to allocate and manage the baud rate + generators. Used by all serial drivers. + + * include/ppc8xx.h: Some common definitions moved here from various + QUICC serial files. + + * cdl/hal_powerpc_quicc.cdl: Add interface for SCC4 (not implemented + by any platform yet) + 2003-03-20 Gary Thomas <gary@mlbassoc.com> * src/cpm.c (_mpc8xx_allocBd): Improve "best guess" for intial DPRAM
--- a/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl +++ b/packages/hal/powerpc/quicc/current/cdl/hal_powerpc_quicc.cdl @@ -100,12 +100,18 @@ cdl_package CYGPKG_HAL_QUICC { Port SCC3 is available for serial I/O" } + cdl_interface CYGNUM_HAL_QUICC_SCC4 { + display "SCC4 is available for serial I/O" + description " + Port SCC4 is available for serial I/O" + } + compile quicc_smc1.c cpm.c cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { display "Number of communication channels on the board" flavor data - calculated CYGNUM_HAL_QUICC_SMC1+CYGNUM_HAL_QUICC_SMC2+CYGNUM_HAL_QUICC_SCC1+CYGNUM_HAL_QUICC_SCC2+CYGNUM_HAL_QUICC_SCC3 + calculated CYGNUM_HAL_QUICC_SMC1+CYGNUM_HAL_QUICC_SMC2+CYGNUM_HAL_QUICC_SCC1+CYGNUM_HAL_QUICC_SCC2+CYGNUM_HAL_QUICC_SCC3+CYGNUM_HAL_QUICC_SCC4 } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
--- a/packages/hal/powerpc/quicc/current/include/ppc8xx.h +++ b/packages/hal/powerpc/quicc/current/include/ppc8xx.h @@ -936,12 +936,16 @@ static inline EPPC *eppc_base(void) return retval; } +// Function used to reset [only once!] the CPM +__externC void _mpc8xx_reset_cpm(void); // Function used to allocate space in shared memory area // typically used for buffer descriptors, etc. -__externC void _mpc8xx_reset_cpm(void); __externC unsigned short _mpc8xx_allocBd(int len); +// Function used to manage the pool of baud rate generators +__externC unsigned long *_mpc8xx_allocate_brg(int port); + #define QUICC_BD_BASE 0x2000 // Start of shared memory #define QUICC_BD_END 0x3000 // End of shared memory @@ -984,4 +988,52 @@ static inline EPPC *eppc_base(void) #define QUICC_CPM_SCC4 0x00C0 #define QUICC_CPM_SMC2 0x00D0 +// SMC Events (interrupts) +#define QUICC_SMCE_BRK 0x10 // Break received +#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun +#define QUICC_SMCE_TX 0x02 // Tx interrupt +#define QUICC_SMCE_RX 0x01 // Rx interrupt + +// SMC Mode Register +#define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length +#define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2) +#define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable) +#define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even) +#define QUICC_SMCMR_UART (2<<4) // UART mode +#define QUICC_SMCMR_TEN (1<<1) // Enable transmitter +#define QUICC_SMCMR_REN (1<<0) // Enable receiver + +// SMC Commands +#define QUICC_SMC_CMD_InitTxRx (0<<8) +#define QUICC_SMC_CMD_InitTx (1<<8) +#define QUICC_SMC_CMD_InitRx (2<<8) +#define QUICC_SMC_CMD_StopTx (4<<8) +#define QUICC_SMC_CMD_RestartTx (6<<8) +#define QUICC_SMC_CMD_Reset 0x8000 +#define QUICC_SMC_CMD_Go 0x0001 + +// SCC PSMR masks .... +#define QUICC_SCC_PSMR_ASYNC 0x8000 +#define QUICC_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb) +#define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8) +#define QUICC_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled) +#define QUICC_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high) +#define QUICC_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high) + +// SCC DSR masks +#define QUICC_SCC_DSR_FULL 0x7e7e +#define QUICC_SCC_DSR_HALF 0x467e + +// SCC GSMR masks ... +#define QUICC_SCC_GSMR_H_INIT 0x00000060 +#define QUICC_SCC_GSMR_L_INIT 0x00028004 +#define QUICC_SCC_GSMR_L_Tx 0x00000010 +#define QUICC_SCC_GSMR_L_Rx 0x00000020 + +// SCC Events (interrupts) +#define QUICC_SCCE_BRK 0x0040 +#define QUICC_SCCE_BSY 0x0004 +#define QUICC_SCCE_TX 0x0002 +#define QUICC_SCCE_RX 0x0001 + #endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
--- a/packages/hal/powerpc/quicc/current/src/cpm.c +++ b/packages/hal/powerpc/quicc/current/src/cpm.c @@ -56,9 +56,9 @@ #include <pkgconf/hal.h> #include <pkgconf/hal_powerpc_quicc.h> #include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> #include <cyg/hal/hal_arch.h> -#ifdef CYGPKG_HAL_POWERPC_MPC860 // eCos headers decribing PowerQUICC: #include <cyg/hal/quicc/ppc8xx.h> @@ -103,13 +103,136 @@ unsigned short // Most likely not set up - make a guess :-( bd = *nextBd = QUICC_BD_BASE+0x400; } + CYG_ASSERT((len & 0x7) == 0, "BD length must be multiple of 8 bytes"); len = (len + 7) & ~7; // Multiple of 8 bytes *nextBd += len; + CYG_ASSERT(*nextBd < QUICC_BD_END, "Out of buffer descriptors!"); if (*nextBd >= QUICC_BD_END) { *nextBd = QUICC_BD_BASE; } return bd; } -#endif // CYGPKG_HAL_POWERPC_MPC860 +#define BRG_MAX 4 +#define BRG_UNAVAIL -1 +#define BRG_FREE -2 +static unsigned long *brg[BRG_MAX]; // Available generators +static int alloc[BRG_MAX]; // Which port is assigned where + // -1 indicates unavailable + // -2 indicates free + // xx indicates port assignment + +static void +_mpc8xx_mark_brg(int port, int brgnum) +{ + if (brgnum >= BRG_MAX) { + return; // Invalid selection + } + if (alloc[brgnum] == BRG_FREE) { + // Allocation unknown + alloc[brgnum] = port; + } +} + +unsigned long * +_mpc8xx_allocate_brg(int port) +{ + EPPC *eppc = eppc_base(); + static int init = 0; + int brgnum; + + if (!init) { + // Set up available pool +#if defined(CYGHWR_HAL_POWERPC_MPC8XX_852T) + // The 852T variant only has BRG3/BRG4 + alloc[0] = BRG_UNAVAIL; + alloc[1] = BRG_UNAVAIL; +#else + brg[0] = (unsigned long *)&eppc->brgc1; alloc[0] = BRG_FREE; + brg[1] = (unsigned long *)&eppc->brgc2; alloc[1] = BRG_FREE; +#endif + brg[2] = (unsigned long *)&eppc->brgc3; alloc[2] = BRG_FREE; + brg[3] = (unsigned long *)&eppc->brgc4; alloc[3] = BRG_FREE; +#if !defined(CYGSEM_HAL_ROM_MONITOR) + // Figure out how hardware was set by previous ROM monitor +#if CYGNUM_HAL_QUICC_SMC1 > 0 + _mpc8xx_mark_brg(QUICC_CPM_SMC1, (eppc->si_simode >> 12) & 0x07); +#endif +#if CYGNUM_HAL_QUICC_SMC2 > 0 + _mpc8xx_mark_brg(QUICC_CPM_SMC2, (eppc->si_simode >> 28) & 0x07); +#endif +#if CYGNUM_HAL_QUICC_SCC1 > 0 + _mpc8xx_mark_brg(QUICC_CPM_SCC1, (eppc->si_sicr >> 0) & 0x07); +#endif +#if CYGNUM_HAL_QUICC_SCC2 > 0 + _mpc8xx_mark_brg(QUICC_CPM_SCC2, (eppc->si_sicr >> 8) & 0x07); +#endif +#if CYGNUM_HAL_QUICC_SCC3 > 0 + _mpc8xx_mark_brg(QUICC_CPM_SCC3, (eppc->si_sicr >> 16) & 0x07); +#endif +#if CYGNUM_HAL_QUICC_SCC4 > 0 + _mpc8xx_mark_brg(QUICC_CPM_SCC4, (eppc->si_sicr >> 24) & 0x07); +#endif +#endif + init = 1; + } + // Find a free generator (or if port has already been assigned) + for (brgnum = 0; brgnum < BRG_MAX; brgnum++) { + if (alloc[brgnum] >= 0) { + // See if it is for this port + if (alloc[brgnum] == port) { + // It is - just reuse it (already set up) + return brg[brgnum]; + } + } + } + // Not currently assigned, try and find a free one + for (brgnum = 0; brgnum < BRG_MAX; brgnum++) { + if (alloc[brgnum] == BRG_FREE) { + // Allocate to this port. + alloc[brgnum] = port; + break; + } + } + CYG_ASSERT(brgnum < BRG_MAX, "Out of baud rate generators!"); + // If no generator found - punt! + if (brgnum == BRG_MAX) { + brgnum = BRG_MAX-1; + } + // Set up clock routing for new assignment + switch (port) { +#if CYGNUM_HAL_QUICC_SMC1 > 0 + case QUICC_CPM_SMC1: + eppc->si_simode = (eppc->si_simode & ~(0x07<<12)) | (brgnum<<12); + break; +#endif +#if CYGNUM_HAL_QUICC_SMC2 > 0 + case QUICC_CPM_SMC2: + eppc->si_simode = (eppc->si_simode & ~(0x07<<28)) | (brgnum<<28); + break; +#endif +#if CYGNUM_HAL_QUICC_SCC1 > 0 + case QUICC_CPM_SCC1: + eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<0)) | (((brgnum<<3)|(brgnum<<0))<<0); + break; +#endif +#if CYGNUM_HAL_QUICC_SCC2 > 0 + case QUICC_CPM_SCC2: + eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<8)) | (((brgnum<<3)|(brgnum<<0))<<8); + break; +#endif +#if CYGNUM_HAL_QUICC_SCC3 > 0 + case QUICC_CPM_SCC3: + eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<16)) | (((brgnum<<3)|(brgnum<<0))<<16); + break; +#endif +#if CYGNUM_HAL_QUICC_SCC4 > 0 + case QUICC_CPM_SCC4: + eppc->si_sicr = (eppc->si_sicr & ~(0xFF<<24)) | (((brgnum<<3)|(brgnum<<0))<<24); + break; +#endif + } + return brg[brgnum]; +} + // EOF cpm.c
--- a/packages/hal/powerpc/quicc/current/src/quicc_smc1.c +++ b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c @@ -61,8 +61,6 @@ #include <cyg/hal/hal_arch.h> -#ifdef CYGPKG_HAL_POWERPC_MPC860 - // eCos headers decribing PowerQUICC: #include <cyg/hal/quicc/ppc8xx.h> @@ -91,6 +89,7 @@ struct port_info { volatile struct cp_bufdesc *next_rxbd; int irq; // Interrupt state int init; // Has port been initialized? + volatile unsigned long *brg; // Baud rate generator }; static struct port_info ports[] = { @@ -126,12 +125,6 @@ static struct port_info ports[] = { #endif }; -// SMC Events (interrupts) -#define QUICC_SMCE_BRK 0x10 // Break received -#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun -#define QUICC_SMCE_TX 0x02 // Tx interrupt -#define QUICC_SMCE_RX 0x01 // Rx interrupt - /* * Initialize SMCX as a uart. * @@ -164,14 +157,6 @@ cyg_hal_smcx_init_channel(struct port_in eppc->pip_pbpar |= 0xc0; eppc->pip_pbdir &= ~0xc0; - /* Configure baud rate generator (Section 16.13.2) */ - eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); - - /* - * NMSI mode, BRG1 to SMC1 - * (Section 16.12.5.2) - */ - eppc->si_simode = 0; break; #endif #if CYGNUM_HAL_QUICC_SMC2 > 0 @@ -185,18 +170,17 @@ cyg_hal_smcx_init_channel(struct port_in eppc->pio_padir &= ~0xc0; eppc->pio_paodr &= ~0xc0; - /* Configure baud rate generator (Section 16.13.2) */ - eppc->brgc1 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); - - /* - * NMSI mode, BRG1 to SMC2 - * (Section 16.12.5.2) - */ - eppc->si_simode = 0x00000000; break; #endif } + // Set up baud rate generator. These are allocated from a + // pool, based on the port number and type. The allocator + // will arrange to have the selected baud rate clock steered + // to this device. + info->brg = _mpc8xx_allocate_brg(port); + *(info->brg) = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); + /* * Set pointers to buffer descriptors. * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13) @@ -288,7 +272,7 @@ extern int enable_diag_uart; #endif // CYGDBG_DIAG_BUF static void -cyg_hal_smcx_putc(void* __ch_data, cyg_uint8 ch) +cyg_hal_sxx_putc(void* __ch_data, cyg_uint8 ch) { volatile struct cp_bufdesc *bd, *first; EPPC *eppc = eppc_base(); @@ -424,13 +408,13 @@ cyg_hal_sxx_getc(void* __ch_data) static void -cyg_hal_smcx_write(void* __ch_data, const cyg_uint8* __buf, +cyg_hal_sxx_write(void* __ch_data, const cyg_uint8* __buf, cyg_uint32 __len) { CYGARC_HAL_SAVE_GP(); while(__len-- > 0) - cyg_hal_smcx_putc(__ch_data, *__buf++); + cyg_hal_sxx_putc(__ch_data, *__buf++); CYGARC_HAL_RESTORE_GP(); } @@ -608,13 +592,6 @@ cyg_hal_sccx_init_channel(struct port_in eppc->pip_pbpar |= 0x1000; eppc->pip_pbdir |= 0x1000; - /* Configure baud rate generator (Section 16.13.2) */ - eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); - - /* - * NMSI mode, BRG2 to SCC1 - */ - eppc->si_sicr |= (1<<3)|(1<<0); break; #endif #if CYGNUM_HAL_QUICC_SCC2 > 0 @@ -633,13 +610,6 @@ cyg_hal_sccx_init_channel(struct port_in eppc->pip_pbpar |= 0x2000; eppc->pip_pbdir |= 0x2000; - /* Configure baud rate generator (Section 16.13.2) */ - eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); - - /* - * NMSI mode, BRG2 to SCC2 - */ - eppc->si_sicr |= (1<<11)|(1<<8); break; #endif #if CYGNUM_HAL_QUICC_SCC3 > 0 @@ -658,18 +628,17 @@ cyg_hal_sccx_init_channel(struct port_in eppc->pip_pbdir |= 0x00C0; eppc->pip_pbodr &= ~0x00C0; - /* Configure baud rate generator (Section 16.13.2) */ - eppc->brgc4 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); - - /* - * NMSI mode, BRG4 to SCC3 - */ - eppc->si_sicr &= ~(0xFF << 16); - eppc->si_sicr |= (3<<19)|(3<<16); break; #endif } + // Set up baud rate generator. These are allocated from a + // pool, based on the port number and type. The allocator + // will arrange to have the selected baud rate clock steered + // to this device. + info->brg = _mpc8xx_allocate_brg(port); + *(info->brg) = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1); + /* * Set pointers to buffer descriptors. */ @@ -754,57 +723,6 @@ cyg_hal_sccx_init_channel(struct port_in info->irq = 0; } -static void -cyg_hal_sccx_putc(void* __ch_data, cyg_uint8 ch) -{ - volatile struct cp_bufdesc *bd, *first; - EPPC *eppc = eppc_base(); - struct port_info *info = (struct port_info *)__ch_data; - volatile struct uart_pram *uart_pram = (volatile struct uart_pram *)((char *)eppc + info->pram); - CYGARC_HAL_SAVE_GP(); - - /* tx buffer descriptor */ - bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbptr); - - // Scan for a free buffer - first = bd; - while (bd->ctrl & QUICC_BD_CTL_Ready) { - if (bd->ctrl & QUICC_BD_CTL_Wrap) { - bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase); - } else { - bd++; - } - if (bd == first) break; - } - - while (bd->ctrl & QUICC_BD_CTL_Ready) ; // Wait for buffer free - if (bd->ctrl & QUICC_BD_CTL_Int) { - // This buffer has just completed interrupt output. Reset bits - bd->ctrl &= ~QUICC_BD_CTL_Int; - bd->length = 0; - } - - bd->length = 0; - bd->buffer[bd->length++] = ch; - bd->ctrl |= QUICC_BD_CTL_Ready; - - while (bd->ctrl & QUICC_BD_CTL_Ready) ; // Wait until buffer free - - CYGARC_HAL_RESTORE_GP(); -} - -static void -cyg_hal_sccx_write(void* __ch_data, const cyg_uint8* __buf, - cyg_uint32 __len) -{ - CYGARC_HAL_SAVE_GP(); - - while(__len-- > 0) - cyg_hal_sccx_putc(__ch_data, *__buf++); - - CYGARC_HAL_RESTORE_GP(); -} - static int cyg_hal_sccx_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) @@ -877,9 +795,9 @@ cyg_hal_plf_serial_init(void) CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); - CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_smcx_write); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); - CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_smcx_putc); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr); @@ -893,9 +811,9 @@ cyg_hal_plf_serial_init(void) CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); - CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_smcx_write); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); - CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_smcx_putc); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr); @@ -909,9 +827,9 @@ cyg_hal_plf_serial_init(void) CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); - CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); - CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr); @@ -925,9 +843,9 @@ cyg_hal_plf_serial_init(void) CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); - CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); - CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr); @@ -941,9 +859,9 @@ cyg_hal_plf_serial_init(void) CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); - CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sccx_write); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); - CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sccx_putc); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr); @@ -955,5 +873,4 @@ cyg_hal_plf_serial_init(void) CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); } -#endif // CYGPKG_HAL_POWERPC_MPC860 // EOF quicc_smc1.c
--- a/packages/hal/powerpc/ts1000/current/ChangeLog +++ b/packages/hal/powerpc/ts1000/current/ChangeLog @@ -1,3 +1,7 @@ +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * cdl/hal_powerpc_ts1000.cdl: New CDL for setting processor type. + 2002-12-02 Gary Thomas <gthomas@ecoscentric.com> * include/plf_intr.h: Use MPC8xx variant RESET support.
--- a/packages/hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl +++ b/packages/hal/powerpc/ts1000/current/cdl/hal_powerpc_ts1000.cdl @@ -9,7 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## Copyright (C) 2002 Gary Thomas +## Copyright (C) 2002, 2003 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -67,11 +67,13 @@ cdl_package CYGPKG_HAL_POWERPC_TS1000 { implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT implements CYGNUM_HAL_QUICC_SMC1 + requires { CYGHWR_HAL_POWERPC_MPC8XX == "855T" } + define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_ts1000.h>" - puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 855\"" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 855T\"" puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Allied Telesyn TS1000\"" puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" }
--- a/packages/hal/powerpc/viper/current/ChangeLog +++ b/packages/hal/powerpc/viper/current/ChangeLog @@ -1,3 +1,7 @@ +2003-03-23 Gary Thomas <gary@mlbassoc.com> + + * cdl/hal_powerpc_viper.cdl: New CDL for setting processor type. + 2003-03-11 Mark Salter <msalter@redhat.com> * src/redboot_linux_exec.c (do_exec): Call eth_drv_stop as necessary.
--- a/packages/hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl +++ b/packages/hal/powerpc/viper/current/cdl/hal_powerpc_viper.cdl @@ -9,7 +9,7 @@ ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -## Copyright (C) 2002 Gary Thomas +## Copyright (C) 2002, 2003 Gary Thomas ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -68,6 +68,8 @@ cdl_package CYGPKG_HAL_POWERPC_VIPER { implements CYGNUM_HAL_QUICC_SMC1 implements CYGNUM_HAL_QUICC_SCC1 + requires { (CYGHWR_HAL_POWERPC_MPC8XX == "860T") || (CYGHWR_HAL_POWERPC_MPC8XX == "862P") } + define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_viper.h>"
--- a/packages/hal/powerpc/viper/current/misc/redboot_ROMRAM.ecm +++ b/packages/hal/powerpc/viper/current/misc/redboot_ROMRAM.ecm @@ -17,6 +17,7 @@ cdl_configuration eCos { package -hardware CYGPKG_HAL_QUICC current ; package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC current ; package -hardware CYGPKG_DEVS_ETH_POWERPC_FEC current ; + package -hardware CYGPKG_DEVS_ETH_POWERPC_VIPER current ; package -hardware CYGPKG_DEVS_FLASH_VIPER current ; package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; package -template CYGPKG_HAL current ; @@ -25,6 +26,7 @@ cdl_configuration eCos { package -template CYGPKG_ISOINFRA current ; package -template CYGPKG_LIBC_STRING current ; package -template CYGPKG_NS_DNS current ; + package -template CYGPKG_CRC current ; package CYGPKG_IO_FLASH current ; package CYGPKG_IO_ETH_DRIVERS current ; package CYGPKG_COMPRESS_ZLIB current ; @@ -55,6 +57,10 @@ cdl_option CYGSEM_HAL_ROM_MONITOR { inferred_value 1 }; +cdl_component CYGHWR_HAL_POWERPC_MPC8XX { + inferred_value 860T +}; + cdl_component CYG_HAL_STARTUP { user_value ROMRAM };