Mercurial > flash_v2
changeset 1106:d4e3faad8d75
Data cache flush broken on 850.
| author | gthomas |
|---|---|
| date | Tue, 15 Jul 2003 00:58:02 +0000 |
| parents | a8f01385190a |
| children | b7ec9459b80d |
| files | packages/hal/powerpc/mpc8xx/current/ChangeLog packages/hal/powerpc/mpc8xx/current/include/var_cache.h |
| diffstat | 2 files changed, 19 insertions(+), 0 deletions(-) [+] |
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--- a/packages/hal/powerpc/mpc8xx/current/ChangeLog +++ b/packages/hal/powerpc/mpc8xx/current/ChangeLog @@ -1,3 +1,10 @@ +2003-07-14 Gary Thomas <gary@mlbassoc.com> + + * include/var_cache.h: Data cache flush on 850 fails when using + cache SPR commands, so use brute force. This fixes some problems + with network based debugging (RedBoot got lost because of cache + not being flushed properly). + 2003-06-24 Jonathan Larmour <jifl@eCosCentric.com> * include/var_intr.h (cyg_hal_interrupt_acknowledge): Don't
--- a/packages/hal/powerpc/mpc8xx/current/include/var_cache.h +++ b/packages/hal/powerpc/mpc8xx/current/include/var_cache.h @@ -140,6 +140,17 @@ "r" (CYGARC_REG_DC_CMD_IA)) // Synchronize the contents of the cache with memory. +#if defined(CYGHWR_HAL_POWERPC_MPC8XX_850) +// Note: the data cache flush seems to be broken on this chip :-( +#define HAL_DCACHE_SYNC() \ + CYG_MACRO_START \ + cyg_int32 i; \ + cyg_uint32 *__base = (cyg_uint32 *) (0); \ + for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \ + asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0"); \ + } \ + CYG_MACRO_END +#else #define HAL_DCACHE_SYNC() \ CYG_MACRO_START \ cyg_int32 i; \ @@ -159,6 +170,7 @@ /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \ } \ CYG_MACRO_END +#endif // Query the state of the data cache #define HAL_DCACHE_IS_ENABLED(_state_) \