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changeset 974:e432f748c9e1

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* include/idt79rc233x.h (INTR_CLEAR_REG): Define (needed for serial). * include/platform.inc: updated ROMRAM support for gdb. * src/ser16c550c.c (SIO_IER_ERDAI): updated value for errata.
author jlarmour
date Tue, 29 Apr 2003 02:39:30 +0000
parents 468a48fe0e01
children 04b3d562c506
files packages/hal/mips/idt79s334a/current/ChangeLog packages/hal/mips/idt79s334a/current/include/idt79rc233x.h packages/hal/mips/idt79s334a/current/include/platform.inc packages/hal/mips/idt79s334a/current/include/plf_intr.h packages/hal/mips/idt79s334a/current/src/ser16c550c.c
diffstat 5 files changed, 38 insertions(+), 2 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/mips/idt79s334a/current/ChangeLog
+++ b/packages/hal/mips/idt79s334a/current/ChangeLog
@@ -1,3 +1,9 @@
+2003-04-29  Tim Michals  <t.michals@attbi.com>
+
+	* include/idt79rc233x.h (INTR_CLEAR_REG): Define (needed for serial).
+	* include/platform.inc: updated ROMRAM support for gdb.
+	* src/ser16c550c.c (SIO_IER_ERDAI): updated value for errata.
+
 2003-02-13  Tim Michals  <t.michals@attbi.com>
 2003-02-13  Jonathan Larmour  <jifl@eCosCentric.com>
 
--- a/packages/hal/mips/idt79s334a/current/include/idt79rc233x.h
+++ b/packages/hal/mips/idt79s334a/current/include/idt79rc233x.h
@@ -425,6 +425,7 @@
 /* Rc32134 Interrupt controller settings for Uart */
 #define INTR_STATUS_PTR         0xb8000500
 #define INTR_MASK_REG           0xb8000504
+#define INTR_CLEAR_REG          0xb8000508
 
 #define INTR_COM0_REG           0xb8000554
 #define INTR_COM1_REG           0xb8000564
--- a/packages/hal/mips/idt79s334a/current/include/platform.inc
+++ b/packages/hal/mips/idt79s334a/current/include/platform.inc
@@ -45,7 +45,7 @@
 ## Author(s): 	 tmichals
 ## Contributors: nickg
 ## Date:	 2003-02-13
-## Purpose:	 CT1608-IDT32334 board definitions.
+## Purpose:	 IDT32334 board definitions.
 ## Description:	 This file contains various definitions and macros that are
 ##               useful for writing assembly code for the IDT32334 reference
 ##               board.
@@ -164,6 +164,34 @@ 1:
 	bne	t0,t3,1b
 	nop
 
+/* set up and move interrupts */
+
+/* setup and move the vector table into ram */
+/* This allows execptions to happen in ROM first
+** then when running in RAM, they are switched */
+        mfc0    v0, status
+        nop
+        li      v1, ~0x00400000
+        and   v0, v0,v1
+        mtc0    v0, status
+        nop
+
+
+        la      t0, hal_vsr_table
+        la      t1,__default_interrupt_vsr
+
+        sw      t1, 0(t0)
+
+        la      t1,__default_exception_vsr
+        li      t2, 62
+        li      t3, 0
+        addi    t0,t0,4
+12:
+        sw      t1,0(t0)
+        addi    t3,t3,1
+        addi    t0,t0,4
+        bne     t3,t2, 12b
+        nop
 
 	la	v0,2f			# RAM address to go to
 	jr	v0
--- a/packages/hal/mips/idt79s334a/current/include/plf_intr.h
+++ b/packages/hal/mips/idt79s334a/current/include/plf_intr.h
@@ -76,6 +76,7 @@
 // the default for all MIPS variants is to use the 6 bits
 // in the cause register.
 
+// These are only HW interrupts
 #define CYGNUM_HAL_INTERRUPT_0                0
 #define CYGNUM_HAL_INTERRUPT_1                1
 #define CYGNUM_HAL_INTERRUPT_2                2
--- a/packages/hal/mips/idt79s334a/current/src/ser16c550c.c
+++ b/packages/hal/mips/idt79s334a/current/src/ser16c550c.c
@@ -84,7 +84,7 @@
 #define SER_16550_SCR 0x1c   // scratch pad register
 
 // The interrupt enable register bits.
-#define SIO_IER_ERDAI   0x01            // enable received data available irq
+#define SIO_IER_ERDAI   0x04            // enable received data available irq
 #define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
 #define SIO_IER_ELSI    0x04            // enable receiver line status irq
 #define SIO_IER_EMSI    0x08            // enable modem status interrupt