flash_v2: packages/hal/mips/arch/current/include/hal

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 124:0ec04793409a ecos-sw-2000-09-11

Merge from eCos master repository on 2000-09-11-03:00:13-BST

author	jlarmour
date	Mon, 11 Sep 2000 02:42:46 +0000
parents	6bd9d475ed4b
children	6b5f480c6929

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	11 //####COPYRIGHTBEGIN####
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	12 //
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	13 // -------------------------------------------
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	14 // The contents of this file are subject to the Red Hat eCos Public License
66 bf00f99aec69 Merge from eCos master repository on 2000-02-02-19:16:44-GMT jlarmour parents: 64 diff changeset	15 // Version 1.1 (the "License"); you may not use this file except in
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	16 // compliance with the License. You may obtain a copy of the License at
66 bf00f99aec69 Merge from eCos master repository on 2000-02-02-19:16:44-GMT jlarmour parents: 64 diff changeset	17 // http://www.redhat.com/
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	18 //
66 bf00f99aec69 Merge from eCos master repository on 2000-02-02-19:16:44-GMT jlarmour parents: 64 diff changeset	19 // Software distributed under the License is distributed on an "AS IS"
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	21 // License for the specific language governing rights and limitations under
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	22 // the License.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	23 //
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	24 // The Original Code is eCos - Embedded Configurable Operating System,
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	25 // released September 30, 1998.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	26 //
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	27 // The Initial Developer of the Original Code is Red Hat.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	28 // Portions created by Red Hat are
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	30 // All Rights Reserved.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	31 // -------------------------------------------
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	32 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	33 //####COPYRIGHTEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	34 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	35 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	36 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	37 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	38 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	40 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	41 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	42 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	43 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	44 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	45 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	46 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	47 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	48 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	49 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	50 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	52 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	53 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	54
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	55 #include <cyg/hal/var_cache.h>
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	56
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	57 // Use this macro to allow the assembler to accept "cache" instructions,
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	58 // which are MIPS ISA 3. This is useful if someone is compiling
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	59 // with -mips2, but the architecture is really MIPS ISA 3.
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	60
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	61 #define _hal_asm_mips_cpp_stringize( _x_ ) #_x_
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	62 #define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( \
121 6bd9d475ed4b Merge from eCos master repository on 2000-09-04-20:50:20-BST jlarmour parents: 92 diff changeset	63 ".set mips" _hal_asm_mips_cpp_stringize(_isal_) )
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	64
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	65
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	66 //=============================================================================
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	67 // Default Implementation. This uses the standard MIPS CP0 registers and
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	68 // cache instructions. Note that not all variants will have all of the
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	69 // functionality defined here.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	70
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	71 //-----------------------------------------------------------------------------
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	72 // Cache dimensions.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	73 // These really should be defined in var_cache.h. If they are not, then provide
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	74 // a set of numbers that are typical of many variants.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	75
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	76 #ifndef HAL_DCACHE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	77
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	78 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	80 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	81 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	82
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	83 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	87
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	91 #endif
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	92
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 //-----------------------------------------------------------------------------
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	94 // Cache instruction uses LSB to specify which WAY to affect. This macro
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	95 // defines the necessary cache instructions to affect all ways.
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	96 #if (HAL_DCACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	97 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	98 asm volatile ("cache %0,0(%1);" \
124 0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST jlarmour parents: 121 diff changeset	99 : : "I" ((_cmd_) \| 1), "r"(_addr_) )
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	100 #elif (HAL_DCACHE_WAYS == 2)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	101 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	102 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	103 "cache %0,1(%1);" \
124 0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST jlarmour parents: 121 diff changeset	104 : : "I" ((_cmd_) \| 1), "r"(_addr_) )
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	105 #elif (HAL_DCACHE_WAYS == 4)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	106 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	107 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	108 "cache %0,1(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	109 "cache %0,2(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	110 "cache %0,3(%1);" \
124 0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST jlarmour parents: 121 diff changeset	111 : : "I" ((_cmd_) \| 1), "r"(_addr_) )
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	112 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	113 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	114 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	115
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	116 #if (HAL_ICACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	117 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	118 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	119 : : "I" (_cmd_), "r"(_addr_) )
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	120 #elif (HAL_ICACHE_WAYS == 2)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	121 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	122 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	123 "cache %0,1(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	124 : : "I" (_cmd_), "r"(_addr_) )
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	125 #elif (HAL_ICACHE_WAYS == 4)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	126 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	127 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	128 "cache %0,1(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	129 "cache %0,2(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	130 "cache %0,3(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	131 : : "I" (_cmd_), "r"(_addr_) )
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	132 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	133 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	134 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	135
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	136 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139 // Enable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	140 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	141 #ifndef HAL_DCACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	142 #define HAL_DCACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	143 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	144
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	145 // Disable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	146 #ifndef HAL_DCACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	147 #define HAL_DCACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	148 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	149
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	150 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	151 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	152 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	153
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	154 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	155 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	156 // is not quite what we want, but there is no index-invalidate operation
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	157 // available.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	158 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	159 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	160 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	161
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	163 // This uses the index-writeback-invalidate operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	164 #ifndef HAL_DCACHE_SYNC_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	165 #define HAL_DCACHE_SYNC() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	166 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	167 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	168 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	169 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	170 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	171 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	172 { _HAL_ASM_DCACHE_ALL_WAYS(0x01, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	173 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	174 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	175 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	176
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	177 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	178 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	179
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	180 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	181 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	182
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	183 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	184 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	185
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	186 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	187 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	188 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	189 #ifndef HAL_DCACHE_LOCK_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	190 #define HAL_DCACHE_LOCK(_base_, _asize_) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	191 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	192 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	193 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	194 register CYG_WORD _size_ = (_asize_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	195 register CYG_WORD _state_; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	196 HAL_DCACHE_IS_ENABLED( _state_ ); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	197 if( _state_ ) { \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	198 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	199 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	200 { _HAL_ASM_DCACHE_ALL_WAYS(0x1d, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	201 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	202 } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	203 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	204 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	205
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	206 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	207 // Do this by flushing the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	208 #ifndef HAL_DCACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	209 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	210 HAL_DCACHE_FLUSH( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	211 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	212
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	213 // Unlock entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	214 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	215 #define HAL_DCACHE_UNLOCK_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	216 HAL_DCACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	217 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	218
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	222 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	224 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	225
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	227 // for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	228 // This uses the hit-writeback-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	229 #ifndef HAL_DCACHE_FLUSH_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	230 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	231 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	232 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	233 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	234 register CYG_WORD _size_ = (_asize_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	235 register CYG_WORD _state_; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	236 HAL_DCACHE_IS_ENABLED( _state_ ); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	237 if( _state_ ) { \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	238 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	239 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	240 { _HAL_ASM_DCACHE_ALL_WAYS(0x15, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	241 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	242 } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	243 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	244 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	245
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	246 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	247 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	248 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	249 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	250 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	251 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	252 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	253 register CYG_WORD _size_ = (_asize_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	254 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	255 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	256 { _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	257 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	258 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	259 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	260
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	261 // Write dirty cache lines to memory for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	262 // This uses the hit-writeback cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	263 #ifndef HAL_DCACHE_STORE_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	264 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	265 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	266 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	267 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	268 register CYG_WORD _size_ = (_asize_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	269 register CYG_WORD _state_; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	270 HAL_DCACHE_IS_ENABLED( _state_ ); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	271 if( _state_ ) { \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	272 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	273 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	274 { _HAL_ASM_DCACHE_ALL_WAYS(0x19, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	275 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	276 } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	277 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	278 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	279
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	280 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	281 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	282 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	283
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	284 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	285 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	286 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	287
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	288 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	289 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	290
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	291 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	292 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	293
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	294 // Enable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	295 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	296 #ifndef HAL_ICACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	297 #define HAL_ICACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	298 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	299
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300 // Disable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	301 #ifndef HAL_ICACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	302 #define HAL_ICACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	303 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	304
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	305 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	306 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	307 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	308
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	309 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	310 // This uses the index-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	311 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	312 #define HAL_ICACHE_INVALIDATE_ALL() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	313 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	314 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	315 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	316 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	317 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	318 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	319 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	320 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	321 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	322
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	323 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	324 // Simply force the cache to reload.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	325 #ifndef HAL_ICACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	326 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	327 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	328
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	329 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	330 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	331
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	332 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	333 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	334 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	335 #ifndef HAL_ICACHE_LOCK_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	336 #define HAL_ICACHE_LOCK(_base_, _asize_) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	337 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	338 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	339 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	340 register CYG_WORD _size_ = (_asize_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	341 register CYG_WORD _state_; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	342 HAL_ICACHE_IS_ENABLED( _state_ ); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	343 if( _state_ ) { \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	344 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	345 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	346 { _HAL_ASM_ICACHE_ALL_WAYS(0x1c, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	347 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	348 } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	349 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	350 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	351
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	352 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	353 // Do this by invalidating the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	354 #ifndef HAL_ICACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	355 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	356 HAL_ICACHE_INVALIDATE( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	357 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	358
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	359 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	360 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	361
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	362 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	363 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	364
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	365 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	366 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	367 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	368 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	369 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	370 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	371 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	372 register CYG_WORD _size_ = (_asize_); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	373 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	374 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	375 { _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	376 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	377 CYG_MACRO_END
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	378 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	379
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	380 //-----------------------------------------------------------------------------
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	381 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	382
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	383 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	384
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	385 #error Unsupported MIPS configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	386
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	387 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	388
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	389 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	390 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	391 // End of hal_cache.h

Mercurial > flash_v2

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 124:0ec04793409a ecos-sw-2000-09-11