flash_v2: packages/hal/mips/arch/current/include/hal

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 464:bac0bf105669

Fix cache macros, which could go wrong if the base address was not on a cacheline boundary.

author	bartv
date	Sun, 15 Dec 2002 21:27:39 +0000
parents	d2c90368aeef
children	ea74d0ea9eb1

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	11 //####ECOSGPLCOPYRIGHTBEGIN####
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	12 // -------------------------------------------
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	13 // This file is part of eCos, the Embedded Configurable Operating System.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	15 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	16 // eCos is free software; you can redistribute it and/or modify it under
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	17 // the terms of the GNU General Public License as published by the Free
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	18 // Software Foundation; either version 2 or (at your option) any later version.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	19 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	23 // for more details.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	24 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	25 // You should have received a copy of the GNU General Public License along
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	26 // with eCos; if not, write to the Free Software Foundation, Inc.,
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	28 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	29 // As a special exception, if other files instantiate templates or use macros
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	30 // or inline functions from this file, or you compile this file and link it
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	31 // with other works to produce a work based on this file, this file does not
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	32 // by itself cause the resulting work to be covered by the GNU General Public
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	33 // License. However the source code for this file must still be made available
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	34 // in accordance with section (3) of the GNU General Public License.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	35 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	36 // This exception does not invalidate any other reasons why a work based on
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	37 // this file might be covered by the GNU General Public License.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	38 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
210 d2c90368aeef Merge from eCos master repository on 2002-05-23-21:39:14-BST jlarmour parents: 208 diff changeset	40 // at http://sources.redhat.com/ecos/ecos-license/
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	41 // -------------------------------------------
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	42 //####ECOSGPLCOPYRIGHTEND####
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	43 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	44 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	45 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	46 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	47 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	48 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	49 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	50 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	52 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	53 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	54 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	55 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	56 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	57 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	58 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	60
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	61 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	62 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	63
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	64 #include <cyg/hal/var_cache.h>
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	65
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	66 // Use this macro to allow the assembler to accept "cache" instructions,
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	67 // which are MIPS ISA 3. This is useful if someone is compiling
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	68 // with -mips2, but the architecture is really MIPS ISA 3.
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	69
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	70 #define _hal_asm_mips_cpp_stringize( _x_ ) #_x_
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	71 #define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( \
121 6bd9d475ed4b Merge from eCos master repository on 2000-09-04-20:50:20-BST jlarmour parents: 92 diff changeset	72 ".set mips" _hal_asm_mips_cpp_stringize(_isal_) )
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	73
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	74
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75 //=============================================================================
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	76 // Default Implementation. This uses the standard MIPS CP0 registers and
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	77 // cache instructions. Note that not all variants will have all of the
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	78 // functionality defined here.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	80 //-----------------------------------------------------------------------------
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	81 // Cache dimensions.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	82 // These really should be defined in var_cache.h. If they are not, then provide
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	83 // a set of numbers that are typical of many variants.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	84
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	85 #ifndef HAL_DCACHE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	87 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	91
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	92 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	100 #endif
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	101
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	102 //-----------------------------------------------------------------------------
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	103 // Cache instruction uses LSBs or MSBs (depending on the
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	104 // implementation) of the virtual address to specify which WAY to
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	105 // affect. The _ALL_WAYS macro defines the necessary cache instructions
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	106 // to affect all ways.
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	107
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	108 #ifdef HAL_MIPS_CACHE_INSN_USES_LSB
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	109 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS+(_n_))
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	110 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS+(_n_))
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	111 #else
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	112 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS)
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	113 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS)
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	114 #endif
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	115
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	116 #if (HAL_DCACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	117 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	118 asm volatile ("cache %0,0(%1);" \
124 0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST jlarmour parents: 121 diff changeset	119 : : "I" ((_cmd_) \| 1), "r"(_addr_) )
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	120 #elif (HAL_DCACHE_WAYS == 2)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	121 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	122 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	123 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	124 : : "I" ((_cmd_) \| 1), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	125 "I" (_DWAY(1)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	126 #elif (HAL_DCACHE_WAYS == 4)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	127 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	128 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	129 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	130 "cache %0,%3(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	131 "cache %0,%4(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	132 : : "I" ((_cmd_) \| 1), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	133 "I" (_DWAY(1)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	134 "I" (_DWAY(2)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	135 "I" (_DWAY(3)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	136 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	137 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	138 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	139
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	140 #if (HAL_ICACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	141 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	142 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	143 : : "I" (_cmd_), "r"(_addr_) )
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	144 #elif (HAL_ICACHE_WAYS == 2)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	145 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	146 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	147 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	148 : : "I" (_cmd_), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	149 "I" (_IWAY(1)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	150 #elif (HAL_ICACHE_WAYS == 4)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	151 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	152 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	153 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	154 "cache %0,%3(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	155 "cache %0,%4(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	156 : : "I" (_cmd_), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	157 "I" (_IWAY(1)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	158 "I" (_IWAY(2)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	159 "I" (_IWAY(3)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	160 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	161 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	162 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	163
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	164 //-----------------------------------------------------------------------------
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	165 // Address adjustment.
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	166 // Given an address and a size, these macros return the first
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	167 // cacheline containing the requested range and a terminating address.
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	168
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	169 #define HAL_DCACHE_START_ADDRESS(_addr_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	170 (((CYG_ADDRESS)(_addr_)) & ~(HAL_DCACHE_LINE_SIZE-1))
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	171
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	172 #define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	173 ((CYG_ADDRESS)((_addr_) + (_asize_)))
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	174
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	175 #define HAL_ICACHE_START_ADDRESS(_addr_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	176 (((CYG_ADDRESS)(_addr_)) & ~(HAL_ICACHE_LINE_SIZE-1))
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	177
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	178 #define HAL_ICACHE_END_ADDRESS(_addr_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	179 ((CYG_ADDRESS)((_addr_) + (_asize_)))
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	180
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	181 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	182 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	183
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	184 // Enable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	185 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	186 #ifndef HAL_DCACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	187 #define HAL_DCACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	188 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	189
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	190 // Disable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	191 #ifndef HAL_DCACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	192 #define HAL_DCACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	193 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	194
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	195 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	196 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	197 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	198
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	199 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	200 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	201 // is not quite what we want, but there is no index-invalidate operation
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	202 // available.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	203 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	204 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	205 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	206
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	207 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	208 // This uses the index-writeback-invalidate operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	209 #ifndef HAL_DCACHE_SYNC_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	210 #define HAL_DCACHE_SYNC() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	211 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	212 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	213 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	214 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	215 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	216 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	217 { _HAL_ASM_DCACHE_ALL_WAYS(0x01, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	218 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	219 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	220 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	222 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	224
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	225 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	227
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	228 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	229 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	230
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	231 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	232 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	233 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	234 #ifndef HAL_DCACHE_LOCK_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	235 #define HAL_DCACHE_LOCK(_base_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	236 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	237 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	238 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	239 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	240 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	241 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	242 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	243 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	244 { _HAL_ASM_DCACHE_ALL_WAYS(0x1d, _addr_); } \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	245 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	246 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	247 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	248 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	249
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	250 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	251 // Do this by flushing the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	252 #ifndef HAL_DCACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	253 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	254 HAL_DCACHE_FLUSH( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	255 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	256
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	257 // Unlock entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	258 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	259 #define HAL_DCACHE_UNLOCK_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	260 HAL_DCACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	261 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	262
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	263 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	264 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	265
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	266 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	269
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	270 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	271 // for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	272 // This uses the hit-writeback-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	273 #ifndef HAL_DCACHE_FLUSH_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	274 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	275 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	276 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	277 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	278 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	279 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	280 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	281 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	282 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	283 { _HAL_ASM_DCACHE_ALL_WAYS(0x15, _addr_); } \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	284 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	285 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	286 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	287 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	288
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	289 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	290 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	291 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	292 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	293 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	294 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	295 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	296 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	297 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	298 { _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); } \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	299 _HAL_ASM_SET_MIPS_ISA(0); \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	300 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	301 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	302
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	303 // Write dirty cache lines to memory for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	304 // This uses the hit-writeback cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	305 #ifndef HAL_DCACHE_STORE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	306 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	307 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	308 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	309 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	310 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	311 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	312 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	313 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	314 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	315 { _HAL_ASM_DCACHE_ALL_WAYS(0x19, _addr_); } \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	316 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	317 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	318 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	319 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	320
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	321 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	322 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	323 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	324
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	326 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	327 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	328
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	329 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	330 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	331
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	332 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	333 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	334
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	335 // Enable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	336 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	337 #ifndef HAL_ICACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	338 #define HAL_ICACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	339 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	340
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	341 // Disable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	342 #ifndef HAL_ICACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	343 #define HAL_ICACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	344 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	345
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	346 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	347 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	348 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	349
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	350 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	351 // This uses the index-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	352 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	353 #define HAL_ICACHE_INVALIDATE_ALL() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	354 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	355 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	356 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	357 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	358 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	359 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	360 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	361 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	362 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	363
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	364 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	365 // Simply force the cache to reload.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	366 #ifndef HAL_ICACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	367 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	368 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	369
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	370 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	371 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	372
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	373 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	374 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	375 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	376 #ifndef HAL_ICACHE_LOCK_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	377 #define HAL_ICACHE_LOCK(_base_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	378 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	379 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	380 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	381 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	382 HAL_ICACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	383 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	384 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	385 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	386 { _HAL_ASM_ICACHE_ALL_WAYS(0x1c, _addr_); } \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	387 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	388 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	389 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	390 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	391
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	392 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	393 // Do this by invalidating the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	394 #ifndef HAL_ICACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	395 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	396 HAL_ICACHE_INVALIDATE( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	397 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	398
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	399 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	400 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	401
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	402 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	403 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	404
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	405 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	406 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	407 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	408 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	409 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	410 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	411 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	412 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	413 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	414 { _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); } \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	415 _HAL_ASM_SET_MIPS_ISA(0); \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	416 CYG_MACRO_END
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	417 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	418
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	419 //-----------------------------------------------------------------------------
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	420 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	421
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	422 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	423
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	424 #error Unsupported MIPS configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	425
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	426 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	427
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	428 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	429 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	430 // End of hal_cache.h

Mercurial > flash_v2

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 464:bac0bf105669